High-Q CMOS LC Pseudo Switched-Capacitor ... - Semantic Scholar
High-Q CMOS LC Pseudo Switched-Capacitor Bandpass Filter with Center Frequency Tuning Ahmed El Oualkadi, David Cordeau* and Jean-Marie Paillot* Microelectronics laboratory, Electrical Engineering Department, Université Catholique de Louvain 3, Place du Levant, 1348 Louvain-la-Neuve, Belgium [email protected] * LAII-ESIP, Université de Poitiers, 4, avenue de Varsovie, 16021 Angoulême Cedex, France
Abstract—The design of a new high-Q LC pseudo switchedcapacitor bandpass filter is presented. The proposed filter is tuned by using a command circuit made up by a ring voltage controlled oscillator (VCO) with ‘XOR’ gates. Fabricated in a standard 0.35 µm CMOS, this circuit is intended to replace the SAW filters in wireless broadband applications. Measured results demonstrate interesting performances; a tunable center frequency range of 285 MHz [240–525 MHz] and a quality factor that can be as high as 300 within the tunable frequency range.
I.
INTRODUCTION
Fig. 1. Classical switched-capacitor filter architecture.
Recent years have seen the rapid proliferation of wireless applications circuits and systems [1, 2]. Wireless transceivers are an increasingly important commercial application. The current transceiver solutions often use low cost CMOS for digital and baseband circuitry, while reserving silicon bipolar or GaAs for critical RF circuits. While this is good for optimizing the performance of individual subsystems, it is costly and makes full transceiver integration very difficult. Discrete passive components commonly used in today’s transceivers (e.g. SAW filters and high-Q resonators) enable excellent filtering and ease generation of spectral pure signals, but they are often bulky and expensive. In addition, while the fixed frequency characteristics of these components are ideal for single-standard transceivers, they are inflexible and generally not as well suited for systems requiring multi-standard adaptation. In this context, promising prospects can be profiled for the switched capacitor (SC) filters [3]. These filters present very interesting advantages in particular a very high selectivity associated with the possibility of adjustment of the center frequency by an internal or external clock signal. This characteristic is more significant for the RF integrated circuits, for which the tuning of the center frequency by a clock signal permits either to compensate the dispersions due to the technology used, or to filter various channels with the same filter. This paper proposes the design of a new high-Q LC pseudo switched-capacitor bandpass filter tunable over a
0-7803-9390-2/06/$20.00 ©2006 IEEE
broad frequency band for wireless applications. The original topology of the proposed filter is based on the modification of the basic cell of the well-known scheme of N-path switched-capacitor filter [4, 5]. II.
PROPOSED FILTER TOPOLOGY
A.
Classical switched-capacitor filter topology Fig. 1 shows the architecture of the classical switchedcapacitor filter, which uses a first-order RC low-pass filter as basic cell. This simplified topology shows the same behavior as N-path switched-capacitor filters [6]. In this case, the switches are activated successively by the To periodic command signals which are delayed by the same duration To/N. If the command signals of the switches are supposed to be ideal Dirac impulses delayed by To/N, then the output expression Vs(f) according to the input signal Ve(f), can be written as : +∞
Vs(f) =
∑ Ve(qTo/N). q =-∞
e - 2 πjfqTo/N .
+∞
∑ h(mTo).e
- 2 π jfmTo
(1)
m =-∞
This expression shows that the output signal is the result of two multiplied sums. The first one corresponds to the
3906
ISCAS 2006
number seems to be an acceptable limit of the complexity of realization on-chip. Fig. 2-b shows the proposed architecture of a LC pseudo switched-capacitor filter. The main advantages of this novel architecture are both to reduce the thermal noise figure due to the input resistor and to improve the quality factor according to input inductor value. Furthermore, this new configuration will allow a good dynamic range due to the second-order behavior brought by the new basic cell. III.
(a)
A. Circuit design
Basic cell C
C
x1 L
CIRCUIT DESIGN AND SIMULATION RESULTS
C
x2
The filter switches were produced with N channel MOSFETs transistors, which are switching sequentially between the ON and OFF modes. The first critical design limitation is the choice of the switching transistors size. Indeed, a compromise about the transistor size gate was found [8], it consists in using a N channel MOSFETs of respectively a gate width and length equal to 6 x 25 µm and 0.35 µm.
C
x3
x4
RL x5
x6
C
x7
C
x8
C
C
RL: Low resistor used to simulate the inductor losses. (b) Fig. 2. Proposed LC pseudo switched-capactor filter architecture.
input signal Fourier transform sampled with a period equal to To/N, while, the second one corresponds to the impulse response Fourier transform of the basic cell (RC low-pass filter) sampled with a period equal to To. Hence, the global transfer function presents a succession of bandwidth at the fundamental frequency Fo and all command signal harmonics. Then, this filter (Fig. 1) can be used for clock recovering by filtering the harmonic components [7]. It can also be employed as bandpass filter centered around Fo. This last application will be discussed in this paper. The noise factor generated mainly by the input resistor seemed to be a penalizing element for the use of this classical filter topology. For this raison, a novel architecture is proposed in this paper. B. Proposed LC pseudo switched-capacitor filter topology This novel topology is based in the modification of a basic cell (RC low-pass filter) of the classical architecture. The new basic cell is formed by a second-order LC low-pass filter (Fig. 2-a). A trade-off has been found concerning the number of branches of these switched capacitors. Indeed, if a significant number of branches would permit to improve the filter performances, on the other hand it would lead quickly to an excessive complexity of the design [8]. The compromise retained for this study is eight branches; this
The command circuit has long been the main difficulty to make a more advanced RF study of this kind of filter. The classical solution is generally carried out using a shift register. This solution which requires a clock frequency equal to the filter center frequency multiplied by the number of branches to commutate can be exclusively used at low frequencies. Recently, a new solution [8] which consists in using a command circuit made up by a ring voltage controlled oscillator (VCO) with "XOR" gates has been proposed. The original association of such command circuit with the proposed filters presents significant advantages especially the reduction of command signal frequency (switching frequency) compared to a low frequency solution by a shift register [8]. Moreover, this association can make this type of filters more attractive for designers. Simulations realized with the novel topology (LC pseudo switched-capacitor filter), show the same transfer characteristic behavior as the classical filter. B. Simulation results Fig. 3 shows the simulated voltage gain magnitude versus frequency with a switching frequency Fo equal to 500 MHz, for LC pseudo switched-capacitor filter. For these global circuit simulations, all the parasitic effects are taken into account. Fig. 3 shows an optimal dynamic range of 35 dB is obtained which is comprised between 8 dB voltage gain in the band and –27 dB in the rejection band. Table I summarizes the main simulation results. This new design presents an adjustable simulated center frequency ranging between 240 MHz and 525.MHz with a simulated Q-factor value which is better than 300 within the tunable frequency band. These simulation results show that the dynamic range and the voltage gain are strongly improved by using the inductor.
3907
Fig. 4. Microphotograph of the fabricated LC pseudo switched-capacitor bandpass filter and its command circuit.
Fig. 3. Simulated voltage gain for the proposed filter obtained with 500 MHz switching frequency, L=100nH, RL=10Ω and C=50pF.
TABLE I SUMMARY OF THE SIMULATION RESULTS classical filter [8]
Proposed filter
Voltage supply (V)
3
3
Current consumption (mA)
26
20
320-500
240-525
0.9
0.9
Insertion loss @ Fo (dB)
2.5
-11
Dynamic range (dB)
25.5
35
1dB Input compression point @ Fo (dBm)
-5
-3
Noise figure @ Fo (dB)
12
7
Parameters
Tuning frequency range (MHz) -3dB Frequency bandwidth @ Fo (MHz)
IV.
IMPLEMENTATION AND MEASURED RESULTS
The proposed LC pseudo switched-capacitor filter with its command circuit made up by a ring voltage controlled oscillator with XOR gates is made up by using a standard 0.35 µm CMOS technology. The corresponding die microphotograph is shown in Fig. 4, and the chip area is 1.1 x 1.75 mm2. For this prototype, the input component is not integrated on-chip. Thus it is possible to place resistor or inductor at the filter input. In these conditions, the input must be matched by external components. This matching takes in toaccount the characteristics of the plastic small outline package (SO14). Fig. 5 illustrates the measured S21 obtained with the LC pseudo switched-capacitor filter (L = 100 nH) for a
Fig. 5. Measured S21 of the proposed filter (L = 100nH) for a switching frequency close to 513 MHz.
switching frequency close to 513 MHz. The obtained measurements with this filter at a switching frequency close to 513 MHz show interesting performances, the bandwidth is equal to 1.7 MHz and the quality factor is roughly 300. For a higher dynamic range 34 dB than the classical filter. Fig. 6 shows the possibility of tuning the center frequency, the S21 measurements are shown for variable
3908
TABLE II SUMMARY OF THE MEASURED RESULTS classical filter
Parameters
Proposed filter
Voltage supply (V)
3
3
Current consumption (mA)
25
21
-3dB Frequency bandwidth @ Fo (MHz)
4.7
1.7
Quality factor
111
308
Insertion loss @ Fo (dB)
3.9
2
Dynamic range (dB)
20
34
1dB Input compression point @ Fo (dBm)
-9
-4
ACKNOWLEDGMENT The authors wish to thank the Professor Denis Flandre from the Université Catholique de Louvain, Belgium, for the helpful comments. Fig. 6. Measured S21 of the proposed filter (L = 100nH) for various switching frequencies.
REFERENCES [1]
switching frequencies. The proposed filter is tunable over a broad frequency band in the RF range by using a ring VCO. The achieved results show a tunable center frequency band of 285 MHz [240–525 MHz], with a quality factor that can achieve a maximum value higher than 300. The measured results at 525 MHz center frequencies are summarized in Table II. For higher frequencies applications, a CMOS technology with a higher fT (frequency transition) will be suitable to enhance the performance of this circuit. V.
[2]
[3]
[4]
[5]
CONCLUSION
A new filter topology has been proposed and studied; this novel structure presents a high performance compared to the classical one particularly in the noise factor and dynamic range. The design of the proposed filter has been discussed, and the first measured results have been presented, these measurements confirm the interest of this design. This original circuit could substitute some SAW filters in wireless broadband applications.
[6]
[7]
[8]
3909
P. J. Chang, A. Rofougaran, and A. A. Abidi “A CMOS channelselect filter for a direct-conversion wireless receiver” IEEE J. SolidState Circuits, vol. 32, no. 5, pp. 722-729, May 1997. A. Yoshizawa and Y. P. Tsividis “Anti-blocker design techniques for MOSFET-C filters for direct conversion receivers” IEEE J. SolidState Circuits, vol. 37, no. 3, pp. 357-364, March 2002. C. Toumazou, D. G. Haigh, S. J. Harrold, S. J. Steptoe, J. I. Sewell, and R. Bayruns, “400 MHz switching rate GaAs switched capacitor filter,” IEE Electronics Letters, vol.26, pp. 460-461, 1990. J.C. Nallatamby, M. Bridier, M. Prigent, and J. Obregon, “Switched capacitors and sampled circuit by harmonic balance and related techniques,” IEE Electronics Letters, vol. 27, pp. 2364-2367, 1991. U. Kleine, W. Brockherde, A. Fettweis, B. J. Hosticka, J. Pandel and G. Zimmer, “An integrated six-path wave-SC filter”, IEEE J. of Solid State Circuits, vol. SC-20, no. 2, pp. 632-640, April 1985. H. Wupper, “A modified N-path filter suited for practical realization,” IEEE Trans. on Circuits and Systems, vol. 21, pp. 449-456, May 1974. B. Lai and R. C. Walker, “A monolithic 622 Mb/s clock extraction data retiming circuit,” in ISSCC Dig. Tech. Papers, Feb. 1993, pp. 144–144. A. El Oualkadi, J.M. Paillot, H. Guegnaud and R. Allam, “CMOS RF switched-capacitor bandpass filter tuned by ring VCO”, International Journal of Electronics and Communications, AEÜ, Elsevier, vol.59, issue no.6, pp.352-358, 15 September 2005.
Abstract—The design of a new high-Q LC pseudo switchedcapacitor bandpass filter is presented. The proposed filter is tuned by using a command circuit made up by a ring voltage controlled oscillator (VCO) with ‘XOR’ gates. Fabricated in a standard 0.35 µm CMOS, this circuit is intended to replace the SAW filters in wireless broadband applications. Measured results demonstrate interesting performances; a tunable center frequency range of 285 MHz [240–525 MHz] and a quality factor that can be as high as 300 within the tunable frequency range.
I.
INTRODUCTION
Fig. 1. Classical switched-capacitor filter architecture.
Recent years have seen the rapid proliferation of wireless applications circuits and systems [1, 2]. Wireless transceivers are an increasingly important commercial application. The current transceiver solutions often use low cost CMOS for digital and baseband circuitry, while reserving silicon bipolar or GaAs for critical RF circuits. While this is good for optimizing the performance of individual subsystems, it is costly and makes full transceiver integration very difficult. Discrete passive components commonly used in today’s transceivers (e.g. SAW filters and high-Q resonators) enable excellent filtering and ease generation of spectral pure signals, but they are often bulky and expensive. In addition, while the fixed frequency characteristics of these components are ideal for single-standard transceivers, they are inflexible and generally not as well suited for systems requiring multi-standard adaptation. In this context, promising prospects can be profiled for the switched capacitor (SC) filters [3]. These filters present very interesting advantages in particular a very high selectivity associated with the possibility of adjustment of the center frequency by an internal or external clock signal. This characteristic is more significant for the RF integrated circuits, for which the tuning of the center frequency by a clock signal permits either to compensate the dispersions due to the technology used, or to filter various channels with the same filter. This paper proposes the design of a new high-Q LC pseudo switched-capacitor bandpass filter tunable over a
0-7803-9390-2/06/$20.00 ©2006 IEEE
broad frequency band for wireless applications. The original topology of the proposed filter is based on the modification of the basic cell of the well-known scheme of N-path switched-capacitor filter [4, 5]. II.
PROPOSED FILTER TOPOLOGY
A.
Classical switched-capacitor filter topology Fig. 1 shows the architecture of the classical switchedcapacitor filter, which uses a first-order RC low-pass filter as basic cell. This simplified topology shows the same behavior as N-path switched-capacitor filters [6]. In this case, the switches are activated successively by the To periodic command signals which are delayed by the same duration To/N. If the command signals of the switches are supposed to be ideal Dirac impulses delayed by To/N, then the output expression Vs(f) according to the input signal Ve(f), can be written as : +∞
Vs(f) =
∑ Ve(qTo/N). q =-∞
e - 2 πjfqTo/N .
+∞
∑ h(mTo).e
- 2 π jfmTo
(1)
m =-∞
This expression shows that the output signal is the result of two multiplied sums. The first one corresponds to the
3906
ISCAS 2006
number seems to be an acceptable limit of the complexity of realization on-chip. Fig. 2-b shows the proposed architecture of a LC pseudo switched-capacitor filter. The main advantages of this novel architecture are both to reduce the thermal noise figure due to the input resistor and to improve the quality factor according to input inductor value. Furthermore, this new configuration will allow a good dynamic range due to the second-order behavior brought by the new basic cell. III.
(a)
A. Circuit design
Basic cell C
C
x1 L
CIRCUIT DESIGN AND SIMULATION RESULTS
C
x2
The filter switches were produced with N channel MOSFETs transistors, which are switching sequentially between the ON and OFF modes. The first critical design limitation is the choice of the switching transistors size. Indeed, a compromise about the transistor size gate was found [8], it consists in using a N channel MOSFETs of respectively a gate width and length equal to 6 x 25 µm and 0.35 µm.
C
x3
x4
RL x5
x6
C
x7
C
x8
C
C
RL: Low resistor used to simulate the inductor losses. (b) Fig. 2. Proposed LC pseudo switched-capactor filter architecture.
input signal Fourier transform sampled with a period equal to To/N, while, the second one corresponds to the impulse response Fourier transform of the basic cell (RC low-pass filter) sampled with a period equal to To. Hence, the global transfer function presents a succession of bandwidth at the fundamental frequency Fo and all command signal harmonics. Then, this filter (Fig. 1) can be used for clock recovering by filtering the harmonic components [7]. It can also be employed as bandpass filter centered around Fo. This last application will be discussed in this paper. The noise factor generated mainly by the input resistor seemed to be a penalizing element for the use of this classical filter topology. For this raison, a novel architecture is proposed in this paper. B. Proposed LC pseudo switched-capacitor filter topology This novel topology is based in the modification of a basic cell (RC low-pass filter) of the classical architecture. The new basic cell is formed by a second-order LC low-pass filter (Fig. 2-a). A trade-off has been found concerning the number of branches of these switched capacitors. Indeed, if a significant number of branches would permit to improve the filter performances, on the other hand it would lead quickly to an excessive complexity of the design [8]. The compromise retained for this study is eight branches; this
The command circuit has long been the main difficulty to make a more advanced RF study of this kind of filter. The classical solution is generally carried out using a shift register. This solution which requires a clock frequency equal to the filter center frequency multiplied by the number of branches to commutate can be exclusively used at low frequencies. Recently, a new solution [8] which consists in using a command circuit made up by a ring voltage controlled oscillator (VCO) with "XOR" gates has been proposed. The original association of such command circuit with the proposed filters presents significant advantages especially the reduction of command signal frequency (switching frequency) compared to a low frequency solution by a shift register [8]. Moreover, this association can make this type of filters more attractive for designers. Simulations realized with the novel topology (LC pseudo switched-capacitor filter), show the same transfer characteristic behavior as the classical filter. B. Simulation results Fig. 3 shows the simulated voltage gain magnitude versus frequency with a switching frequency Fo equal to 500 MHz, for LC pseudo switched-capacitor filter. For these global circuit simulations, all the parasitic effects are taken into account. Fig. 3 shows an optimal dynamic range of 35 dB is obtained which is comprised between 8 dB voltage gain in the band and –27 dB in the rejection band. Table I summarizes the main simulation results. This new design presents an adjustable simulated center frequency ranging between 240 MHz and 525.MHz with a simulated Q-factor value which is better than 300 within the tunable frequency band. These simulation results show that the dynamic range and the voltage gain are strongly improved by using the inductor.
3907
Fig. 4. Microphotograph of the fabricated LC pseudo switched-capacitor bandpass filter and its command circuit.
Fig. 3. Simulated voltage gain for the proposed filter obtained with 500 MHz switching frequency, L=100nH, RL=10Ω and C=50pF.
TABLE I SUMMARY OF THE SIMULATION RESULTS classical filter [8]
Proposed filter
Voltage supply (V)
3
3
Current consumption (mA)
26
20
320-500
240-525
0.9
0.9
Insertion loss @ Fo (dB)
2.5
-11
Dynamic range (dB)
25.5
35
1dB Input compression point @ Fo (dBm)
-5
-3
Noise figure @ Fo (dB)
12
7
Parameters
Tuning frequency range (MHz) -3dB Frequency bandwidth @ Fo (MHz)
IV.
IMPLEMENTATION AND MEASURED RESULTS
The proposed LC pseudo switched-capacitor filter with its command circuit made up by a ring voltage controlled oscillator with XOR gates is made up by using a standard 0.35 µm CMOS technology. The corresponding die microphotograph is shown in Fig. 4, and the chip area is 1.1 x 1.75 mm2. For this prototype, the input component is not integrated on-chip. Thus it is possible to place resistor or inductor at the filter input. In these conditions, the input must be matched by external components. This matching takes in toaccount the characteristics of the plastic small outline package (SO14). Fig. 5 illustrates the measured S21 obtained with the LC pseudo switched-capacitor filter (L = 100 nH) for a
Fig. 5. Measured S21 of the proposed filter (L = 100nH) for a switching frequency close to 513 MHz.
switching frequency close to 513 MHz. The obtained measurements with this filter at a switching frequency close to 513 MHz show interesting performances, the bandwidth is equal to 1.7 MHz and the quality factor is roughly 300. For a higher dynamic range 34 dB than the classical filter. Fig. 6 shows the possibility of tuning the center frequency, the S21 measurements are shown for variable
3908
TABLE II SUMMARY OF THE MEASURED RESULTS classical filter
Parameters
Proposed filter
Voltage supply (V)
3
3
Current consumption (mA)
25
21
-3dB Frequency bandwidth @ Fo (MHz)
4.7
1.7
Quality factor
111
308
Insertion loss @ Fo (dB)
3.9
2
Dynamic range (dB)
20
34
1dB Input compression point @ Fo (dBm)
-9
-4
ACKNOWLEDGMENT The authors wish to thank the Professor Denis Flandre from the Université Catholique de Louvain, Belgium, for the helpful comments. Fig. 6. Measured S21 of the proposed filter (L = 100nH) for various switching frequencies.
REFERENCES [1]
switching frequencies. The proposed filter is tunable over a broad frequency band in the RF range by using a ring VCO. The achieved results show a tunable center frequency band of 285 MHz [240–525 MHz], with a quality factor that can achieve a maximum value higher than 300. The measured results at 525 MHz center frequencies are summarized in Table II. For higher frequencies applications, a CMOS technology with a higher fT (frequency transition) will be suitable to enhance the performance of this circuit. V.
[2]
[3]
[4]
[5]
CONCLUSION
A new filter topology has been proposed and studied; this novel structure presents a high performance compared to the classical one particularly in the noise factor and dynamic range. The design of the proposed filter has been discussed, and the first measured results have been presented, these measurements confirm the interest of this design. This original circuit could substitute some SAW filters in wireless broadband applications.
[6]
[7]
[8]
3909
P. J. Chang, A. Rofougaran, and A. A. Abidi “A CMOS channelselect filter for a direct-conversion wireless receiver” IEEE J. SolidState Circuits, vol. 32, no. 5, pp. 722-729, May 1997. A. Yoshizawa and Y. P. Tsividis “Anti-blocker design techniques for MOSFET-C filters for direct conversion receivers” IEEE J. SolidState Circuits, vol. 37, no. 3, pp. 357-364, March 2002. C. Toumazou, D. G. Haigh, S. J. Harrold, S. J. Steptoe, J. I. Sewell, and R. Bayruns, “400 MHz switching rate GaAs switched capacitor filter,” IEE Electronics Letters, vol.26, pp. 460-461, 1990. J.C. Nallatamby, M. Bridier, M. Prigent, and J. Obregon, “Switched capacitors and sampled circuit by harmonic balance and related techniques,” IEE Electronics Letters, vol. 27, pp. 2364-2367, 1991. U. Kleine, W. Brockherde, A. Fettweis, B. J. Hosticka, J. Pandel and G. Zimmer, “An integrated six-path wave-SC filter”, IEEE J. of Solid State Circuits, vol. SC-20, no. 2, pp. 632-640, April 1985. H. Wupper, “A modified N-path filter suited for practical realization,” IEEE Trans. on Circuits and Systems, vol. 21, pp. 449-456, May 1974. B. Lai and R. C. Walker, “A monolithic 622 Mb/s clock extraction data retiming circuit,” in ISSCC Dig. Tech. Papers, Feb. 1993, pp. 144–144. A. El Oualkadi, J.M. Paillot, H. Guegnaud and R. Allam, “CMOS RF switched-capacitor bandpass filter tuned by ring VCO”, International Journal of Electronics and Communications, AEÜ, Elsevier, vol.59, issue no.6, pp.352-358, 15 September 2005.
