cmos analog current-mode multiplier based on the ... - IEEE Xplore
CMOS Analog Current-Mode Multiplier Based on the Advanced Compact MOSFET Model Pereira, F. A., Oliveira, M. C. G. de, Cunha A. I. A. Departamento de Engenharia Elétrica – Escola Politécnica Universidade Federal da Bahia - UFBA Salvador – BA, Brazil [email protected], [email protected] Abstract—This work presents a four-quadrant current-mode CMOS multiplier structure based on the Advanced Compact MOSFET (ACM) Model. On the contrary of most traditional approaches for implementing CMOS multipliers, the proposed configuration is valid in the whole inversion regime of the MOS transistor, providing wide input range and improved linearity. The main theoretical principle of our multiplier lies on the quadratic relationship between the forward saturation component of drain current and source transconductance, according to ACM model. A current signal is converted into source transconductance through a device operating in the linear region and this transconductance is mirrored to another device operating in saturation. The proposed architecture is compared with other current mode circuits regarding some performance features, such as linearity, harmonic distortion, dynamic input range and mismatch sensitivity.
I.
INTRODUCTION
Analog multipliers are basic building blocks in analog signal processing, communication systems and electronic instrumentation in general. Its wide application field, which includes mixers and analog implementation of neural networks, has instigated the conception and design of many structures in CMOS technology, taking advantage of the MOS transistor non-linearity [1] – [5]. Analog multipliers is often part of a mixed-mode CMOS integrated circuit designed to conciliate power consumption, chip area and performance specifications. The increasing demand for low-voltage/low-power integrated circuits has encouraged the conception of CMOS current-mode architectures. As in their voltage-mode counterparts, the operation principle of most available current-mode structures lies on the asymptotical behavior of drain current either deep in strong inversion [3] or in weak inversion [4] [5]. In both cases linearity becomes poorer as the amplitude of input signals increases, thus leading the MOS transistor to attain moderate inversion levels.
which describes the device operation in the whole inversion regime through single, simple and accurate expressions. Therefore, dynamic input range may be augmented without significantly degrading linearity. The proposed multiplier architecture is composed of current squarer networks associated in a well-known cancellation scheme [1]. The kernel of each current squarer is a source transconductance ( g ms = − ∂I D ∂VSB ) mirror, to be introduced in next section. II.
A.
Model Equations A theoretical analysis of the transconductance mirror current squarer may be entirely formulated in terms of the Advanced Compact MOSFET (ACM) model [6] [7], whose expressions are simple, require few parameters and are valid in the whole inversion regime. The ACM model expressions used in this work are shown in Table I, where if is the normalized forward saturation current (inversion level), ir is the normalized reverse saturation current which becomes negligible in saturation, φt is the thermal voltage, n is the slope factor almost bias independent, µ is the carrier mobility, C ′ox is the oxide capacitance per unit area, VGB is the gate-bulk voltage, VT0 is the threshold voltage in equilibrium, W is the channel width and L is the channel length. B. Source Transconductance Mirror In the basic structure shown in Fig.1, since transistors M1 and M2 have the same gate, source and bulk potentials, according to expressions in Table I, their inversion levels are equal. Therefore:
We present here a CMOS current-mode multiplier based on the Advanced Compact MOSFET (ACM) model [6] [7],
0-7803-8834-8/05/$20.00 ©2005 IEEE.
CURRENT MODE MULTIPLIER ARCHITECTURE
1020
g ms 2 IS2
=
g ms1 I S1
(1)
TABLE I. parameter/ characteristic
ACM MODEL EQUATIONS
symbol
expression
specific current source transconductance
IS
µC′ox
g ms
2 IS φt
source- bulk voltage for
iD2 ≅
IS (if − i r )
ID
drain current
Substituting (2) into (3), with VDS1 = Kφt and M2 in saturation (iD2 = IS2.if2), follows:
( 1 + i − 1) f
[
(
)]
[
(
)]
VP − ( + )φ t 1 + i f − 2 + ln 1 + i f − 1
VDB
VP − ( + )φ t 1 + i r − 2 + ln 1 + i r − 1
N(P)MOSFET voltage for N(P)MOSFET pinch-off voltage
VP =
VP
saturation drainsource voltage for
VGB − VT 0 n
(
+ (−)φT 3 + 1 + if
VDSSAT
i 2D1 i D1 4K 2 I + K S1
A i D2 = 2K
2
(I BIAS + iin )2 IS 2
+
A (I BIAS + iin ) K
1 + (1 + δ )i B − 1 K = 1 + (1 + δ )i B − 1 + i B + ln 1 + i − 1 B
)
Regardless the inversion level, if transistor M2 operates in saturation and transistor M1 operates in the linear region, with constant VDS1 < 2φt, the transconductance mirror performs current squaring. The following approximation is valid in the linear region: i D1 VDS1
VDD
MR1 MR2
VSS
VSS iDR1
(2)
iDR2
iD1
1:1 M3
iin VGG
VSS
+ VDS1
-
VS 1
M1
(6)
where iB = IBIAS/ISR1. (1 + δ)IBIAS
VGG
(5)
where A = IS2/IS1 is the mirroring ratio of the pair M1-M2. Since the current through M2 is mirrored by the pairs M3-M4 and M5-M6, the current through M1 is not modified by the connection between the sources of M1 and M2. A proper injection of signal and DC current through the pair MR1-MR2 allows the adjustment of parameter K by the relationship:
N(P) MOSFET
g ms1 ≅ g md1 ≅
(4)
C. Circuit implementation Fig.2 exhibits a possible circuit implementation of the structure in Fig.1. Parameter δ is adjusted in order to keep the value of VDS1 very small. The output current iD2 of the squarer is given by
W φ2t n L 2
VSB
drain- bulk
IS2 IS1
iin
M2
(2 + δ)IBIAS
VS 1
iD2 iD2
iD2
VSS M1
iD2
M4
M2
1:A
iD2
M6
M7 M5
1:1:1 VSS
iD1
Figure 2. Current squarer based on the transconductance mirror
The relationships for assuring that transistors MR2, M2, M4, M6 and M7 operate in saturation are given in Table II, according to ACM model. They are derived from the conditions: VDS > VDSSAT for NMOSFET and VDS < VDSSAT for PMOSFET, with VDSSAT given in Table I.
Figure 1. Source transconductance mirror
From (1) and the expression of gms in Table I: 2
φ φ i f 2 = t g ms1 + t g ms1 IS1 2IS1
(3)
1021
TABLE II. RELATIONSHIPS FOR ASSURING OPERATION IN THE SATURATION REGIME OF TRANSISTORS IN THE CURRENT SQUARER OF FIG.2 MOSFET
Condition for Saturation VDD − VSS φT
MR2 +
[ 1+ i
r1
−
VGG − VSS − VT 0
(
nφ T
)] [ 1 + i
− 2 + ln 1 + i r1 − 1 >
[
]
+3
B
)]
(
VDD − VT 0 VGG − VSS − VT 0 VSS > + + 5 − ln 1 + i f 1 − 1 + φT nφT φT
M2
I I + n 1 + i f 1 S2 − 2 + ln 1 + i f 1 S2 − 1 I S3 IS3
VDD − VSS − VT 0 I > 3 + 1 + i f 1 S2 φT I S4
M4
M6
The simulated performance of the proposed multiplier is compared with those of two current mode circuits based on weak [4] [5] and strong [3] inversion approaches. In the simulated weak inversion and strong inversion multipliers, all transistors operate with inversion levels equal to 0.5 and 250, respectively. We name IBIAS the DC component of the drain current through the input transistors in each configuration and we have adopted IBIAS = 10 µA. The cancellation scheme of Fig.3 has been applied to all three structures, with wx = wy = 0.5. The features here focused are input range, linearity and sensitivity on device mismatch.
Simulation of the DC transfer characteristics gives the linearity errors illustrated in Fig. 4. A wide relative input range has been considered for each input. As input signal amplitudes approach IBIAS, the inversion levels of the input transistors increase and the linearity of the weak inversion architecture becomes worse. Inversely, the linearity of the strong inversion architecture degrades as the input signal amplitudes approach –IBIAS, driving the input transistors from strong towards moderate inversion.
I I + n 1 + i f 1 S2 − 2 + ln 1 + i f 1 S2 − 1 I S6 I S6 VGG − VSS − VT 0 I > 3 + 1 + i f 1 S 2 nφT IS 6
[
)]
(
+ 1 + i f 1 − 2 + ln 1 + i f 1 − 1
VD9 − VSS I > 3 + 1 + i f 1 S 2 I S7 φT
M7
5
D. Cancellation configuration The complete multiplier structure is accomplished using the continuous-time cancellation scheme presented in [3] and illustrated in Fig.3. Assuming the four current squarer cells C1, C2 , C3 and C4 perfectly matched, each one behaving according to (5) with iin replaced by wxix + wyiy, 0, wxix and wyiy respectively, the output current iout is given by:
Linearity error (%)
2 A wxwy i OUT = ixi y K 2I S2
iY = IBIAS
(7)
C2
iOUT
wxix
C4 wyiy
Figure 3. Cancellation scheme for implementing four quadrant multiplier
III.
4
0.2
0.4
0.6
0.8
1
CIRCUIT PERFORMANCE
iY = -IBIAS
2 0
WI [4] [5] (b)
proposed
-2
SI [3]
-4 -6 -1
The complete multiplier circuit has been simulated through SMASH 4.3 [8], using parameters of CMOS AMS 0.8µm technology, which have been extracted for ACM model in [9]. We have adopted IBIAS = 2IS1 = 10 µA, A = 0.01, δ = 0.05, VGG = 1.0 V and wx = wy = 0.5. W1/L1 = 100, W2/L2 = 1, WR1/LR1 = WR2/LR2 = 40. The aspect ratio of the other transistors in Fig.2 are equal to 10.
WI [4] [5]
-10
normalized input current iX/IBIAS
Linearity error (%)
C3
C1
(a)
6
1:1
wxix + wyiy
SI [3]
-5
-15 0
The weight parameters wx and wy should be properly dimensioned in order to provide maximum excursion, inside the interval (0, 2IBIAS), for the input signal at C1.
proposed
0
-0.8
-0.6
-0.4
-0.2
normalized input current iX/IBIAS
0
Figure 4. Simulated linearity error in proposed structure (solid), strong inversion structure [3] (dashed) and weak inversion structure [4] [5] (dotted), for: (a) iY= IBIAS, (b) iY = -IBIAS.
Since the proposed multiplier operation is valid in the entire inversion regime, its linearity is chiefly restrained by the approximation in (2), which holds only if the transistor M1 of each squarer cell (Fig.2) operates in the beginning of the nonsaturation region. Provided that the constant drainsource voltage of M1 in the squarer cell remains sufficiently
1022
small, the amplitudes of its input current do not significantly affect the linear behavior of the multiplier. Therefore, the proposed architecture exhibits the smallest linearity error along the widest input rage.
Total Harmonic Distortion (%)
The results of total harmonic distortion (THD) simulation, performed for all three structures, are illustrated in Fig.5 and corroborate the previous argumentation. ix is a 100 Hz sinusoidal waveform with amplitude varying from zero to IBIAS and iy has the constant value IBIAS. For iy = - IBIAS, the THD augments in the strong inversion structure and diminishes in the weak inversion one, but remains the lowest in the proposed multiplier. 8
iY = IBIAS 6
The sensitivity of the proposed multiplier is comparable to that of the weak inversion structure and smaller than that of the circuit based on the strong inversion approach. IV.
ACKNOWLEDGMENT
4
Authors would like to acknowledge CNPq, CAPES and FAPESB for the financial support.
2
REFERENCES 0 0
0.2
0.4
0.6
0.8
[1]
1
normalized input current iX/IBIAS Figure 5. Simulated total harmonic distortion in proposed structure (circles), weak inversion structure [4] [5] (asterisks) and strong inversion structure [3] (squares).
[2]
Sensitivity on device mismatch can be verified through Monte Carlo analysis as illustrated in Fig.6 for the proposed structure, where the results are presented in the form of DC characteristics. MOS transistors from different cells have been given random geometric deviations.
[3]
[4]
[5]
0.8
0.6 iout/IBIAS 0.4
CONCLUSION
A new current-mode multiplier structure based on the ACM model has been proposed. Its theoretical principle lies on the mirroring of source transconductance and on the almost perfectly linear dependence of this parameter upon drain current in the very beginning of triode region. Therefore, provided that the input transistor is biased with very low drain-source voltage drop, the proposed architecture allows operation with wide input range with high linearity. Indeed, the input signals may swing up to the bias current value, without endangering linearity. Moreover, the proposed architecture presents acceptably low sensitivity on device mismatch.
iY = IBIAS
[6]
0.2 0 [7]
-0.2 -0.4
[8]
-0.6 -0.8 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0
[9]
ix/IBIAS Figure 6. Simulated Monte Carlo analysis of the proposed multiplier
1023
G. Han G. and E. Sánchez-Sinencio, “CMOS transconductance multipliers: a tutorial”, in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing., vol. 45, December 1998, pp. 1550 – 1563. B. M. Wilamowski, “VLSI analog multiplier/divider circuit”, in IEEE Proceedings of International Symposium on Industrial Electronics, vol. 2 , July 1998, pp 493 – 496. D.M.W. Leenaerts,. G.H.M. Joordens, J.A. Hegt, “A 3.3 V 625 kHz switched-current multiplier”, in IEEE Journal of Solid-State Circuits, vol. 31, September 1996, pp 1340 – 1343. E. Seevinck and R.J. Wiegerink, “ Generalized Translinear Circuit Principle”, in IEEE Journal of Solid-State Circuits, vol. 26, August 1991, pp 1098 - 1102. T. Serrano-Gotarredona, B. Linares-Barranco and A. G. Andreou, “A general translinear principle for subthreshold MOS transistors”, in IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 46, May 1999, pp 607 – 616. C. Galup-Montoro, M. C. Schneider and A. I. A. Cunha, “A currentbased MOSFET model for integrated circuit design,” Chapter 2 of Low-Voltage/Low-Power Integrated Circuits and Systems, pp. 7-55, edited by E. Sánchez-Sinencio and A. Andreou, IEEE Press, 1999, ISBN 0-7803-3446-9.. A.I.A. Cunha, M.C.Schneider and C. Galup-Montoro, “An MOS Transistor Model for Analog Circuit Design,” in IEEE J. Solid-State Circuits, vol.33, October 1998, pp.1510-1519. SMASH Circuit Simulator, Dolphin Integration, Meylan, France. Homepage: http://www.dolphin.fr. R.M. Coitinho, L.H. Spiller, M.C. Schneider and C. Galup-Montoro, “A simplified methodology for the extraction of the ACM MOST model parameters,” in 14th Symposium on Integrated Circuits and Systems Design (SBCCI 2001), Pirenópolis, GO, pp.136-141, September 2001.
I.
INTRODUCTION
Analog multipliers are basic building blocks in analog signal processing, communication systems and electronic instrumentation in general. Its wide application field, which includes mixers and analog implementation of neural networks, has instigated the conception and design of many structures in CMOS technology, taking advantage of the MOS transistor non-linearity [1] – [5]. Analog multipliers is often part of a mixed-mode CMOS integrated circuit designed to conciliate power consumption, chip area and performance specifications. The increasing demand for low-voltage/low-power integrated circuits has encouraged the conception of CMOS current-mode architectures. As in their voltage-mode counterparts, the operation principle of most available current-mode structures lies on the asymptotical behavior of drain current either deep in strong inversion [3] or in weak inversion [4] [5]. In both cases linearity becomes poorer as the amplitude of input signals increases, thus leading the MOS transistor to attain moderate inversion levels.
which describes the device operation in the whole inversion regime through single, simple and accurate expressions. Therefore, dynamic input range may be augmented without significantly degrading linearity. The proposed multiplier architecture is composed of current squarer networks associated in a well-known cancellation scheme [1]. The kernel of each current squarer is a source transconductance ( g ms = − ∂I D ∂VSB ) mirror, to be introduced in next section. II.
A.
Model Equations A theoretical analysis of the transconductance mirror current squarer may be entirely formulated in terms of the Advanced Compact MOSFET (ACM) model [6] [7], whose expressions are simple, require few parameters and are valid in the whole inversion regime. The ACM model expressions used in this work are shown in Table I, where if is the normalized forward saturation current (inversion level), ir is the normalized reverse saturation current which becomes negligible in saturation, φt is the thermal voltage, n is the slope factor almost bias independent, µ is the carrier mobility, C ′ox is the oxide capacitance per unit area, VGB is the gate-bulk voltage, VT0 is the threshold voltage in equilibrium, W is the channel width and L is the channel length. B. Source Transconductance Mirror In the basic structure shown in Fig.1, since transistors M1 and M2 have the same gate, source and bulk potentials, according to expressions in Table I, their inversion levels are equal. Therefore:
We present here a CMOS current-mode multiplier based on the Advanced Compact MOSFET (ACM) model [6] [7],
0-7803-8834-8/05/$20.00 ©2005 IEEE.
CURRENT MODE MULTIPLIER ARCHITECTURE
1020
g ms 2 IS2
=
g ms1 I S1
(1)
TABLE I. parameter/ characteristic
ACM MODEL EQUATIONS
symbol
expression
specific current source transconductance
IS
µC′ox
g ms
2 IS φt
source- bulk voltage for
iD2 ≅
IS (if − i r )
ID
drain current
Substituting (2) into (3), with VDS1 = Kφt and M2 in saturation (iD2 = IS2.if2), follows:
( 1 + i − 1) f
[
(
)]
[
(
)]
VP − ( + )φ t 1 + i f − 2 + ln 1 + i f − 1
VDB
VP − ( + )φ t 1 + i r − 2 + ln 1 + i r − 1
N(P)MOSFET voltage for N(P)MOSFET pinch-off voltage
VP =
VP
saturation drainsource voltage for
VGB − VT 0 n
(
+ (−)φT 3 + 1 + if
VDSSAT
i 2D1 i D1 4K 2 I + K S1
A i D2 = 2K
2
(I BIAS + iin )2 IS 2
+
A (I BIAS + iin ) K
1 + (1 + δ )i B − 1 K = 1 + (1 + δ )i B − 1 + i B + ln 1 + i − 1 B
)
Regardless the inversion level, if transistor M2 operates in saturation and transistor M1 operates in the linear region, with constant VDS1 < 2φt, the transconductance mirror performs current squaring. The following approximation is valid in the linear region: i D1 VDS1
VDD
MR1 MR2
VSS
VSS iDR1
(2)
iDR2
iD1
1:1 M3
iin VGG
VSS
+ VDS1
-
VS 1
M1
(6)
where iB = IBIAS/ISR1. (1 + δ)IBIAS
VGG
(5)
where A = IS2/IS1 is the mirroring ratio of the pair M1-M2. Since the current through M2 is mirrored by the pairs M3-M4 and M5-M6, the current through M1 is not modified by the connection between the sources of M1 and M2. A proper injection of signal and DC current through the pair MR1-MR2 allows the adjustment of parameter K by the relationship:
N(P) MOSFET
g ms1 ≅ g md1 ≅
(4)
C. Circuit implementation Fig.2 exhibits a possible circuit implementation of the structure in Fig.1. Parameter δ is adjusted in order to keep the value of VDS1 very small. The output current iD2 of the squarer is given by
W φ2t n L 2
VSB
drain- bulk
IS2 IS1
iin
M2
(2 + δ)IBIAS
VS 1
iD2 iD2
iD2
VSS M1
iD2
M4
M2
1:A
iD2
M6
M7 M5
1:1:1 VSS
iD1
Figure 2. Current squarer based on the transconductance mirror
The relationships for assuring that transistors MR2, M2, M4, M6 and M7 operate in saturation are given in Table II, according to ACM model. They are derived from the conditions: VDS > VDSSAT for NMOSFET and VDS < VDSSAT for PMOSFET, with VDSSAT given in Table I.
Figure 1. Source transconductance mirror
From (1) and the expression of gms in Table I: 2
φ φ i f 2 = t g ms1 + t g ms1 IS1 2IS1
(3)
1021
TABLE II. RELATIONSHIPS FOR ASSURING OPERATION IN THE SATURATION REGIME OF TRANSISTORS IN THE CURRENT SQUARER OF FIG.2 MOSFET
Condition for Saturation VDD − VSS φT
MR2 +
[ 1+ i
r1
−
VGG − VSS − VT 0
(
nφ T
)] [ 1 + i
− 2 + ln 1 + i r1 − 1 >
[
]
+3
B
)]
(
VDD − VT 0 VGG − VSS − VT 0 VSS > + + 5 − ln 1 + i f 1 − 1 + φT nφT φT
M2
I I + n 1 + i f 1 S2 − 2 + ln 1 + i f 1 S2 − 1 I S3 IS3
VDD − VSS − VT 0 I > 3 + 1 + i f 1 S2 φT I S4
M4
M6
The simulated performance of the proposed multiplier is compared with those of two current mode circuits based on weak [4] [5] and strong [3] inversion approaches. In the simulated weak inversion and strong inversion multipliers, all transistors operate with inversion levels equal to 0.5 and 250, respectively. We name IBIAS the DC component of the drain current through the input transistors in each configuration and we have adopted IBIAS = 10 µA. The cancellation scheme of Fig.3 has been applied to all three structures, with wx = wy = 0.5. The features here focused are input range, linearity and sensitivity on device mismatch.
Simulation of the DC transfer characteristics gives the linearity errors illustrated in Fig. 4. A wide relative input range has been considered for each input. As input signal amplitudes approach IBIAS, the inversion levels of the input transistors increase and the linearity of the weak inversion architecture becomes worse. Inversely, the linearity of the strong inversion architecture degrades as the input signal amplitudes approach –IBIAS, driving the input transistors from strong towards moderate inversion.
I I + n 1 + i f 1 S2 − 2 + ln 1 + i f 1 S2 − 1 I S6 I S6 VGG − VSS − VT 0 I > 3 + 1 + i f 1 S 2 nφT IS 6
[
)]
(
+ 1 + i f 1 − 2 + ln 1 + i f 1 − 1
VD9 − VSS I > 3 + 1 + i f 1 S 2 I S7 φT
M7
5
D. Cancellation configuration The complete multiplier structure is accomplished using the continuous-time cancellation scheme presented in [3] and illustrated in Fig.3. Assuming the four current squarer cells C1, C2 , C3 and C4 perfectly matched, each one behaving according to (5) with iin replaced by wxix + wyiy, 0, wxix and wyiy respectively, the output current iout is given by:
Linearity error (%)
2 A wxwy i OUT = ixi y K 2I S2
iY = IBIAS
(7)
C2
iOUT
wxix
C4 wyiy
Figure 3. Cancellation scheme for implementing four quadrant multiplier
III.
4
0.2
0.4
0.6
0.8
1
CIRCUIT PERFORMANCE
iY = -IBIAS
2 0
WI [4] [5] (b)
proposed
-2
SI [3]
-4 -6 -1
The complete multiplier circuit has been simulated through SMASH 4.3 [8], using parameters of CMOS AMS 0.8µm technology, which have been extracted for ACM model in [9]. We have adopted IBIAS = 2IS1 = 10 µA, A = 0.01, δ = 0.05, VGG = 1.0 V and wx = wy = 0.5. W1/L1 = 100, W2/L2 = 1, WR1/LR1 = WR2/LR2 = 40. The aspect ratio of the other transistors in Fig.2 are equal to 10.
WI [4] [5]
-10
normalized input current iX/IBIAS
Linearity error (%)
C3
C1
(a)
6
1:1
wxix + wyiy
SI [3]
-5
-15 0
The weight parameters wx and wy should be properly dimensioned in order to provide maximum excursion, inside the interval (0, 2IBIAS), for the input signal at C1.
proposed
0
-0.8
-0.6
-0.4
-0.2
normalized input current iX/IBIAS
0
Figure 4. Simulated linearity error in proposed structure (solid), strong inversion structure [3] (dashed) and weak inversion structure [4] [5] (dotted), for: (a) iY= IBIAS, (b) iY = -IBIAS.
Since the proposed multiplier operation is valid in the entire inversion regime, its linearity is chiefly restrained by the approximation in (2), which holds only if the transistor M1 of each squarer cell (Fig.2) operates in the beginning of the nonsaturation region. Provided that the constant drainsource voltage of M1 in the squarer cell remains sufficiently
1022
small, the amplitudes of its input current do not significantly affect the linear behavior of the multiplier. Therefore, the proposed architecture exhibits the smallest linearity error along the widest input rage.
Total Harmonic Distortion (%)
The results of total harmonic distortion (THD) simulation, performed for all three structures, are illustrated in Fig.5 and corroborate the previous argumentation. ix is a 100 Hz sinusoidal waveform with amplitude varying from zero to IBIAS and iy has the constant value IBIAS. For iy = - IBIAS, the THD augments in the strong inversion structure and diminishes in the weak inversion one, but remains the lowest in the proposed multiplier. 8
iY = IBIAS 6
The sensitivity of the proposed multiplier is comparable to that of the weak inversion structure and smaller than that of the circuit based on the strong inversion approach. IV.
ACKNOWLEDGMENT
4
Authors would like to acknowledge CNPq, CAPES and FAPESB for the financial support.
2
REFERENCES 0 0
0.2
0.4
0.6
0.8
[1]
1
normalized input current iX/IBIAS Figure 5. Simulated total harmonic distortion in proposed structure (circles), weak inversion structure [4] [5] (asterisks) and strong inversion structure [3] (squares).
[2]
Sensitivity on device mismatch can be verified through Monte Carlo analysis as illustrated in Fig.6 for the proposed structure, where the results are presented in the form of DC characteristics. MOS transistors from different cells have been given random geometric deviations.
[3]
[4]
[5]
0.8
0.6 iout/IBIAS 0.4
CONCLUSION
A new current-mode multiplier structure based on the ACM model has been proposed. Its theoretical principle lies on the mirroring of source transconductance and on the almost perfectly linear dependence of this parameter upon drain current in the very beginning of triode region. Therefore, provided that the input transistor is biased with very low drain-source voltage drop, the proposed architecture allows operation with wide input range with high linearity. Indeed, the input signals may swing up to the bias current value, without endangering linearity. Moreover, the proposed architecture presents acceptably low sensitivity on device mismatch.
iY = IBIAS
[6]
0.2 0 [7]
-0.2 -0.4
[8]
-0.6 -0.8 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0
[9]
ix/IBIAS Figure 6. Simulated Monte Carlo analysis of the proposed multiplier
1023
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