class-ab rail-to-rail cmos analog buffer - IEEE Xplore
Class-AB Rail-to-Rail CMOS Analog Buffer Juan M. Carrillo, J. Francisco Duque-Carrillo
Antonio Torralba, Ramón G. Carvajal
Dept. of Electronics and Elec. Eng. University of Extremadura, 06071 Badajoz, Spain {jmcarcal,duque}@unex.es
Dept. of Electronic Engineering University of Sevilla, 41092 Sevilla, Spain {torralba,carvajal}@gte.esi.us.es
I.
VDD
100.0 75.0
M3 A
V2 M2
IdM2 (µA)
Abstract— In this paper a low-power rail-to-rail CMOS analog buffer is presented. The circuit is based on an input stage made up of two complementary class AB differential pairs, while a simple additional circuit allows rail-to-rail operation at the output terminal. The proposed circuit combines low static power consumption and high drive capability, resulting very suitable for applications with large capacitive loads. The buffer has been designed in a 0.35-µm CMOS technology to operate with a ±1.5 V dual supply. Simulated results are provided in order to demonstrate the proper operation of the proposed circuit. A rail-to-rail signal swing is achieved and a THD lower than –44 dB is obtained for a 2.4-Vpp 100-kHz input sinewave signal, whereas the input capacitance is lower than 32 fF.
V1
M1
25.0
IB
IdM2
0.0
IB
−200.0
0.0
200.0
V1−V2 (mV)
VSS
(a)
(b)
Figure 1. (a) Class AB differential input cell and (b) its DC transfer characteristic for a differential input signal.
INTRODUCTION
VDD
Analog voltage buffers are important building blocks in mixed signal designs, where they are used for testing or signal monitoring and for driving large capacitive loads [19]. In the first case, the buffer is usually connected to internal nodes of the circuit under test. Therefore, any increase of the parasitic capacitance at this node could be critical and the performance could be degraded. For this reason, an important feature in an analog buffer is to present a low input capacitance. On the other hand, when the buffer is used to drive loads the input capacitance in not a significant problem. However, a high slew-rate along with a large output signal swing is desirable in order to drive the load over the entire voltage range in a fast way. The total supply voltage of present integrated circuits has been reduced, attending mainly to power consumption and reliability issues. This trend has forced most basic building blocks to be redesigned, in an attempt to operate under so stringent supply conditions. However, in an analog circuit a low supply voltage is not necessarily equivalent to a low power consumption, as the overall performance of analog blocks has to be guaranteed. In addition, noise levels remain unchanged in analog circuits while the available voltage range for the signal decreases. Therefore, rail-to-rail operation is essential in low-voltage designs, in order to maximize the signal-to-noise ratio. Different techniques have been previously proposed to implement a buffer meting the features pointed out above [1-9].
M3P A
M2P
M1P VDD Vin
IB
IB
Vout
VSS M1N
M2N B
M3N VSS
Figure 2. Low power buffer based on two complementary class AB differential input cells.
This paper introduces a circuit technique to obtain a rail-torail CMOS analog buffer with class AB behavior, which leads to a low power approach. Simulated results are provided to demonstrate the correct operation of the proposed solution. II.
PREVIOUS IMPLEMENTATION
A good approach based on using a complementary input stage with class AB behavior was introduced in [9]. Figure 1(a) illustrates a p-channel class AB differential pair, able to deliver a large amount of current when a large differential signal is applied to its input terminals [10]. The impedance
This work has been supported by the Spanish R&D Plan under Grants TIC-2002-00367 and TIC-2003-07307-C02-01.
0-7803-8834-8/05/$20.00 ©2005 IEEE.
50.0
1008
VDD M4NR
M2NR M4N
IB
MSN
IB
M1NR
M1N
M2N
M5N
M3NR IB,SN
M5NR
VSS
M3N Vin
VSS
Vout
VDD M3P VDD
M2P
M1P IB,SP
M1PR M3PR
MSP M4P
IB M5P
IB M2PR
M4PR
M5PR
VSS
Figure 3. Proposed rail-to-rail class AB buffer.
at node A in the differential pair is very low and its voltage is approximately constant even in the case of large input signals. Consequently, a differential voltage V1 – V2 leads to large current variations in M2 and, so, in M3, as shown in Figure 1(b). A class AB voltage buffer can be obtained by combining two complementary differential cells, as illustrated in Figure 2. In this case, the PMOS differential pair is able to deliver a large maximum current to the load when the input signal goes close to VDD, while the NMOS differential pair is used to sink a large current when a negative input signal is applied. Besides, the input capacitance of the circuit can be easily reduced if transistors M1P and M1N are scaled down with respect to M2P and M2N. Nevertheless, the circuit in Fig. 2 has two main limitations. On the one hand, the gate-source voltage of M3P and M3N may force the driver transistors M1P and M1N, respectively, to operate in the triode region, reducing the available operating voltage range. This drawback can be overcome by introducing voltage level shifters in order to drive M3P and M3N, as will be explained in detail later. On the other hand, the output voltage swing of this structure is limited when the output node goes close either the positive or the negative supply. In fact, when the input signal goes up the p-channel input pair delivers a certain current into the load. Nevertheless, the maximum voltage level that can be reached by the p-channel differential pair in the positive direction is one gate-source voltage and one saturation
voltage, VGS,p + VDSat,p, below VDD. Similarly, the constraint for the n-channel differential pair in the negative direction can be expressed as VGS,n + VDSat,n above VSS. For this reason, it would be advisable to drive the load through a n-channel pair in the positive direction and through a p-channel pair in the negative one, so that rail-to-rail operation could be achieved. III.
PROPOSED ANALOG BUFFER
Figure 3 illustrates the transistor-level implementation of the proposed rail-to-rail CMOS analog buffer [11]. The circuit is a single-gain-stage in which the input branch is made up of two complementary class AB differential pairs. One important difference respect to the circuit in Fig. 2 is that in this case the output node is not driven directly by the input drivers, but current mirrors M4P-M5P and M4NM5N, respectively, are used with this goal. As a consequence, the common gate of transistors M2P and M2N is now the non-inverting input terminal. In the midsupply region the PMOS as well as the NMOS input pair are active and their biasing currents are mirrored to the output branch of the circuit through current mirrors M4P-M5P and M4N-M5N, respectively. This configuration allows the NMOS input pair driving the output node in the voltage region close to VDD, whereas the PMOS pair controls the output in the voltage range close to VSS, in order to achieve rail-to-rail operation. Unfortunately, close to VDD the p-channel input pair is cut off and no current is mirrored
1009
maintaining the buffer turned on. Something similar happens when the input signal, Vin, is close to VSS and, therefore, rail-to-rail operation is reached at the input as well as at the output terminal of the circuit.
TABLE I TRANSISTOR ASPECT RATIOS (IN µm/ µm) FOR THE PROPOSED RAIL-TO-RAIL CLASS-AB BUFFER. M1P, M2P, M1PR
60/1
M1N, M2N, M1NR
20/1
M3P, M4N, M5N
30/1
M3N, M4P, M5P
10/1
M2PR-M5PR
10/1
M2NR-M5NR
30/1
MSP
1.8/1
MSN
0.6/1
It is worth to note that voltage level-shifters have been included in the input stage so as to drive transistors M3P and M3N, avoiding the operation of M1P and M1N, respectively, in the linear region and extending the signal range at the input branch up to both supplies.
1.50
50m
VOUT (V)
OFFSET (mV)
300. m /div
The dynamic operation of the proposed buffer is enhanced by the high drive capability of the class AB differential cells in the input branch of the circuit. In the case of a large input signal in the positive direction, transistor M2P cuts off whereas transistor M2N draws a large amount of current. This current is then mirrored to the output branch providing a copy of it to the load and allowing the output node to follow the input voltage. On the contrary, when a large input signal is applied in the negative direction, transistor M2N cuts off and M2P delivers a large current, which is drawn from the load when the output voltage follows the input signal.
10. m /div
-1.50
The input capacitance of the buffer can be reduced by scaling down the size of transistors M2P and M2N with respect to the geometry of M1P and M1N. Nevertheless, it must be pointed out that the reduction of the aspect ratio of these transistors would lead to a decrease of their effective drive capability.
-50m -1.50
VIN (V)
300. m/div
1.50
Figure 4. DC transfer characteristic of the analog buffer in Fig. 3 (solid line: output voltage, dashed line: offset voltage).
to the bottom part of the output branch, turning off the buffer. A similar situation arises close VSS, where the nchannel differential pair is not active. For this reason, transistors M1PR-M5PR and M1NR-M5NR have been included in the circuit in Fig. 2, maintaining active the output branch over the entire voltage range. Thus, the operation of the buffer can be detailed as follows. When the input signal, Vin, is in the midsupply region, the two input pairs, M1P-M2P and M1N-M2N, are active and M4P-M5P and M4N-M5N, respectively, mirror a current equal to IB to the output branch. Furthermore, a replica of the current IB is copied through transistors M1PR (M1NR) and M2PR-M3PR (M2NR-M3NR), providing the current required by the current source in the additional circuit at the bottom (top) of the output branch. As a consequence, transistors M4PR and M5PR (M4NR and M5NR) are turned off and do not contribute to the output current. When the input signal goes close to VDD, the PMOS input pair cuts off and the replica of the inverting input branch, i.e., M1PR-M3PR, does not send any current contribution to the current source in the additional circuit at the output. Thus, M4PR and M5PR turn on, drawing a current equal to IB from the output branch and, thus,
The bandwidth of the proposed buffer can be very large as there is only one high impedance node in the circuit. However, the single-gain-stage configuration adopted along with the high output impedance of the output node makes this configuration more suitable to be used for driving large capacitive loads, given that low resistive loads would reduce the total gain of the buffer and, consequently, its accuracy. IV.
SIMULATED RESULTS
The analog voltage buffer in Fig. 3 was implemented in a 0.35-µm CMOS technology, with nominal threshold voltages of 0.5 V and –0.6 V for NMOS and PMOS transistors, respectively. The circuit was designed to operate with a supply voltage of ±1.5 V, a biasing current of 10µA, and a capacitive load of 10 pF. The aspect ratios of the transistors in the circuit in Figure 3 are detailed in Table I. Figure 4 shows the DC transfer characteristic of the proposed analog buffer along with the offset voltage. As expected, rail-to-rail behavior is achieved. Figure 5 illustrates the large-signal transient response of the circuit in Fig. 3 to 2.4-Vpp 0.5-µs input pulses. Particularly, in Fig. 5(a) the input and output voltages are depicted. The circuit features a high slew-rate due to the class AB operation of the input stage. Figure 5(b) illustrates the currents flowing through the output transistors of the
1010
TABLE II SIMULATED PERFORMANCE OF THE ANALOG BUFFER IN FIGURE 3 (VDD = -VSS = 1.5 V, IB = 10 µA, CL = 10 PF).
(a)
Parameter
Value
Open-loop gain Unity-gain frequency
54 dB 6.1 MHz
Phase margin
86 º
Power dissipation
0.33 mW
Input capacitance THD (1.0 Vp-p @ 100 kHz)
31.5 fF –54.2 dB
(2.4 Vp-p @ 100 kHz)
–44.6 dB
SR+ / SR−
achieved by connecting two complementary differential pairs in parallel, while the output voltage can also be swept over the entire input voltage range, thanks to an additional circuit connected to the output branch. Simulated results have been provided in order to demonstrate that the proposed circuit can be used to test analog signals and to drive large capacitive loads.
(b) Figure 5. Large-signal transient response of the buffer in Fig. 3 with a 10-pF load to a 2.4-Vpp, 0.5-µs square input signal: (a) input and output voltages and (b) currents through the output transistors.
REFERENCES [1]
buffer. A large ratio between the maximum output current delivered by the buffer and the quiescent biasing current can be observed, demonstrating that the proposed solution leads to low power consumption. Finally, Table II provides a summary of the performance of the proposed buffer. All the parameters in the table were obtained for an input voltage equal to zero. The simulated open-loop gain and unity-gain frequency were approximately 54 dB and 6.1 MHz. The relatively low value of the gain is due to the single-gain-stage arrangement of the circuit. The value of the GBW can be increased at the expense of increasing the biasing current of the input differential pairs and, so, raising the power consumption of the circuit. A total harmonic distortion (THD) equal to –44.6 dB is obtained for a 2.4-Vpp 100-kHz input sinewave signal. The simulated input capacitance of the proposed buffer is lower than 32 fF when no scaling is performed in the input transistors. V.
56 / 44 V/µs
CONCLUSION
In this paper a rail-to-rail voltage buffer with reduced input capacitance has been proposed. Its class-AB operation provides a low-power consumption, resulting very suitable to drive large capacitive loads. Input rail-to-rail operation is
P. M. van Petegem and J. F. Duque-Carrillo, “Compact highfrequency output buffer for testing of analog CMOS VLSI circuits,” IEEE Journal of Solid-State Circuits, vol. 24, pp. 540–542, April 1989. [2] J. F. Duque-Carrillo and R. Perez-Aloe, “High-Bandwidth CMOS test buffer with very small input capacitance,” Electronics Letters, vol. 26, pp. 2084-2086, December 1990. [3] A. Nosratinia, M. Ahmadi, G. A. Jullien, “High-drive CMOS buffer for large capacitive loads,” Electronics Letters, vol. 27, pp. 10441046, June 1991. [4] P. Setty and W. Bliss, “A high-frequency BiCMOS buffer for testing analog ICs,” Proc. 35th IEEE MWSCAS, vol. I, pp. 768-769, 1992. [5] A. Nosratinia, M. Ahmadi, G. A. Jullien, M. Shridar, “High-swing, high-drive CMOS buffer,” IEE Proceedings – Circuits, Devices and Systems, vol. 142, pp. 109-112, April 1995. [6] G. Ciaulo, P. Malcovati, C. Bona, and F. Maloberti, “Novel circuit solutions for rail-to-rail CMOS buffer,” Proc. 1995 IEEE ISCAS, vol. III, pp. 1980-1983, 1995. [7] H. Elwan and M. Ismail, “CMOS low noise class AB buffer,” Electronics Letters, vol. 35, pp. 1834-1836, October 1999. [8] P. K. Chan, L. Siek, T. Lim, and M. K. Han, “Adaptive-biased buffer with low input capacitance,” Electronics Letters, vol. 36, pp. 775-776, April 2000. [9] A. Torralba, R. G. Carvajal, J. Galán, J. Ramírez-Angulo, “Compact low-power high slew rate CMOS buffer for large capacitive loads,” Electronics Letters, vol. 38, pp. 1348-1349, October 2002. [10] V. Peluso, P. Vancoreland, A. M. Marqués, M. S. J. Steyaert, and W. Sansen, “A 900-mV low-power ∆Σ A/D converter with 77-dB dynamic range,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 1887–1897, December 1998. [11] J. M. Carrillo, R. G. Carvajal, A. Torralba, and J. F. Duque-Carrillo, “Rail-to-rail low-power high-slew-rate CMOS analogue buffer,” Electronics Letters, vol. 40, pp. 843-844, July 2004.
1011
Antonio Torralba, Ramón G. Carvajal
Dept. of Electronics and Elec. Eng. University of Extremadura, 06071 Badajoz, Spain {jmcarcal,duque}@unex.es
Dept. of Electronic Engineering University of Sevilla, 41092 Sevilla, Spain {torralba,carvajal}@gte.esi.us.es
I.
VDD
100.0 75.0
M3 A
V2 M2
IdM2 (µA)
Abstract— In this paper a low-power rail-to-rail CMOS analog buffer is presented. The circuit is based on an input stage made up of two complementary class AB differential pairs, while a simple additional circuit allows rail-to-rail operation at the output terminal. The proposed circuit combines low static power consumption and high drive capability, resulting very suitable for applications with large capacitive loads. The buffer has been designed in a 0.35-µm CMOS technology to operate with a ±1.5 V dual supply. Simulated results are provided in order to demonstrate the proper operation of the proposed circuit. A rail-to-rail signal swing is achieved and a THD lower than –44 dB is obtained for a 2.4-Vpp 100-kHz input sinewave signal, whereas the input capacitance is lower than 32 fF.
V1
M1
25.0
IB
IdM2
0.0
IB
−200.0
0.0
200.0
V1−V2 (mV)
VSS
(a)
(b)
Figure 1. (a) Class AB differential input cell and (b) its DC transfer characteristic for a differential input signal.
INTRODUCTION
VDD
Analog voltage buffers are important building blocks in mixed signal designs, where they are used for testing or signal monitoring and for driving large capacitive loads [19]. In the first case, the buffer is usually connected to internal nodes of the circuit under test. Therefore, any increase of the parasitic capacitance at this node could be critical and the performance could be degraded. For this reason, an important feature in an analog buffer is to present a low input capacitance. On the other hand, when the buffer is used to drive loads the input capacitance in not a significant problem. However, a high slew-rate along with a large output signal swing is desirable in order to drive the load over the entire voltage range in a fast way. The total supply voltage of present integrated circuits has been reduced, attending mainly to power consumption and reliability issues. This trend has forced most basic building blocks to be redesigned, in an attempt to operate under so stringent supply conditions. However, in an analog circuit a low supply voltage is not necessarily equivalent to a low power consumption, as the overall performance of analog blocks has to be guaranteed. In addition, noise levels remain unchanged in analog circuits while the available voltage range for the signal decreases. Therefore, rail-to-rail operation is essential in low-voltage designs, in order to maximize the signal-to-noise ratio. Different techniques have been previously proposed to implement a buffer meting the features pointed out above [1-9].
M3P A
M2P
M1P VDD Vin
IB
IB
Vout
VSS M1N
M2N B
M3N VSS
Figure 2. Low power buffer based on two complementary class AB differential input cells.
This paper introduces a circuit technique to obtain a rail-torail CMOS analog buffer with class AB behavior, which leads to a low power approach. Simulated results are provided to demonstrate the correct operation of the proposed solution. II.
PREVIOUS IMPLEMENTATION
A good approach based on using a complementary input stage with class AB behavior was introduced in [9]. Figure 1(a) illustrates a p-channel class AB differential pair, able to deliver a large amount of current when a large differential signal is applied to its input terminals [10]. The impedance
This work has been supported by the Spanish R&D Plan under Grants TIC-2002-00367 and TIC-2003-07307-C02-01.
0-7803-8834-8/05/$20.00 ©2005 IEEE.
50.0
1008
VDD M4NR
M2NR M4N
IB
MSN
IB
M1NR
M1N
M2N
M5N
M3NR IB,SN
M5NR
VSS
M3N Vin
VSS
Vout
VDD M3P VDD
M2P
M1P IB,SP
M1PR M3PR
MSP M4P
IB M5P
IB M2PR
M4PR
M5PR
VSS
Figure 3. Proposed rail-to-rail class AB buffer.
at node A in the differential pair is very low and its voltage is approximately constant even in the case of large input signals. Consequently, a differential voltage V1 – V2 leads to large current variations in M2 and, so, in M3, as shown in Figure 1(b). A class AB voltage buffer can be obtained by combining two complementary differential cells, as illustrated in Figure 2. In this case, the PMOS differential pair is able to deliver a large maximum current to the load when the input signal goes close to VDD, while the NMOS differential pair is used to sink a large current when a negative input signal is applied. Besides, the input capacitance of the circuit can be easily reduced if transistors M1P and M1N are scaled down with respect to M2P and M2N. Nevertheless, the circuit in Fig. 2 has two main limitations. On the one hand, the gate-source voltage of M3P and M3N may force the driver transistors M1P and M1N, respectively, to operate in the triode region, reducing the available operating voltage range. This drawback can be overcome by introducing voltage level shifters in order to drive M3P and M3N, as will be explained in detail later. On the other hand, the output voltage swing of this structure is limited when the output node goes close either the positive or the negative supply. In fact, when the input signal goes up the p-channel input pair delivers a certain current into the load. Nevertheless, the maximum voltage level that can be reached by the p-channel differential pair in the positive direction is one gate-source voltage and one saturation
voltage, VGS,p + VDSat,p, below VDD. Similarly, the constraint for the n-channel differential pair in the negative direction can be expressed as VGS,n + VDSat,n above VSS. For this reason, it would be advisable to drive the load through a n-channel pair in the positive direction and through a p-channel pair in the negative one, so that rail-to-rail operation could be achieved. III.
PROPOSED ANALOG BUFFER
Figure 3 illustrates the transistor-level implementation of the proposed rail-to-rail CMOS analog buffer [11]. The circuit is a single-gain-stage in which the input branch is made up of two complementary class AB differential pairs. One important difference respect to the circuit in Fig. 2 is that in this case the output node is not driven directly by the input drivers, but current mirrors M4P-M5P and M4NM5N, respectively, are used with this goal. As a consequence, the common gate of transistors M2P and M2N is now the non-inverting input terminal. In the midsupply region the PMOS as well as the NMOS input pair are active and their biasing currents are mirrored to the output branch of the circuit through current mirrors M4P-M5P and M4N-M5N, respectively. This configuration allows the NMOS input pair driving the output node in the voltage region close to VDD, whereas the PMOS pair controls the output in the voltage range close to VSS, in order to achieve rail-to-rail operation. Unfortunately, close to VDD the p-channel input pair is cut off and no current is mirrored
1009
maintaining the buffer turned on. Something similar happens when the input signal, Vin, is close to VSS and, therefore, rail-to-rail operation is reached at the input as well as at the output terminal of the circuit.
TABLE I TRANSISTOR ASPECT RATIOS (IN µm/ µm) FOR THE PROPOSED RAIL-TO-RAIL CLASS-AB BUFFER. M1P, M2P, M1PR
60/1
M1N, M2N, M1NR
20/1
M3P, M4N, M5N
30/1
M3N, M4P, M5P
10/1
M2PR-M5PR
10/1
M2NR-M5NR
30/1
MSP
1.8/1
MSN
0.6/1
It is worth to note that voltage level-shifters have been included in the input stage so as to drive transistors M3P and M3N, avoiding the operation of M1P and M1N, respectively, in the linear region and extending the signal range at the input branch up to both supplies.
1.50
50m
VOUT (V)
OFFSET (mV)
300. m /div
The dynamic operation of the proposed buffer is enhanced by the high drive capability of the class AB differential cells in the input branch of the circuit. In the case of a large input signal in the positive direction, transistor M2P cuts off whereas transistor M2N draws a large amount of current. This current is then mirrored to the output branch providing a copy of it to the load and allowing the output node to follow the input voltage. On the contrary, when a large input signal is applied in the negative direction, transistor M2N cuts off and M2P delivers a large current, which is drawn from the load when the output voltage follows the input signal.
10. m /div
-1.50
The input capacitance of the buffer can be reduced by scaling down the size of transistors M2P and M2N with respect to the geometry of M1P and M1N. Nevertheless, it must be pointed out that the reduction of the aspect ratio of these transistors would lead to a decrease of their effective drive capability.
-50m -1.50
VIN (V)
300. m/div
1.50
Figure 4. DC transfer characteristic of the analog buffer in Fig. 3 (solid line: output voltage, dashed line: offset voltage).
to the bottom part of the output branch, turning off the buffer. A similar situation arises close VSS, where the nchannel differential pair is not active. For this reason, transistors M1PR-M5PR and M1NR-M5NR have been included in the circuit in Fig. 2, maintaining active the output branch over the entire voltage range. Thus, the operation of the buffer can be detailed as follows. When the input signal, Vin, is in the midsupply region, the two input pairs, M1P-M2P and M1N-M2N, are active and M4P-M5P and M4N-M5N, respectively, mirror a current equal to IB to the output branch. Furthermore, a replica of the current IB is copied through transistors M1PR (M1NR) and M2PR-M3PR (M2NR-M3NR), providing the current required by the current source in the additional circuit at the bottom (top) of the output branch. As a consequence, transistors M4PR and M5PR (M4NR and M5NR) are turned off and do not contribute to the output current. When the input signal goes close to VDD, the PMOS input pair cuts off and the replica of the inverting input branch, i.e., M1PR-M3PR, does not send any current contribution to the current source in the additional circuit at the output. Thus, M4PR and M5PR turn on, drawing a current equal to IB from the output branch and, thus,
The bandwidth of the proposed buffer can be very large as there is only one high impedance node in the circuit. However, the single-gain-stage configuration adopted along with the high output impedance of the output node makes this configuration more suitable to be used for driving large capacitive loads, given that low resistive loads would reduce the total gain of the buffer and, consequently, its accuracy. IV.
SIMULATED RESULTS
The analog voltage buffer in Fig. 3 was implemented in a 0.35-µm CMOS technology, with nominal threshold voltages of 0.5 V and –0.6 V for NMOS and PMOS transistors, respectively. The circuit was designed to operate with a supply voltage of ±1.5 V, a biasing current of 10µA, and a capacitive load of 10 pF. The aspect ratios of the transistors in the circuit in Figure 3 are detailed in Table I. Figure 4 shows the DC transfer characteristic of the proposed analog buffer along with the offset voltage. As expected, rail-to-rail behavior is achieved. Figure 5 illustrates the large-signal transient response of the circuit in Fig. 3 to 2.4-Vpp 0.5-µs input pulses. Particularly, in Fig. 5(a) the input and output voltages are depicted. The circuit features a high slew-rate due to the class AB operation of the input stage. Figure 5(b) illustrates the currents flowing through the output transistors of the
1010
TABLE II SIMULATED PERFORMANCE OF THE ANALOG BUFFER IN FIGURE 3 (VDD = -VSS = 1.5 V, IB = 10 µA, CL = 10 PF).
(a)
Parameter
Value
Open-loop gain Unity-gain frequency
54 dB 6.1 MHz
Phase margin
86 º
Power dissipation
0.33 mW
Input capacitance THD (1.0 Vp-p @ 100 kHz)
31.5 fF –54.2 dB
(2.4 Vp-p @ 100 kHz)
–44.6 dB
SR+ / SR−
achieved by connecting two complementary differential pairs in parallel, while the output voltage can also be swept over the entire input voltage range, thanks to an additional circuit connected to the output branch. Simulated results have been provided in order to demonstrate that the proposed circuit can be used to test analog signals and to drive large capacitive loads.
(b) Figure 5. Large-signal transient response of the buffer in Fig. 3 with a 10-pF load to a 2.4-Vpp, 0.5-µs square input signal: (a) input and output voltages and (b) currents through the output transistors.
REFERENCES [1]
buffer. A large ratio between the maximum output current delivered by the buffer and the quiescent biasing current can be observed, demonstrating that the proposed solution leads to low power consumption. Finally, Table II provides a summary of the performance of the proposed buffer. All the parameters in the table were obtained for an input voltage equal to zero. The simulated open-loop gain and unity-gain frequency were approximately 54 dB and 6.1 MHz. The relatively low value of the gain is due to the single-gain-stage arrangement of the circuit. The value of the GBW can be increased at the expense of increasing the biasing current of the input differential pairs and, so, raising the power consumption of the circuit. A total harmonic distortion (THD) equal to –44.6 dB is obtained for a 2.4-Vpp 100-kHz input sinewave signal. The simulated input capacitance of the proposed buffer is lower than 32 fF when no scaling is performed in the input transistors. V.
56 / 44 V/µs
CONCLUSION
In this paper a rail-to-rail voltage buffer with reduced input capacitance has been proposed. Its class-AB operation provides a low-power consumption, resulting very suitable to drive large capacitive loads. Input rail-to-rail operation is
P. M. van Petegem and J. F. Duque-Carrillo, “Compact highfrequency output buffer for testing of analog CMOS VLSI circuits,” IEEE Journal of Solid-State Circuits, vol. 24, pp. 540–542, April 1989. [2] J. F. Duque-Carrillo and R. Perez-Aloe, “High-Bandwidth CMOS test buffer with very small input capacitance,” Electronics Letters, vol. 26, pp. 2084-2086, December 1990. [3] A. Nosratinia, M. Ahmadi, G. A. Jullien, “High-drive CMOS buffer for large capacitive loads,” Electronics Letters, vol. 27, pp. 10441046, June 1991. [4] P. Setty and W. Bliss, “A high-frequency BiCMOS buffer for testing analog ICs,” Proc. 35th IEEE MWSCAS, vol. I, pp. 768-769, 1992. [5] A. Nosratinia, M. Ahmadi, G. A. Jullien, M. Shridar, “High-swing, high-drive CMOS buffer,” IEE Proceedings – Circuits, Devices and Systems, vol. 142, pp. 109-112, April 1995. [6] G. Ciaulo, P. Malcovati, C. Bona, and F. Maloberti, “Novel circuit solutions for rail-to-rail CMOS buffer,” Proc. 1995 IEEE ISCAS, vol. III, pp. 1980-1983, 1995. [7] H. Elwan and M. Ismail, “CMOS low noise class AB buffer,” Electronics Letters, vol. 35, pp. 1834-1836, October 1999. [8] P. K. Chan, L. Siek, T. Lim, and M. K. Han, “Adaptive-biased buffer with low input capacitance,” Electronics Letters, vol. 36, pp. 775-776, April 2000. [9] A. Torralba, R. G. Carvajal, J. Galán, J. Ramírez-Angulo, “Compact low-power high slew rate CMOS buffer for large capacitive loads,” Electronics Letters, vol. 38, pp. 1348-1349, October 2002. [10] V. Peluso, P. Vancoreland, A. M. Marqués, M. S. J. Steyaert, and W. Sansen, “A 900-mV low-power ∆Σ A/D converter with 77-dB dynamic range,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 1887–1897, December 1998. [11] J. M. Carrillo, R. G. Carvajal, A. Torralba, and J. F. Duque-Carrillo, “Rail-to-rail low-power high-slew-rate CMOS analogue buffer,” Electronics Letters, vol. 40, pp. 843-844, July 2004.
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