CMOS Current-controlled Oscillators - Semantic Scholar
CMOS Current-controlled Oscillators Junhong Zhao, Chunyan Wang Department of Electrical and Computer Engineering Concordia University Montreal, Canada Email: {zhao_jun, chunyan}@encs.concordia.ca
Abstract— The work presented in this paper is about the design of current-controlled oscillators (ICO). Two ICOs are proposed. Aiming at reducing the duration of the short-circuit currents caused by slowly-changing voltages in the circuits, signal conversion blocks are introduced to generate sharp pulses. In this way, the power efficiency of the circuits is improved, which leads to an extensive performance improvement of the circuits. Both ICOs can operate over a frequency range from 100 KHz to 900 MHz. The quality of the output waveforms before buffers is good and over the entire frequency range the rise/fall time is consistently short. The power dissipation of the ICOs is very low, the same as that of a 5-stage current-starving ring oscillator. Moreover, the scheme of the ICOs allows an easy adjustment of the duty cycle of the output pulse signals. A simple digital control structure of the duty cycle has also been proposed.
I.
INTRODUCTION
Current-controlled oscillator (ICO) is widely used in analog and digital circuits for signal generation and conversion. The frequency of the oscillation in an ICO can be controlled using different methods. Some use variable bias currents to make the delay and frequency in analog oscillators controlled [1]. In a current-starving ring oscillator, the supply current is adjusted to control the rise/fall time of each stage so that the frequency of oscillation depends on the current [2]. Using this method, in case of low frequency oscillation, the supply current is made weak, resulting a long rise/fall time of the output voltage. In the current-controlled oscillator proposed in [3], shown in Fig. 1, the frequency is controlled by the input current Iin , whereas the rise/fall time depends on the supply current in the latch and it is oscillation frequency independent. Thus, the quality of the output waveform is considerably improved. Aiming at a high performance of ICO circuits, the prime objective of this work is to develop an ICO scheme of very low power dissipation, high gain, wide range and simple structure. The ICO in [3] is able to provide almost all of them but its power dissipation may not be optimal. In this paper, a new scheme based on [3] is presented and two ICOs are proposed. Besides, a structure of ICO with easy duty cycle adjustment is also presented.
Fig. 1 ICO proposed in [3]. The oscillation is based on alternative SetReset of the latch placed in the center. The two PMOS transistors P1 and P2 are used to steer the input current Iin to the node Va to set the latch by means of N3, and then the node Vb to reset the latch by means of N4. The duration of set/reset process depends on Iin and the capacitances at these nodes.
II.
CIRCUIT DESIGN
A. Basic Idea In the circuit shown in Fig. 1, the change of the state of the latch is done by means of the pull-down NMOS transistor N3 or N4. The voltage for the pull-down operation, Va or Vb, is built up gradually by the charge accumulation with the input current Iin. The transistor N3 or N4 is turned on during most time of the built-up process until Vd is pulled down and Vc is set up. Thus, the short-circuit current from the latch for this pull-down operation contributes significantly to the power dissipation of the circuit. In the analysis above, it can be seen that the power dissipation in the circuit shown in Fig. 1 can be effectively decreased if the short-circuit current is reduced. To this end, the pull-down transistor N3 or N4 should be driven on by a maximum level of the gate voltage during a very short period of time. Therefore, a short-duration and large-swing pulse is needed to apply to these transistors. However, it should be mentioned that the rate of voltage variation dva/dt or dvb/dt at the gate of each pull-down transistor is related to the input
current and determines the oscillation frequency. In order to provide a high-driving short-duration pulse signal to each of the pull-down transistors while keeping the built-up process at Va and Vb untouched, a conversion block is needed, as shown in Fig. 2. The function of the block is to convert a slow-rise voltage signal into a sharp pulse without changing its cycle time. Also, it should be noted that the introduction of such blocks should not result in any degradation of other specifications. Based on the scheme shown in Fig. 2, two versions of ICO, namely ICO_NA and ICO_NB, are proposed in the following subsections. B. ICO_NA The circuit of ICO_NA is illustrated in Fig. 3a. The conversion block consists of two stages of inverter. It converts slowly-changing Va or Vb to a needed pulse signal Va'' or Vb'', as shown in Fig. 3b. It should be mentioned that, due to the added inverters, there are more current paths in the circuit shown in Fig. 3a, compared to that in Fig. 1. One may wonder if the power dissipation would be increased because of the currents in these added paths. In fact, the short-circuit currents in the added inverters during transition are much weaker than the current flowing through the pull-down transistors in the ICO of Fig. 1. A graphical explanation is presented in Fig. 4. The power dissipation can be reduced by replacing a strong longduration current by a few weaker short-duration ones. The introduction of the conversion block of two inverters helps to reduce the short-circuit currents in the ICO. The added conversion blocks improve the waveforms of the voltages Vc and Vd. If the quality of the waveforms are good, the buffers that are usually used for the outputs may not be needed, which reduces the global power dissipation. If they are still needed, the improvement of the waveforms will result in a better power efficiency of the buffers. In the circuit shown in Fig. 3a, the capacitance at the node Va or Vb is slightly changed due to the introduction of the inverters, but it will not result in a significant change of the sensitivity of frequency to current.
(a)
(b) Fig. 3 Oscillator ICO_NA (a) and the expected waveforms of the conversion block (b).
(a)
(b)
Fig. 4 Comparison between two short-circuit current i1 in ICO shown in Fig. 1 and i2 in ICO _NA of Fig. 3a. For the same slow-rising Va , i1 is much larger than i2 and lasts longer during transition, as the gate voltage of the PMOS shown in (a) is kept at 0V before the latch changes its state, whereas that in (b) is increasing, weakening i2 .
C. ICO_NB In the oscillator ICO_NA, the inverters are used for the pulse signal conversion to reduce the short-circuit currents of the latch. So the power dissipation of the circuit is reduced. This reduction is achieved at expense of introducing much smaller currents in the inverters of the conversion blocks. It would be desirable if these currents can be eliminated or reduced in order to have further improvement of power dissipation. To reduce the short-circuit currents added by the conversion blocks, we need to investigate about which kind of gate voltages is required to eliminate the short-circuit currents in the added inverters shown in Fig. 3a. The currents Fig. 2 Diagram of the ICO scheme for reducing short-circuit currents.
exist when the voltage Va is built up and a positive pulse signal is being formed to pull Vd down. Fig. 5 shows the desirable gate voltages for the elimination of the short-circuit currents. The conversion block of two cascaded inverters is unlikely to provide the voltage configuration shown in Fig. 5. However, in the period specified in Fig. 5, Vc and Vd are temporarily at the high level (VDD) and the low level (0V), respectively. Thus, Vd can be used to control P3 and Vc to N6. It should be noted that Vd is not a constant voltage but a pulse signal. Two inverters are inserted to add a delay so that the transistors P3 and N5 can not be turned on simultaneously. Similarly, the conversion block in the right side can also be made in a symmetrical way shown in Fig. 6. Using similar analysis as described above, we can find that, in the circuit shown in Fig. 6, the short-circuit currents during the period when Va and Va’’ are reset to 0V are also reduced. The global short-circuit currents of the circuit should be minimized even though more devices are used in the circuit as the duration of the currents is minimized. Furthermore, the voltages Vo and Vo’ of the circuit, as shown in Fig. 6, can be used as the outputs.
It is often the case that a pulse signal with long rise or fall time of an input voltage results in a long duration of shortcircuit currents in a digital gate. To reduce this time duration, the gate can be designed in a similar way as that described in ICO_NB. The signals applied to the MOS gates of the transistors of one current path need to be made nonoverlapping. It can be done at reasonably small expense of additional block forming the non-overlapping signals if the voltages applied to the block are fair-quality pulses. III.
DUTY CYCLE ADJUSTMENT
Unlike most of the oscillators, in the ICO shown in Fig. 1, 3 or 6, for a specified input current, the pulse width of Vd is proportional to C|Va, the capacitance at the node Va, and that of the rest of the cycle to C|Vb, that at the node Vb. The duty cycle T1/(T1+T2) can be easily adjusted by changing C|Va and/or C|Vb. Using this feature, we proposed a structure adjusting the duty cycle of the ICOs by means of a digital control, shown in Fig. 7. In this structure, the node capacitance and the duty cycle can be expressed as C |v a = C |vb =
n −1 i=0 m −1 i =0
Di 2i C0
(1)
Li 2 i C0
(2) n −1
T1 DutyCycle | vd = = T1 + T2
n −1 i =0
Fig. 5 Circuit of conversion block with the gate voltages desirable for the elimination of short-circuit currents during the Va built-up process. The short-circuit current can be completely removed if P3 has VDD at its gate and N6 has 0V, which can not be done by two cascaded inverters.
Fig. 6 Oscillator ICO_NB.
i =0
Di 2 i C 0
Di 2 i C 0 +
m −1 i =0
(3)
Li 2 i C0
where C0 is the unit capacitance, Di and Li are the binary data of the (i-1)th digit of the two digital control signals, respectively, shown in Fig. 7. In order to have an acceptable accuracy of the duty cycle control, the unit capacitance C0 should be significant larger than the parasitic capacitance at node Va or Vb. The unit capacitance C0 corresponds to the LSB of digital control signal.
Fig. 7 Duty cycle adjustment for the ICOs. The unit capacitance is C0 corresponding to the LSB of digital control signal.
IV.
SIMULATION RESULTS
It should be mentioned that the improvement of the quality of the ICO function is based on the improvement of power efficiency of the circuits by means of reducing the short-circuit currents. Fig. 10 shows the characteristics of power dissipation versus frequency of the three ICOs. By adding only a small number of devices, the power dissipation of the proposed ICOs is much lower than that of ICO in [3]. In particular, if the frequency is below 100MHz, the power dissipation is about 10 µW or below it, about 5 times lower than ICO in [3]. It is also confirmed that the power dissipation of ICO_NB is several times lower than that of ICO_NA in most part of the frequency range.
Power of ICOs versus frequency curves
100
The simulations using the models of a 0.18 µm technology have been conducted to verify the function of the proposed oscillators and to compare their performance with that of the ICO in [3]. The waveforms obtained in the simulation of ICO_NB are illustrated in Fig. 8. Similar waveforms have been observed in the simulation of the circuit ICO_NA. These ICOs can operate over a wide range of the input current, form sub-nA to µA and their oscillation frequency covers a range from 100KHz to 900MHz, as shown in Fig. 9. The waveforms of the output voltages of the proposed ICOs are of good quality and the rise/fall time of the outputs has little dependency on the frequency, as shown in Table. 1, which is not often the case in many other oscillators.
90 80
ICO in [3] ICO_NA ICO_NB
Power of ICOs (uW)
70 60 50 40 30 20 10 0 -1 10
0
1
10
10 Frequency (MHz)
2
3
10
10
Fig. 10 Power dissipation versus oscillation frequency characteristics of the three ICOs. The two proposed ICOs dissipate less power than ICO in [3] shown in Fig. 1 and the difference is, for example, about 20 times when f =10 MHz comparing ICO in [3] and ICO_NB. TABLE I.
RISE TIME AND FALL TIME OF ICO FAMILY*
ICO
Tr (S)
Tf (S)
ICO in [3]
179p < Tr < 250p
367p < Tf < 3.36µ
ICO_NA
140p < Tr < 171p
60p < Tf < 104n
ICO_NB
85p < Tr < 90p
44p < Tf < 64p
* f = 100K~900MHz.
V.
Fig. 8 Simulation waveforms of the proposed ICO_NB shown in Fig. 6 at Iin=630nA that results in the oscillation frequency of 400MHz. It shows the waveform of Va, Va’, Va’’,and Vd. Input current versus frequency curves
4
10
ICO in [3] ICO_NA ICO_NB
3
Frequency (MHz)
10
2
10
CONCLUSION
In this paper, two ICO circuits have been proposed. By means of simple conversion blocks, the short-circuit currents in these ICOs are reduced considerably, which improves the power efficiency and the quality of operation. Both of the proposed ICO circuits can operate over a wide frequency rang from 100KHz to 900MHz. The rise/fall time of the output signals is consistently short over the entire frequency range. The power dissipation of these circuits is among the lowest of CMOS oscillators, at the same level of a currentstarving 5-inversion-stage VCOs. Furthermore, if buffers are needed for the output signals, the good-quality waveforms of the ICOs help to reduce the power dissipation in the buffers. The duty cycle of the pulse signal generated by the ICOs can be easily adjusted. A digital control structure of the duty cycle has also been proposed. The circuits can be very easily implemented with a small number of transistors using a standard technology process.
1
10
REFERENCES [1]
0
10
[2] -1
10
-2
10
-1
10
0
10
1
2
10 10 Input current Iin (nA)
3
10
4
10
Fig. 9 Input current versus frequency of the three oscillators, ICO in [3] shown in Fig. 1, ICO_NA in Fig. 3a and ICO_NB in Fig. 6.
[3]
D. Mijuskovic, “Current-controlled oscillator with linear output frequency”, US. Patent, No.5,206,609, April 27, 1993. H. Ahn, D.J. Allstot, “A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications”, IEEE Journal of SolidState Circuits, pp.450-454, vol.35, March 2000. C. Wang, M.O. Ahmad, M.N.S. Swamy, “A CMOS currentcontrolled oscillator and its applications”, ISCAS ’03, pp.793-796, vol.1, May 2003.
Abstract— The work presented in this paper is about the design of current-controlled oscillators (ICO). Two ICOs are proposed. Aiming at reducing the duration of the short-circuit currents caused by slowly-changing voltages in the circuits, signal conversion blocks are introduced to generate sharp pulses. In this way, the power efficiency of the circuits is improved, which leads to an extensive performance improvement of the circuits. Both ICOs can operate over a frequency range from 100 KHz to 900 MHz. The quality of the output waveforms before buffers is good and over the entire frequency range the rise/fall time is consistently short. The power dissipation of the ICOs is very low, the same as that of a 5-stage current-starving ring oscillator. Moreover, the scheme of the ICOs allows an easy adjustment of the duty cycle of the output pulse signals. A simple digital control structure of the duty cycle has also been proposed.
I.
INTRODUCTION
Current-controlled oscillator (ICO) is widely used in analog and digital circuits for signal generation and conversion. The frequency of the oscillation in an ICO can be controlled using different methods. Some use variable bias currents to make the delay and frequency in analog oscillators controlled [1]. In a current-starving ring oscillator, the supply current is adjusted to control the rise/fall time of each stage so that the frequency of oscillation depends on the current [2]. Using this method, in case of low frequency oscillation, the supply current is made weak, resulting a long rise/fall time of the output voltage. In the current-controlled oscillator proposed in [3], shown in Fig. 1, the frequency is controlled by the input current Iin , whereas the rise/fall time depends on the supply current in the latch and it is oscillation frequency independent. Thus, the quality of the output waveform is considerably improved. Aiming at a high performance of ICO circuits, the prime objective of this work is to develop an ICO scheme of very low power dissipation, high gain, wide range and simple structure. The ICO in [3] is able to provide almost all of them but its power dissipation may not be optimal. In this paper, a new scheme based on [3] is presented and two ICOs are proposed. Besides, a structure of ICO with easy duty cycle adjustment is also presented.
Fig. 1 ICO proposed in [3]. The oscillation is based on alternative SetReset of the latch placed in the center. The two PMOS transistors P1 and P2 are used to steer the input current Iin to the node Va to set the latch by means of N3, and then the node Vb to reset the latch by means of N4. The duration of set/reset process depends on Iin and the capacitances at these nodes.
II.
CIRCUIT DESIGN
A. Basic Idea In the circuit shown in Fig. 1, the change of the state of the latch is done by means of the pull-down NMOS transistor N3 or N4. The voltage for the pull-down operation, Va or Vb, is built up gradually by the charge accumulation with the input current Iin. The transistor N3 or N4 is turned on during most time of the built-up process until Vd is pulled down and Vc is set up. Thus, the short-circuit current from the latch for this pull-down operation contributes significantly to the power dissipation of the circuit. In the analysis above, it can be seen that the power dissipation in the circuit shown in Fig. 1 can be effectively decreased if the short-circuit current is reduced. To this end, the pull-down transistor N3 or N4 should be driven on by a maximum level of the gate voltage during a very short period of time. Therefore, a short-duration and large-swing pulse is needed to apply to these transistors. However, it should be mentioned that the rate of voltage variation dva/dt or dvb/dt at the gate of each pull-down transistor is related to the input
current and determines the oscillation frequency. In order to provide a high-driving short-duration pulse signal to each of the pull-down transistors while keeping the built-up process at Va and Vb untouched, a conversion block is needed, as shown in Fig. 2. The function of the block is to convert a slow-rise voltage signal into a sharp pulse without changing its cycle time. Also, it should be noted that the introduction of such blocks should not result in any degradation of other specifications. Based on the scheme shown in Fig. 2, two versions of ICO, namely ICO_NA and ICO_NB, are proposed in the following subsections. B. ICO_NA The circuit of ICO_NA is illustrated in Fig. 3a. The conversion block consists of two stages of inverter. It converts slowly-changing Va or Vb to a needed pulse signal Va'' or Vb'', as shown in Fig. 3b. It should be mentioned that, due to the added inverters, there are more current paths in the circuit shown in Fig. 3a, compared to that in Fig. 1. One may wonder if the power dissipation would be increased because of the currents in these added paths. In fact, the short-circuit currents in the added inverters during transition are much weaker than the current flowing through the pull-down transistors in the ICO of Fig. 1. A graphical explanation is presented in Fig. 4. The power dissipation can be reduced by replacing a strong longduration current by a few weaker short-duration ones. The introduction of the conversion block of two inverters helps to reduce the short-circuit currents in the ICO. The added conversion blocks improve the waveforms of the voltages Vc and Vd. If the quality of the waveforms are good, the buffers that are usually used for the outputs may not be needed, which reduces the global power dissipation. If they are still needed, the improvement of the waveforms will result in a better power efficiency of the buffers. In the circuit shown in Fig. 3a, the capacitance at the node Va or Vb is slightly changed due to the introduction of the inverters, but it will not result in a significant change of the sensitivity of frequency to current.
(a)
(b) Fig. 3 Oscillator ICO_NA (a) and the expected waveforms of the conversion block (b).
(a)
(b)
Fig. 4 Comparison between two short-circuit current i1 in ICO shown in Fig. 1 and i2 in ICO _NA of Fig. 3a. For the same slow-rising Va , i1 is much larger than i2 and lasts longer during transition, as the gate voltage of the PMOS shown in (a) is kept at 0V before the latch changes its state, whereas that in (b) is increasing, weakening i2 .
C. ICO_NB In the oscillator ICO_NA, the inverters are used for the pulse signal conversion to reduce the short-circuit currents of the latch. So the power dissipation of the circuit is reduced. This reduction is achieved at expense of introducing much smaller currents in the inverters of the conversion blocks. It would be desirable if these currents can be eliminated or reduced in order to have further improvement of power dissipation. To reduce the short-circuit currents added by the conversion blocks, we need to investigate about which kind of gate voltages is required to eliminate the short-circuit currents in the added inverters shown in Fig. 3a. The currents Fig. 2 Diagram of the ICO scheme for reducing short-circuit currents.
exist when the voltage Va is built up and a positive pulse signal is being formed to pull Vd down. Fig. 5 shows the desirable gate voltages for the elimination of the short-circuit currents. The conversion block of two cascaded inverters is unlikely to provide the voltage configuration shown in Fig. 5. However, in the period specified in Fig. 5, Vc and Vd are temporarily at the high level (VDD) and the low level (0V), respectively. Thus, Vd can be used to control P3 and Vc to N6. It should be noted that Vd is not a constant voltage but a pulse signal. Two inverters are inserted to add a delay so that the transistors P3 and N5 can not be turned on simultaneously. Similarly, the conversion block in the right side can also be made in a symmetrical way shown in Fig. 6. Using similar analysis as described above, we can find that, in the circuit shown in Fig. 6, the short-circuit currents during the period when Va and Va’’ are reset to 0V are also reduced. The global short-circuit currents of the circuit should be minimized even though more devices are used in the circuit as the duration of the currents is minimized. Furthermore, the voltages Vo and Vo’ of the circuit, as shown in Fig. 6, can be used as the outputs.
It is often the case that a pulse signal with long rise or fall time of an input voltage results in a long duration of shortcircuit currents in a digital gate. To reduce this time duration, the gate can be designed in a similar way as that described in ICO_NB. The signals applied to the MOS gates of the transistors of one current path need to be made nonoverlapping. It can be done at reasonably small expense of additional block forming the non-overlapping signals if the voltages applied to the block are fair-quality pulses. III.
DUTY CYCLE ADJUSTMENT
Unlike most of the oscillators, in the ICO shown in Fig. 1, 3 or 6, for a specified input current, the pulse width of Vd is proportional to C|Va, the capacitance at the node Va, and that of the rest of the cycle to C|Vb, that at the node Vb. The duty cycle T1/(T1+T2) can be easily adjusted by changing C|Va and/or C|Vb. Using this feature, we proposed a structure adjusting the duty cycle of the ICOs by means of a digital control, shown in Fig. 7. In this structure, the node capacitance and the duty cycle can be expressed as C |v a = C |vb =
n −1 i=0 m −1 i =0
Di 2i C0
(1)
Li 2 i C0
(2) n −1
T1 DutyCycle | vd = = T1 + T2
n −1 i =0
Fig. 5 Circuit of conversion block with the gate voltages desirable for the elimination of short-circuit currents during the Va built-up process. The short-circuit current can be completely removed if P3 has VDD at its gate and N6 has 0V, which can not be done by two cascaded inverters.
Fig. 6 Oscillator ICO_NB.
i =0
Di 2 i C 0
Di 2 i C 0 +
m −1 i =0
(3)
Li 2 i C0
where C0 is the unit capacitance, Di and Li are the binary data of the (i-1)th digit of the two digital control signals, respectively, shown in Fig. 7. In order to have an acceptable accuracy of the duty cycle control, the unit capacitance C0 should be significant larger than the parasitic capacitance at node Va or Vb. The unit capacitance C0 corresponds to the LSB of digital control signal.
Fig. 7 Duty cycle adjustment for the ICOs. The unit capacitance is C0 corresponding to the LSB of digital control signal.
IV.
SIMULATION RESULTS
It should be mentioned that the improvement of the quality of the ICO function is based on the improvement of power efficiency of the circuits by means of reducing the short-circuit currents. Fig. 10 shows the characteristics of power dissipation versus frequency of the three ICOs. By adding only a small number of devices, the power dissipation of the proposed ICOs is much lower than that of ICO in [3]. In particular, if the frequency is below 100MHz, the power dissipation is about 10 µW or below it, about 5 times lower than ICO in [3]. It is also confirmed that the power dissipation of ICO_NB is several times lower than that of ICO_NA in most part of the frequency range.
Power of ICOs versus frequency curves
100
The simulations using the models of a 0.18 µm technology have been conducted to verify the function of the proposed oscillators and to compare their performance with that of the ICO in [3]. The waveforms obtained in the simulation of ICO_NB are illustrated in Fig. 8. Similar waveforms have been observed in the simulation of the circuit ICO_NA. These ICOs can operate over a wide range of the input current, form sub-nA to µA and their oscillation frequency covers a range from 100KHz to 900MHz, as shown in Fig. 9. The waveforms of the output voltages of the proposed ICOs are of good quality and the rise/fall time of the outputs has little dependency on the frequency, as shown in Table. 1, which is not often the case in many other oscillators.
90 80
ICO in [3] ICO_NA ICO_NB
Power of ICOs (uW)
70 60 50 40 30 20 10 0 -1 10
0
1
10
10 Frequency (MHz)
2
3
10
10
Fig. 10 Power dissipation versus oscillation frequency characteristics of the three ICOs. The two proposed ICOs dissipate less power than ICO in [3] shown in Fig. 1 and the difference is, for example, about 20 times when f =10 MHz comparing ICO in [3] and ICO_NB. TABLE I.
RISE TIME AND FALL TIME OF ICO FAMILY*
ICO
Tr (S)
Tf (S)
ICO in [3]
179p < Tr < 250p
367p < Tf < 3.36µ
ICO_NA
140p < Tr < 171p
60p < Tf < 104n
ICO_NB
85p < Tr < 90p
44p < Tf < 64p
* f = 100K~900MHz.
V.
Fig. 8 Simulation waveforms of the proposed ICO_NB shown in Fig. 6 at Iin=630nA that results in the oscillation frequency of 400MHz. It shows the waveform of Va, Va’, Va’’,and Vd. Input current versus frequency curves
4
10
ICO in [3] ICO_NA ICO_NB
3
Frequency (MHz)
10
2
10
CONCLUSION
In this paper, two ICO circuits have been proposed. By means of simple conversion blocks, the short-circuit currents in these ICOs are reduced considerably, which improves the power efficiency and the quality of operation. Both of the proposed ICO circuits can operate over a wide frequency rang from 100KHz to 900MHz. The rise/fall time of the output signals is consistently short over the entire frequency range. The power dissipation of these circuits is among the lowest of CMOS oscillators, at the same level of a currentstarving 5-inversion-stage VCOs. Furthermore, if buffers are needed for the output signals, the good-quality waveforms of the ICOs help to reduce the power dissipation in the buffers. The duty cycle of the pulse signal generated by the ICOs can be easily adjusted. A digital control structure of the duty cycle has also been proposed. The circuits can be very easily implemented with a small number of transistors using a standard technology process.
1
10
REFERENCES [1]
0
10
[2] -1
10
-2
10
-1
10
0
10
1
2
10 10 Input current Iin (nA)
3
10
4
10
Fig. 9 Input current versus frequency of the three oscillators, ICO in [3] shown in Fig. 1, ICO_NA in Fig. 3a and ICO_NB in Fig. 6.
[3]
D. Mijuskovic, “Current-controlled oscillator with linear output frequency”, US. Patent, No.5,206,609, April 27, 1993. H. Ahn, D.J. Allstot, “A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications”, IEEE Journal of SolidState Circuits, pp.450-454, vol.35, March 2000. C. Wang, M.O. Ahmad, M.N.S. Swamy, “A CMOS currentcontrolled oscillator and its applications”, ISCAS ’03, pp.793-796, vol.1, May 2003.
