Design of low-phase-noise CMOS ring oscillators - Semantic Scholar
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 49, NO. 5, MAY 2002
Design of Low-Phase-Noise CMOS Ring Oscillators Liang Dai, Member, IEEE, and Ramesh Harjani, Senior Member, IEEE
Abstract—This paper presents a framework for modeling the phase noise in complementary metal–oxide–semiconductor (CMOS) ring oscillators. The analysis considers both linear and nonlinear operations, and it includes both device noise and digital switching noise coupled through the power supply and substrate. In this paper, we show that fast rail-to-rail switching is required in order to achieve low phase noise. Further, flicker noise from the bias circuit can potentially dominate the phase noise at low offset factor for ring oscillators frequencies. We define the effective with large and nonlinear voltage swings and predict its increase for CMOS processes with smaller feature sizes. Our phase-noise analysis is validated via simulation and measurement results for ring oscillators fabricated in a number of CMOS processes. Index Terms—complementary metal–oxide–semiconductor (CMOS) ring oscillator, phase noise, timing jitter, voltage-controlled oscillator (VCO).
elements, the phase noise for ring oscillators have traditionally been much larger than that of resonator-based oscillators. In this paper, we analyze the phase noise due to both the device noise and power supply/substrate noise. We present a modified linear model in Section II which considers the nonlinear impact of voltage clipping. In Section III, we define an effec) for the ring oscillators and predict an intive factor ( with the advance in the operating speed of CMOS crease in processes. In Section IV, we describe the noise up-conversion mechanism due to the bias and frequency control circuits. Then we discuss the impact of the digital switching noise coupled through the shared power supply and substrate in Section V. Finally we provide some conclusions in Section VI. Additional mathematical derivations can be found in the Appendix at the end of this paper.
I. INTRODUCTION
II. MODIFIED LINEAR MODEL
P
HASE-LOCKED loops (PLLs) are used extensively in communications systems. In particular, they are used as frequency synthesizers and clock recovery circuits. Voltage-controlled oscillators (VCOs) are important building blocks in PLLs. The random fluctuations in the output phase of the oscillator, in terms of jitter or phase noise, is undesirable in most applications. The VCO is the major contributor to the PLL output phase noise outside the PLL loop bandwidth. Hence VCOs with low phase noise have to be designed to meet stringent communications standards. Unfortunately, real oscillators are nonlinear time-variant systems such that traditional linear time-invariant analysis becomes invalid for phase noise studies. The design of complementary metal–oxide–semiconductor (CMOS) VCOs with low phase noise is a challenging research topic and has been studied extensively in recent years [1]–[4]. Many traditional oscillators are based on LC resonators. Due to the difficulties in the implementation of on-chip inductors and the limited frequency tuning range, resonatorless VCOs have drawn significant attention for system-on-a-chip solutions [4]–[7]. Among many possible circuit topologies, ring oscillators are promising candidates due to their ease of implementation and wide frequency tuning range. They are compatible with digital CMOS technologies and occupy small chip area. However, because they do not have high- frequency, selective
Manuscript received March 8, 2001; revised May 17, 2002. This paper was recommended by Associate Editor A. Hajimiri. L. Dai was with the University of Minnesota, Minneapolis, MN 55455 USA. He is now with Prominent Communications, San Diego, CA 92121 USA (e-mail: [email protected]). R. Harjani is with the University of Minnesota, Minneapolis, MN 55455 USA and also with Bermai Inc., Minnetonka, MN 55305 USA (e-mail: [email protected]). Publisher Item Identifier 10.1109/TCSII.2002.801409.
In this section, we will derive the relation between the phase noise and the internal signal swing from a modified linear model for ring oscillators. This model applies to the differential pairs and the load devices in the delay cells of the ring oscillators. We show that, in order to achieve phase noise comparable with that of the LC oscillators, fast transitions are needed, i.e., devices have to operate in a hard switching mode and be switched ON and OFF completely. Some measurement results for our test chips are also presented at the end of this section. A. Theoretical Analysis Fig. 1 shows a simplified model for a three-stage ring oscillator. Each delay stage consists of a resistor, a capacitor, a negacell, and a voltage limiter. The system is linear as long tive as the internal voltages are not clipped by the limiters. When the peak-to-peak voltage swing tries to exceed the supply voltage of and ground, the circuit, the waveform becomes clipped by and this is modeled by the limiters in Fig. 1. For this condition the single-sideband (SSB) phase noise can be represented by (1) [2], where is the Boltzmann’s constant and is the absolute temperature. The excess noise factor accounts for the total noise from the passive resistor and the active device [8]. represents the peak-to-peak signal voltage, is the is the offset from the center frequency of oscillation, and center frequency (1) Under linear operation, the voltage waveform is sinusoidal . For simwhich can be written as plicity we have neglected its dc component and assumed that it is . This is a good approximation for most centered around optimally designed oscillators. Neglecting the dc term has no
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DAI AND HARJANI: DESIGN OF LOW-PHASE-NOISE CMOS RING OSCILLATORS.
Fig. 1.
Modified linear model for a three-stage ring VCO.
Fig. 2.
Sinusoidal waveform clipped by power supplies.
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Fig. 3. Waveform with soft clipping.
impact on our following analysis. It has been shown in [3] that the impulse sensitivity function (ISF or )1 can be approximated as shown in (2) while its rms value is given by (3), respectively
It can be shown that (1) has to be modified for as shown in (6). Please refer to Appendix for detailed mathematical derivations
(2)
(3) Comparing (2) and (3), it is easy to see that the SSB phase noise for a three-stage ring oscillator can be expressed in terms as in (4). Even though this expression is derived for of a ring oscillator with linear operation, its validity extends into nonlinear operation of a ring oscillator due to voltage clipping, since the ISF automatically considers the nonlinear effects [3] (4) Here, we have only considered thermal noise. Since the linear model does not predict noise aliasing, only noise close to will cause phase noise in the above linear model. Even though flicker noise exists in CMOS oscillators, its magnitude is usually much smaller than the thermal noise at the oscillation frequency . Hence it is reasonable to neglect flicker noise in the linear model. A more rigorous analysis has shown that flicker noise does result in phase noise due to nonlinear and time-variant effects [3]. Nevertheless, we will not discuss the impact of flicker noise here, since, as we will show in Section IV, the dominant flicker noise sources are in the bias and frequency control circuits instead of the devices in the delay cell and it should be analyzed by a separate model. In a real circuit, the waveform is bounded by the power supplies for large amplitudes. Let us assume that the sinusoidal waveform is symmetrically clipped as shown in Fig. 2. Its ISF can be approximated by (5)
for
(6)
in (6) to represent the idealized peak-to-peak We use voltage of the sine wave as if there was no clipping. Equations (1) and (6) indicate that the phase noise is proportional to for linear operation and is proportional to when clipped by the power supplies. The additional noise reduction results when the voltage is clipped. Hence from the fact that the period when the oscillator is susceptible to noise is reduced as the transitions take less time. In reality, the clipping is rarely as hard as shown in Fig. 2. We model this “soft clipping” shown in Fig. 3 by (7) (7) The ISF is now given by (8) and the phase noise is then given by (9). The mathematical derivations for (9) can be found in the Appendix (8)
for (9) for
.
for B. Simulation Results for
. (5)
1The 0(! t) is a function that defines the impact on the output phase by a unit current impulse at time equal to t.
In Fig. 4 we show the SSB phase noise at 600-kHz offset from a 900-MHz carrier frequency as a function of different signal swings predicted by both of our hard-clipping and soft-clipping k , and models. Here we assume that V, which are typical values for practical designs.
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Fig. 4.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 49, NO. 5, MAY 2002
SSB phase noise versus V .
Fig. 5. Bias and a delay cell for a ring oscillator with a source-coupled pair and symmetric loads.
Both results indicate that the phase noise consists of two re:a region without clipping and a gions with regard to region with clipping. This implies the additional reduction in phase noise when the idealized voltage swing tends to ). exceed the power supply ( The two models provide slightly different break-even points between the two regions. The break-even point for , the hard-clipping model is while the break-even point for the soft-clipping model is . The phase noise predicted by and only the two models are the same for small values of . Since both models differ by 1.76 dB for large values of provide similar predictions for the phase noise, we expect the exact shape of the nonlinear limiting not to significantly impact the phase noise performance. is directly related to the maximum slew rate by Since (10) when the transitions take place, as an alternative, (1), (6), . This is and (9) can also be expressed in terms of is not directly useful when the waveform is clipped and available. We will not rewrite the above equations here, since the derivation is mathematically straightforward (10) is equivalent to maximizing the switching Maximizing current. This suggests that improving the current switching efficiency can reduce the phase noise for given supply current. For a ring oscillator with fully differential delay cells, an ideal case would be that all the tail current is used for switching, i.e., a current switching efficiency of 100%. In practical delay cell topologies, the maximal current for charging and discharging the load capacitors sets a lower bond on the phase noise for given power consumption. A survey of published literature suggests that the phase noise of LC-tank oscillators is close to 120 dBc/Hz when the results are scaled to a 600-kHz offset from a 900-MHz center frequency [9]–[11]. They are located within the ellipse in Fig. 4. The phase noise curve for LC-tank oscillators is also plotted in k , and . Our calculathis figure for tion suggests that the phase noise for ring oscillators is likely to be much higher than that of LC-tank oscillators unless there
is rail-to-rail switching, and efficient switching is the only possible approach. C. Measurement Results As a first exercise we have designed two types of ring oscillators to validate our phase-noise model. Both of them have three delay stages. The bias circuit and the delay cell for one of them are shown in Fig. 5 (called Maneatis ring oscillator from now on in this paper). It contains a source coupled-differential pair and symmetric loads which provide good control over delay and high dynamic supply noise rejection [12]. The other oscillator is a coupled ring oscillator whose diagram is shown in Fig. 6. It contains two single-ended ring oscillators, namely a fast ring and a slow ring. Its frequency of oscillation can be tuned continuously between that of the fast ring and the slow ring. Both oscillators were fabricated in an HP 0.5- m CMOS technology through MOSIS. The chip microphotographs are shown in Fig. 7. As we are unable to measure the actual voltage swings without loading the oscillators, we use simulation reas a guide. We derive from in the sults for transient simulations for both oscillators. Our simulations sugmV for the Maneatis ring oscillator and gest that V for the coupled ring oscillator. The measured center frequency for the Maneatis oscillator is 1.38 GHz and the center frequency for the coupled ring oscillator is 960 MHz. For a fair comparison, the phase noise for both oscillators are scaled to a 600-kHz offset frequency from a 960-MHz carrier. Our measured SSB phase noise results for the two oscillators are 88 dBc/Hz and 114 dBc/Hz, respectively. Both measurement results are marked in Fig. 4 with circled plus signs. They match our theoretical predictions very well for fairly typical values for and . The difference of 26 dB/Hz in their SSB phase noise is primarily due to the difference in their values of . In Fig. 8, we plot the measured phase noise as a function of offset frequency. We note that the phase noise for the coupled ring oscillator is much lower than that for the Maneatis oscillator for all frequencies. It also rises faster at offset frequencies that are less than 300 kHz. We have run transient circuit simulations and extracted the ISFs and operating conditions for every device in the coupled ring oscillator. The result suggests that the
DAI AND HARJANI: DESIGN OF LOW-PHASE-NOISE CMOS RING OSCILLATORS.
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(a)
(b)
(c)
(d)
Fig. 6. Three-stage coupled ring oscillator.
(a) Fig. 7.
(b)
Chip microphotographs for (a) Maneatis ring oscillator (b) coupled ring oscillator.
tant factor that determines the oscillator phase noise due to the differential pairs and the loads in the delay cells. In essence, fast rail-to-rail switching is needed to minimize phase noise. III.
FACTOR FOR RING OSCILLATORS
In the last section, we developed a modified linear model for the additive noise sources in a ring oscillator. In this section, we define an effective factor based on our model and predict its potential improvement for future technologies. For a linear model, the phase noise for an -stage ring oscillator can be written in terms of the factor as [2] Fig. 8. SSB phase noise comparison between the Maneatis oscillator and the coupled ring oscillator.
primary flicker-noise contributors are the fast inverters. It could have been reduced further by a more symmetric waveform design [3]. The simulation and measurement results provided in this section have validated our modified linear phase-noise model. Our model suggests that the signal voltage swing is the most impor-
(11) By comparing (11) and (1) for three-stage ring oscillator is considered.
, we can see that for a if no voltage clipping
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In the last section, we noted that voltage clipping helps reduce phase noise. Alternatively, we can think of this as an increase of for a threethe effective . By comparing (11) and (9), stage ring oscillator with large swings is given by (12)
(12) in terms of the of the It is also interesting to express , where is CMOS process, which is given by characterthe total gate capacitance of the MOS device. The izes the maximum speed for the devices in a certain technology.2 It sets a lower bond for the transition time. Therefore, it is an . important factor determining When a digital inverter is used as a delay stage, the maximum slew rate is determined by the current flowing through the negative-channel MOS (NMOS) or positive-channel MOS (PMOS) device that charges or discharges the load capacitance. In order to minimize the flicker noise, the NMOS and the PMOS devices are sized to achieve identical rise and fall times [3]. Hence, , where and are the carrier mobilities if for the NMOS and PMOS devices, respectively, then the W/L ratio for the PMOS device has to be times larger than that for the NMOS device. Now that the waveform has the same rise and fall time, we can use the discharging process to calculate the transition time. Other than the gate capacitances of the next delay stage, the load usually contains some additional capacitance from an output buffer which amplifies the internal voltage and sends it to the output. The buffer helps prevent load pulling or the variation of frequency due to any change in the output load. Let us assume that the additional load capacitance due to , where and are the gate the buffer is capacitances of the NMOS and PMOS transistors in the next stage, respectively. The maximum slew rate is now given by
(13) Therefore, the
is now given by (14)
f
2The actually defines the frequency at which the current gain of the device is equal to one.
Fig. 9. Effective
Q factor as a function of the f
CALCULATED
Q
FOR
of the process.
TABLE I PROCESSES AVAILABLE FROM MOSIS
Next, we use (14) to calculate the as a function of for different supply voltages, assuming , i.e., the negligible capacitance due to the buffer. For our analysis, we V. This assumption should hold have assumed that reasonably well, since the device threshold voltage does not change substantially for different processes. The results are for a number plotted in Fig. 9. We have also calculated of different processes available via MOSIS, including TSMC 0.35 m, TSMC 0.25 m, TSMC 0.18 m, HP 0.5 m, HP 0.35 m, AMI 1.5 m, AMI 0.8 m, and AMI 0.5 m [13]. s for these processes were obtained by simulating a The transistor with the gate voltage set to be equal to the power are supply voltage. The maximum slew rates derived from the measured results for ring oscillators from MOSIS. Then (12) is used to calculate the effective . The results are summarized in Table I and also shown Fig. 9. It with larger can be seen that there is a trend for higher values for the various technologies. However, it should be noted ’s of future processes are not likely to that the realizable increase as rapidly due to the reduced supply voltages and the close to four is lag in PMOS devices. Fig. 9 projects that a possible at 900 MHz for future processes. If this is achieved, the phase noise for ring oscillators is likely to be comparable to that of LC-tank oscillators with on-chip spiral inductors. Furthermore, ring oscillators still retain their better integration properties and larger frequency tuning range.
DAI AND HARJANI: DESIGN OF LOW-PHASE-NOISE CMOS RING OSCILLATORS.
Fig. 10.
Bias structure for an
N -stage ring oscillator.
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following derivation, we assume that the current mirrors have a ratio of 1 : m as shown in Fig. 10. In general, the oscillation frequency is proportional to , where is the load capacitance for each delay cell. for a three-stage ring As an example, includes a voltage-dependent part, oscillator. Even though in its variation is usually much smaller than the variation in the presence of noise. We can, therefore, derive the relation in (15) using this assumption (15) of each When operated in the long channel regime, the , where is the delay cell is given by tail current. This is valid for all the reasonable gate overdrive voltages . Using (15), it can be shown that (16) is valid for small signal amplitudes
Fig. 11. bias.
Up-conversion mechanism for low-frequency noise in the tail and
(16) IV. NOISE UP-CONVERSION
In a fully differential ring oscillator, low-frequency noise close to dc from the bias and the tail devices is up-converted to the vicinity of the carrier frequency by frequency modulation. This is not modeled by our analysis in the previous section or any previously published work. In this section, we analyze this noise up-conversion mechanism and validate it via simulations and measurement results. A. Theoretical Analysis An -stage ring oscillator is generally biased as shown in of the Fig. 10. Noise in the tail current devices causes the delay cell to change, hence varying the instantaneous oscillation frequency. We derive mathematical expressions to show the impact of bias noise on the overall oscillator phase noise. We will first consider thermal noise, and then extend our analysis to include flicker noise. This up-conversion mechanism can be illustrated with the help of Fig. 11. First, the noise is band-limited by the poles , , , , . This low-pass filtered at the drains of of the delay cells, and results in noise then modulates the in the frequency variation. Finally, since in the frequency dotime domain, they satisfy main. This analysis suggests that the phase noise has a shape at low offset frequencies and drops off at a faster rate for higher offset frequencies. However, since the low-pass bandwidth is usually much larger than the oscillation frequency, the faster phase noise roll-off is rarely observed because other noise sources start to dominate. So it is of little interest. Additionally, we are usually more concerned with the up-conversion of the low-frequency noise. This is more of an issue when flicker noise is present and causes the phase noise to rise at a more rapid rate at low offset frequencies. separately from We treat the noise from the bias transistor , , , in Fig. 10, the noise contributed by transistors is correlated for all because the low-frequency noise from , , , is not. In the stages while the noise from
is , The thermal-noise density from is the for . The noise power is amplified where times by each tail device. We can also replace by with for the tail devices. Hence, the normalized variation in frequency is given by (17) (17) Finally, we can write the resulting phase noise as shown in (18)
(18) to is treated in a similar manner to The noise from except that the noise is uncorrelated for each the noise from tail device. When we consider the frequency variation due to a single delay cell, (16) has to be modified as shown in (19) where and are the and for the th delay cell (19) delay stages, the resulting phase Considering that there are noise expression is given by (20) (20) is 1/4 of , since the variThe SSB phase noise ation in phase generates correlated phase noise on both sides of the carrier. Therefore, the total noise contributed by the bias
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transistor (21)
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[(18)] and the
tail devices [(20)] is given by
(21) The up-conversion of flicker noise can be treated in a similar fashion. If the flicker noise is modeled as in (22) [15] (22) and are flicker noise parameters. Then (21) can where be modified for flicker noise as shown in (23) (23)
Fig. 12.
Bias and a delay cell for a three-stage ring oscillator.
0
, the up-conversion Since is usually much larger than is likely to be more severe than that from of the noise from could be the tail devices. In practice, the flicker noise from the major noise source at low offset frequencies. To take into account of short channel effects, the drain-to-source current can be modeled as shown in (24) [16]
TABLE II AND
0
(24) and are empirical numbers. They approach 0 for where long channel devices and take on larger values for short channel devices. We use this format for short channel devices, because it maintains the simplicity of our equations. Here represents the linear reduction in mobility due to short channel effects, and represents the reduction of the exponent from the quadratic and to the linear for extremely short devices. Values for can be obtained from simulations or by equating (24) with traditional short channel equations [14]. By following a similar derivation as above, it can be shown that (25) becomes smaller for short channel The factor devices. As a result, both (21) and (23) have to be multiplied by to account for short channel effects. B. Simulation Results We have simulated a three-stage ring oscillator as an example whose bias circuit and one of the delay cells are shown in Fig. 12. The frequency of the oscillator is controlled by the supplied through . We apply the analysis bias current methodology proposed in by injecting a current pulse into the nodes 1, 2, and 3 throughout a complete clock cycle and observe the phase shift after it settles into steady state again. ) which are modulated by the thermal The effective ISFs ( and flicker noise are calculated for each individual device. ’s are imAs mentioned in [3], the rms values for the ’s are portant for thermal noise and the mean values of the important for flicker noise. Table II lists the rms values for ’s and mean values for ’s for all the tran-
Fig. 13.
Simulation of frequency variation versus bias current variation.
sistors. It can be seen that the thermal noise contribution of all the devices are similar in magnitude, though the contribution is slightly larger than the others. However, for flicker of and dominate, suggesting that noise the contributions of the majority of the low-frequency phase noise is contributed by the bias devices. in the bias. In We have only included a single device reality, more devices are often used for the bias. For example, a voltage-to-current converter is usually needed between the loop filter and the VCO in a PLL. Any low-frequency noise generated is equivalent to an increase in the noise from and in could potentially dominate the low-frequency phase noise. We verify (16) in our noise up-conversion model by simulating the circuit in Fig. 12. We vary the bias current, and observe the variation in frequency in the steady state. We assume is proportional to and is the same for dc and . Fig. 13 provides the comany low-frequency variation in and . parison between and are drawn as In Fig. 13 both is given a functions of the bias current. In the simulations
DAI AND HARJANI: DESIGN OF LOW-PHASE-NOISE CMOS RING OSCILLATORS.
335
(a)
(b) Fig. 15. VCO block diagram (a) traditional view (b) rigorous view.
Fig. 14.
Phase noise with different bypass capacitors.
fixed value so that is swept linearly. Therefore, the curve of drops at a slope of 20 dB/decade. The two curves match extremely well for low bias currents. The error increases with larger bias current because of short channel effects and current mirror mismatch due to the channel length modulation. increases, the mismatch between the drain voltWhen and increases. This causes not to increase as ages of . As a result, the oscillation frequency becomes much as , and the curve of falls further less sensitive to in Fig. 13 for the increased below the curve of bias currents. Despite short channel effects and channel length modulation effects, our simulations confirm our model for noise up-conversion. Our conclusions are further strengthened by our measurement results discussed next. C. Measurement Results Again, we use measurement results for the Maneatis oscillator shown in Fig. 5. Fig. 14 provides the measurement results for the circuit tested under two conditions. In the first experiment, a 100- F bypass capacitor is connected between the bias is filtered point and ground so that most of the noise from out and does not cause phase noise. In the second experiment, a 11.7-nF capacitor is used instead.3 Due to the higher low-pass is corner frequency, some of the low-frequency noise from up-converted to phase noise by frequency modulation. With a large bypass capacitor, the phase noise curve retains the characteristic of the thermal noise. With a small bypass capacitor, the phase noise curve starts to rise faster at low offset freregion. This implies that the flicker quencies and enters the noise from the bias transistor can dominate at low frequencies which confirms our previous theoretical analysis. In a practical PLL design, the bias point is an internal node and no large off-chip capacitor is available to bypass the flicker and other transistors in the bias circuit. Furnoise from thermore, no additional low-frequency poles can be placed at the VCO frequency control port in a PLL due to stability concerns. Therefore, without this filtering possibility the flicker noise level can become so high that it is even dominant at frequencies beyond the loop bandwidth and cannot be suppressed by the PLL. This is particularly an important issue for low-band3We use such large capacitor values because the filter corner frequency is set by g =C where C is the bypass capacitor value.
Fig. 16. Three-stage differential ring oscillator.
width PLLs. Therefore, for integrated VCO designs, the current mirror bias structure should be avoided if possible. V. POWER SUPPLY/SUBSTRATE NOISE So far, we have analyzed the impact on phase noise caused by intrinsic device noise. When the oscillator is fabricated on the same silicon substrate and shares the same power supply with digital circuits, there is a significant amount of noise due to the digital switching activity coupled through the common power supply and the substrate. In this section, we will analyze the impact of the supply and substrate noise. A. Theoretical Analysis The output frequency of the VCO is traditionally considered only as a function of the control voltage, and the VCO is viewed as a block which does frequency modulation (FM). It has one input port and one output port. This is shown in Fig. 15(a). However, a more rigorous view of the VCO is shown in Fig. 15(b). , but also the power The VCO is not only controlled by supply and the substrate. In addition to frequency variations (FM), changes in the inputs also cause instantaneous phase shift at the output, resulting in phase modulation (PM) as well. Since a change in the output frequency causes the phase noise to accumulate, FM is usually the dominant factor, and PM can be neglected. In the following discussion, we will focus on the power supply noise. The impact of the substrate noise can be derived similarly. We will study the ISF for the power supply first. For an -stage differential ring oscillator operating at frequency , it can be shown that its ISF is a periodic function with a , i.e. frequency of (26) Let us consider the three-stage differential ring oscillator as shown in Fig. 16. Fig. 17 illustrates the waveforms for the internal nodes A, A′, B, B′, C, and C′. It is seen from Fig. 17 that the oscillator goes through six equivalent states in a clock cycle,
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Fig. 17. Waveforms showing the six equivalent states for a three-stage oscillator.
hence the ISF for has a frequency of . This can be generalized to an -stage differential ring oscillator whose ISF for has a frequency of . Based on the analysis in [4], only supply and substrate noise will make major whose frequency is close to dc and . It contribution to the VCO phase noise where can be shown that for supply noise close to dc, the SSB phase is the noise is given by (27) where is the noise amplitude, is the noise frequency dc term for and
Fig. 18.
Sideband PSD when sinusoidal ripple is added to the power supply.
As a result, the rms value for the period jitter is defined by (31). It is interesting to note that it is independent of the frequency of the supply and substrate noise (31)
B. Simulation Results (27) , the SSB phase noise is given For supply noise close to is by (28) where is the th Fourier coefficient for and the offset frequency from (28) From (27) and (28), it can be seen that, for supply noise either , the resulting phase noise is inversely proclose to dc or . However, the previous statement is not preportional to is a function of frequency. We shall provide cisely true when more details of this discrepancy later in this section. In most is at multiple high-frequency applications, the frequency gigahertz and above. However, the majority of the power supply noise is closer to dc than to any of the harmonic frequencies. As a result, the low-frequency supply noise has more of an impact on the ring-oscillator phase noise, and (27) can be used for most practical design considerations. There are also applications where the clock jitter is more of a concern. It is beneficial to discuss the impact of the supply and substrate noise in terms of jitter. In particular, we will use the which is the variation of the clock period. term period jitter where With low-frequency supply noise the instantaneous frequency of oscillation is given by (29) Hence
(30)
Due to the presence of decoupling capacitors on the circuit board and the bond wire inductance, it is hard to precisely control and measure the ripple that the circuit sees on the power supply. Therefore, we use simulations results to verify our power supply noise model on a three-stage Maneatis ring oscillator. We introduce a sinusoidal ripple with a peak voltage of 0.1 V added to the power supply for these simulations. Fig. 18 shows the sideband power spectral density (PSD) as a . In particular, the frequency function of the offset frequency , , and where of the ripple signal is at MHz and . It can be seen from the figure that, for frequencies close to , the PSD for the phase noise drops at a rate of dc and increases for higher frequencies. The lower 20 dB/dec as rate for frequencies less than 100 MHz is because the delay cell has a fully differential topology whose power supply rejection ratio (PSRR) improves at low frequencies. In other words, its becomes smaller at low frequencies. As a result, the curve stops increasing at low offset frequencies. for We have also simulated the oscillator with the ripple freclose to . As shown in Fig. 18, we do not see a quency slope as in the case of and . Instead, it only changes slightly over frequency. Additionally, we note that and its absolute value is lower than for both for low offset frequencies. In a practical CMOS PLL design, high frequency supply and substrate noise is usually more problematic due to reduced isolation at higher frequencies [17]. In [17], the noise power increases at a rate of 20 dB/decade over frequency until about 500 MHz. If we neglect the impact of supply and substrate noise on the other components in a PLL and use the results in [17] and Fig. 18, the supply and substrate noise causes spurs beyond the
DAI AND HARJANI: DESIGN OF LOW-PHASE-NOISE CMOS RING OSCILLATORS.
PLL bandwidth until about 500 MHz with approximately equal amplitude. As a result, it is important to minimize . Fully differential topologies improve the immunity to the supply and substrate noise at low frequencies. Unfortunately, they do not help much at high frequencies as their PSRR degrades. The impact of supply and substrate noise on the other PLL components is beyond the scope of this paper. In general, -stage differential ring oscillators are sensitive to power supply and substrate noise at frequencies close dc, , and its harmonics. Most practical systems are bandlimited and, therefore, the noise near dc is more important. Fully differential structures provide some common-mode rejection for lower frequencies. However, they have limited impact at higher frequencies. This increased rejection may have limited benefit because most VCOs are used within PLLs, where low-frequency noise is suppressed within the loop bandwidth and high-frequency noise is more of a problem. VI. CONCLUSION In this paper, we have introduced a set of ring-oscillator phase noise models which include the additive noise from the delay cells, up-converted noise from the bias and frequency control circuits and the supply/substrate noise. Our models are validated by simulations and measurement results. Our analysis suggests that fast rail-to-rail switching is needed to minimize ring-oscillator phase noise. Current bias circuits have to be avoided if possible to reduce the up-converted low-frequency noise. The supply and substrate noise degrade the oscillator phase noise . Fully differential topologies improve around dc and PSRR at low frequencies, but they provide little help at high frequencies. We have developed phase-noise models that not only predict ring-oscillator phase noise, but also provide an intuitive direction for low-phase-noise oscillator design. APPENDIX
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(33)
Equation (6) can be derived by replacing final expression in (33). B. Derivation for (9)
With the soft-clipping model, the voltage waveform is given by (7) and the ISF is given by (8). Now the rms value for the ISF is given in (34)
(34)
, (34) can be approximated by (35), which is For consistent with the linear model (35) value of the function drops sharply as increases from 0. Therefore, the integral in (34) is dominated by the contributions for values close to 0. In order to simplify the can be made for calculation, the approximation . This has insignificant impact on the result in (34) when . Now (34) can be approximated by (36)
For
In this Appendix we provide mathematical derivations for the phase noise with the hard-clipping model given in (6) and the phase noise with the soft-clipping model given in (9). A. Derivation for (6)
in (4) with the
the
The ISF expression in (5) can be rewritten in a different form , , 2, … as shown in (32) where for
(else).
(32)
The rms value for the ISF can be derived as shown in (33)
(36)
Let
. Then the result in (36) can be further
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derived as shown in (37)
[14] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1998, ch. 3. [15] Meta-Software, Cambridge, MA, HSPICE User’s Manual: Software for IC Design, version 96.1 ed., Feb. 1996. [16] D. P. Foty, MOSFET Modeling With SPICE: Principles and Practice. Englewood Cliffs, NJ: Prentice-Hall, 1996. [17] K. Joardar, “A simple approach to modeling cross-talk in integrated circuits,” IEEE J. Solid State Circuits, vol. 29, pp. 1212–1219, Oct. 1994.
(37) Combining (37) and (4), we can obtain the expression for the SSB phase noise as shown in (9). REFERENCES [1] T. C. Weigandt, B. Kim, and P. R. Gray, “Analysis of timing jitter in CMOS ring oscillators,” in Proc. IEEE Int. Symp. Circuits and Systems, vol. 4, London, U.K., June 1994, pp. 27–30. [2] B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J. SolidState Circuits, vol. 31, pp. 331–343, Mar. 1996. [3] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, pp. 179–194, Feb. 1998. [4] A. Hajimiri, S. Limotyrakis, and T. H. Lee, “Jitter and phase noise in ring oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 790–804, June 1999. [5] M. Thamsirianunt and T. A. Kwasniewski, “CMOS VCOs for pll frequency synthesis in GHz digital mobile radio communications,” IEEE J. Solid-State Circuits, vol. 32, pp. 1511–1524, Oct. 1997. [6] C.-H. Park and B. Kim, “A low-noise, 900-MHz VCO in 0.6-m CMOS,” IEEE J. Solid-State Circuits, vol. 34, pp. 586–591, May 1999. [7] H. Djahanshahi and C. A. T Salama, “Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications,” IEEE J. Solid-State Circuits, vol. 35, pp. 847–855, June 2000. [8] D. B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proc. IEEE, pp. 329–330, Feb. 1966. [9] J. Craninckx and M. S. J. Steyaert, “A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler,” IEEE J. Solid-State Circuits, vol. 30, pp. 1474–1482, Dec. 1995. , “A 1.8-GHz low-phase-noise CMOS VCO using optimized [10] hollow spiral inductors,” IEEE J. Solid-State Circuits, vol. 32, pp. 736–744, May 1997. [11] P. Kinget, “A fully integrated 2.7V 0.35m CMOS VCO for 5GHz wireless applications,” in IEEE ISSCC Dig. Tech. Papers, Feb. 1998, pp. 226–227. [12] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, pp. 1723–1732, Nov. 1996. [13] MOSIS website.. [Online]. Available: http://www.mosis.org
Liang Dai (S’96–M’01) was born in Beijing, China, in 1971. He received the B.S. degree in physics from Beijing University, Beijing, in 1995 and the M.S.E.E. and Ph.D. degrees from the University of Minnesota, Minneapolis, in 1998 and 2002, respectively. From 1998 to 1999, he worked as a Summer Intern at Lucent Technologies, Allentown, PA. Currently, he is a Staff Design Engineer at Prominent Communications, Inc., San Diego, CA. His main research interests involve high-performance mixed signal and RF IC design for communications systems. Dr. Dai was awarded the IEEE SSCS Predoctoral Fellowship from 2000 to 2001.
Ramesh Harjani (S’87–M’89–SM’00) received the B.S. degree in electrical engineering from the Birla Institute of Technology and Science, Pilani, India, the M.S. degree in electrical engineering from the Indian Institute of Technology, New Delhi, and the Ph.D. degree in electrical engineering from Carnegie Mellon University, Pittsburgh, PA, in 1982, 1984, and 1989, respectively. He was with Mentor Graphics Corporation, San Jose, CA, and spent several summers at Lucent Technologies in Allentown, PA. Currently, he is an Associate Professor in the Department of Electrical Engineering, University of Minnesota and a Member of the graduate faculty of the Department of Biomedical Engineering at the same university. He is a Cofounder of Bermai, Inc., a startup company developing CMOS chips for wireless applications. He is a coauthor of Design of Modulators for Oversampled Converters (New York: Kluwer, 1998) and Design of High-Performance CMOS Voltage-Controlled Oscillators (New York: Kluwer, 2002). His research interests include wireless communications circuits, low power analog design, sensor interface electronics and analog and mixed-signal circuit test. Dr. Harjani received the National Science Foundation Research Initiation Award in 1991. He received a Best Paper Award at the 1987 IEEE/ACM Design Automation Conference and an Outstanding paper award at the 1998 GOMAC. His research group was the winner of the SRC Copper Design Challenge “RF Front-End Design with Copper Passive Components.” He was an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING from 1995 to 1997 and the Chair of the IEEE Circuits and Systems Society Technical Committee on Analog Signal Processing from 1999 to 2000. He is a Distinguished Lecturer of the IEEE Circuits and Systems Society for 2001–2002.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 49, NO. 5, MAY 2002
Design of Low-Phase-Noise CMOS Ring Oscillators Liang Dai, Member, IEEE, and Ramesh Harjani, Senior Member, IEEE
Abstract—This paper presents a framework for modeling the phase noise in complementary metal–oxide–semiconductor (CMOS) ring oscillators. The analysis considers both linear and nonlinear operations, and it includes both device noise and digital switching noise coupled through the power supply and substrate. In this paper, we show that fast rail-to-rail switching is required in order to achieve low phase noise. Further, flicker noise from the bias circuit can potentially dominate the phase noise at low offset factor for ring oscillators frequencies. We define the effective with large and nonlinear voltage swings and predict its increase for CMOS processes with smaller feature sizes. Our phase-noise analysis is validated via simulation and measurement results for ring oscillators fabricated in a number of CMOS processes. Index Terms—complementary metal–oxide–semiconductor (CMOS) ring oscillator, phase noise, timing jitter, voltage-controlled oscillator (VCO).
elements, the phase noise for ring oscillators have traditionally been much larger than that of resonator-based oscillators. In this paper, we analyze the phase noise due to both the device noise and power supply/substrate noise. We present a modified linear model in Section II which considers the nonlinear impact of voltage clipping. In Section III, we define an effec) for the ring oscillators and predict an intive factor ( with the advance in the operating speed of CMOS crease in processes. In Section IV, we describe the noise up-conversion mechanism due to the bias and frequency control circuits. Then we discuss the impact of the digital switching noise coupled through the shared power supply and substrate in Section V. Finally we provide some conclusions in Section VI. Additional mathematical derivations can be found in the Appendix at the end of this paper.
I. INTRODUCTION
II. MODIFIED LINEAR MODEL
P
HASE-LOCKED loops (PLLs) are used extensively in communications systems. In particular, they are used as frequency synthesizers and clock recovery circuits. Voltage-controlled oscillators (VCOs) are important building blocks in PLLs. The random fluctuations in the output phase of the oscillator, in terms of jitter or phase noise, is undesirable in most applications. The VCO is the major contributor to the PLL output phase noise outside the PLL loop bandwidth. Hence VCOs with low phase noise have to be designed to meet stringent communications standards. Unfortunately, real oscillators are nonlinear time-variant systems such that traditional linear time-invariant analysis becomes invalid for phase noise studies. The design of complementary metal–oxide–semiconductor (CMOS) VCOs with low phase noise is a challenging research topic and has been studied extensively in recent years [1]–[4]. Many traditional oscillators are based on LC resonators. Due to the difficulties in the implementation of on-chip inductors and the limited frequency tuning range, resonatorless VCOs have drawn significant attention for system-on-a-chip solutions [4]–[7]. Among many possible circuit topologies, ring oscillators are promising candidates due to their ease of implementation and wide frequency tuning range. They are compatible with digital CMOS technologies and occupy small chip area. However, because they do not have high- frequency, selective
Manuscript received March 8, 2001; revised May 17, 2002. This paper was recommended by Associate Editor A. Hajimiri. L. Dai was with the University of Minnesota, Minneapolis, MN 55455 USA. He is now with Prominent Communications, San Diego, CA 92121 USA (e-mail: [email protected]). R. Harjani is with the University of Minnesota, Minneapolis, MN 55455 USA and also with Bermai Inc., Minnetonka, MN 55305 USA (e-mail: [email protected]). Publisher Item Identifier 10.1109/TCSII.2002.801409.
In this section, we will derive the relation between the phase noise and the internal signal swing from a modified linear model for ring oscillators. This model applies to the differential pairs and the load devices in the delay cells of the ring oscillators. We show that, in order to achieve phase noise comparable with that of the LC oscillators, fast transitions are needed, i.e., devices have to operate in a hard switching mode and be switched ON and OFF completely. Some measurement results for our test chips are also presented at the end of this section. A. Theoretical Analysis Fig. 1 shows a simplified model for a three-stage ring oscillator. Each delay stage consists of a resistor, a capacitor, a negacell, and a voltage limiter. The system is linear as long tive as the internal voltages are not clipped by the limiters. When the peak-to-peak voltage swing tries to exceed the supply voltage of and ground, the circuit, the waveform becomes clipped by and this is modeled by the limiters in Fig. 1. For this condition the single-sideband (SSB) phase noise can be represented by (1) [2], where is the Boltzmann’s constant and is the absolute temperature. The excess noise factor accounts for the total noise from the passive resistor and the active device [8]. represents the peak-to-peak signal voltage, is the is the offset from the center frequency of oscillation, and center frequency (1) Under linear operation, the voltage waveform is sinusoidal . For simwhich can be written as plicity we have neglected its dc component and assumed that it is . This is a good approximation for most centered around optimally designed oscillators. Neglecting the dc term has no
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DAI AND HARJANI: DESIGN OF LOW-PHASE-NOISE CMOS RING OSCILLATORS.
Fig. 1.
Modified linear model for a three-stage ring VCO.
Fig. 2.
Sinusoidal waveform clipped by power supplies.
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Fig. 3. Waveform with soft clipping.
impact on our following analysis. It has been shown in [3] that the impulse sensitivity function (ISF or )1 can be approximated as shown in (2) while its rms value is given by (3), respectively
It can be shown that (1) has to be modified for as shown in (6). Please refer to Appendix for detailed mathematical derivations
(2)
(3) Comparing (2) and (3), it is easy to see that the SSB phase noise for a three-stage ring oscillator can be expressed in terms as in (4). Even though this expression is derived for of a ring oscillator with linear operation, its validity extends into nonlinear operation of a ring oscillator due to voltage clipping, since the ISF automatically considers the nonlinear effects [3] (4) Here, we have only considered thermal noise. Since the linear model does not predict noise aliasing, only noise close to will cause phase noise in the above linear model. Even though flicker noise exists in CMOS oscillators, its magnitude is usually much smaller than the thermal noise at the oscillation frequency . Hence it is reasonable to neglect flicker noise in the linear model. A more rigorous analysis has shown that flicker noise does result in phase noise due to nonlinear and time-variant effects [3]. Nevertheless, we will not discuss the impact of flicker noise here, since, as we will show in Section IV, the dominant flicker noise sources are in the bias and frequency control circuits instead of the devices in the delay cell and it should be analyzed by a separate model. In a real circuit, the waveform is bounded by the power supplies for large amplitudes. Let us assume that the sinusoidal waveform is symmetrically clipped as shown in Fig. 2. Its ISF can be approximated by (5)
for
(6)
in (6) to represent the idealized peak-to-peak We use voltage of the sine wave as if there was no clipping. Equations (1) and (6) indicate that the phase noise is proportional to for linear operation and is proportional to when clipped by the power supplies. The additional noise reduction results when the voltage is clipped. Hence from the fact that the period when the oscillator is susceptible to noise is reduced as the transitions take less time. In reality, the clipping is rarely as hard as shown in Fig. 2. We model this “soft clipping” shown in Fig. 3 by (7) (7) The ISF is now given by (8) and the phase noise is then given by (9). The mathematical derivations for (9) can be found in the Appendix (8)
for (9) for
.
for B. Simulation Results for
. (5)
1The 0(! t) is a function that defines the impact on the output phase by a unit current impulse at time equal to t.
In Fig. 4 we show the SSB phase noise at 600-kHz offset from a 900-MHz carrier frequency as a function of different signal swings predicted by both of our hard-clipping and soft-clipping k , and models. Here we assume that V, which are typical values for practical designs.
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Fig. 4.
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SSB phase noise versus V .
Fig. 5. Bias and a delay cell for a ring oscillator with a source-coupled pair and symmetric loads.
Both results indicate that the phase noise consists of two re:a region without clipping and a gions with regard to region with clipping. This implies the additional reduction in phase noise when the idealized voltage swing tends to ). exceed the power supply ( The two models provide slightly different break-even points between the two regions. The break-even point for , the hard-clipping model is while the break-even point for the soft-clipping model is . The phase noise predicted by and only the two models are the same for small values of . Since both models differ by 1.76 dB for large values of provide similar predictions for the phase noise, we expect the exact shape of the nonlinear limiting not to significantly impact the phase noise performance. is directly related to the maximum slew rate by Since (10) when the transitions take place, as an alternative, (1), (6), . This is and (9) can also be expressed in terms of is not directly useful when the waveform is clipped and available. We will not rewrite the above equations here, since the derivation is mathematically straightforward (10) is equivalent to maximizing the switching Maximizing current. This suggests that improving the current switching efficiency can reduce the phase noise for given supply current. For a ring oscillator with fully differential delay cells, an ideal case would be that all the tail current is used for switching, i.e., a current switching efficiency of 100%. In practical delay cell topologies, the maximal current for charging and discharging the load capacitors sets a lower bond on the phase noise for given power consumption. A survey of published literature suggests that the phase noise of LC-tank oscillators is close to 120 dBc/Hz when the results are scaled to a 600-kHz offset from a 900-MHz center frequency [9]–[11]. They are located within the ellipse in Fig. 4. The phase noise curve for LC-tank oscillators is also plotted in k , and . Our calculathis figure for tion suggests that the phase noise for ring oscillators is likely to be much higher than that of LC-tank oscillators unless there
is rail-to-rail switching, and efficient switching is the only possible approach. C. Measurement Results As a first exercise we have designed two types of ring oscillators to validate our phase-noise model. Both of them have three delay stages. The bias circuit and the delay cell for one of them are shown in Fig. 5 (called Maneatis ring oscillator from now on in this paper). It contains a source coupled-differential pair and symmetric loads which provide good control over delay and high dynamic supply noise rejection [12]. The other oscillator is a coupled ring oscillator whose diagram is shown in Fig. 6. It contains two single-ended ring oscillators, namely a fast ring and a slow ring. Its frequency of oscillation can be tuned continuously between that of the fast ring and the slow ring. Both oscillators were fabricated in an HP 0.5- m CMOS technology through MOSIS. The chip microphotographs are shown in Fig. 7. As we are unable to measure the actual voltage swings without loading the oscillators, we use simulation reas a guide. We derive from in the sults for transient simulations for both oscillators. Our simulations sugmV for the Maneatis ring oscillator and gest that V for the coupled ring oscillator. The measured center frequency for the Maneatis oscillator is 1.38 GHz and the center frequency for the coupled ring oscillator is 960 MHz. For a fair comparison, the phase noise for both oscillators are scaled to a 600-kHz offset frequency from a 960-MHz carrier. Our measured SSB phase noise results for the two oscillators are 88 dBc/Hz and 114 dBc/Hz, respectively. Both measurement results are marked in Fig. 4 with circled plus signs. They match our theoretical predictions very well for fairly typical values for and . The difference of 26 dB/Hz in their SSB phase noise is primarily due to the difference in their values of . In Fig. 8, we plot the measured phase noise as a function of offset frequency. We note that the phase noise for the coupled ring oscillator is much lower than that for the Maneatis oscillator for all frequencies. It also rises faster at offset frequencies that are less than 300 kHz. We have run transient circuit simulations and extracted the ISFs and operating conditions for every device in the coupled ring oscillator. The result suggests that the
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(a)
(b)
(c)
(d)
Fig. 6. Three-stage coupled ring oscillator.
(a) Fig. 7.
(b)
Chip microphotographs for (a) Maneatis ring oscillator (b) coupled ring oscillator.
tant factor that determines the oscillator phase noise due to the differential pairs and the loads in the delay cells. In essence, fast rail-to-rail switching is needed to minimize phase noise. III.
FACTOR FOR RING OSCILLATORS
In the last section, we developed a modified linear model for the additive noise sources in a ring oscillator. In this section, we define an effective factor based on our model and predict its potential improvement for future technologies. For a linear model, the phase noise for an -stage ring oscillator can be written in terms of the factor as [2] Fig. 8. SSB phase noise comparison between the Maneatis oscillator and the coupled ring oscillator.
primary flicker-noise contributors are the fast inverters. It could have been reduced further by a more symmetric waveform design [3]. The simulation and measurement results provided in this section have validated our modified linear phase-noise model. Our model suggests that the signal voltage swing is the most impor-
(11) By comparing (11) and (1) for three-stage ring oscillator is considered.
, we can see that for a if no voltage clipping
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In the last section, we noted that voltage clipping helps reduce phase noise. Alternatively, we can think of this as an increase of for a threethe effective . By comparing (11) and (9), stage ring oscillator with large swings is given by (12)
(12) in terms of the of the It is also interesting to express , where is CMOS process, which is given by characterthe total gate capacitance of the MOS device. The izes the maximum speed for the devices in a certain technology.2 It sets a lower bond for the transition time. Therefore, it is an . important factor determining When a digital inverter is used as a delay stage, the maximum slew rate is determined by the current flowing through the negative-channel MOS (NMOS) or positive-channel MOS (PMOS) device that charges or discharges the load capacitance. In order to minimize the flicker noise, the NMOS and the PMOS devices are sized to achieve identical rise and fall times [3]. Hence, , where and are the carrier mobilities if for the NMOS and PMOS devices, respectively, then the W/L ratio for the PMOS device has to be times larger than that for the NMOS device. Now that the waveform has the same rise and fall time, we can use the discharging process to calculate the transition time. Other than the gate capacitances of the next delay stage, the load usually contains some additional capacitance from an output buffer which amplifies the internal voltage and sends it to the output. The buffer helps prevent load pulling or the variation of frequency due to any change in the output load. Let us assume that the additional load capacitance due to , where and are the gate the buffer is capacitances of the NMOS and PMOS transistors in the next stage, respectively. The maximum slew rate is now given by
(13) Therefore, the
is now given by (14)
f
2The actually defines the frequency at which the current gain of the device is equal to one.
Fig. 9. Effective
Q factor as a function of the f
CALCULATED
Q
FOR
of the process.
TABLE I PROCESSES AVAILABLE FROM MOSIS
Next, we use (14) to calculate the as a function of for different supply voltages, assuming , i.e., the negligible capacitance due to the buffer. For our analysis, we V. This assumption should hold have assumed that reasonably well, since the device threshold voltage does not change substantially for different processes. The results are for a number plotted in Fig. 9. We have also calculated of different processes available via MOSIS, including TSMC 0.35 m, TSMC 0.25 m, TSMC 0.18 m, HP 0.5 m, HP 0.35 m, AMI 1.5 m, AMI 0.8 m, and AMI 0.5 m [13]. s for these processes were obtained by simulating a The transistor with the gate voltage set to be equal to the power are supply voltage. The maximum slew rates derived from the measured results for ring oscillators from MOSIS. Then (12) is used to calculate the effective . The results are summarized in Table I and also shown Fig. 9. It with larger can be seen that there is a trend for higher values for the various technologies. However, it should be noted ’s of future processes are not likely to that the realizable increase as rapidly due to the reduced supply voltages and the close to four is lag in PMOS devices. Fig. 9 projects that a possible at 900 MHz for future processes. If this is achieved, the phase noise for ring oscillators is likely to be comparable to that of LC-tank oscillators with on-chip spiral inductors. Furthermore, ring oscillators still retain their better integration properties and larger frequency tuning range.
DAI AND HARJANI: DESIGN OF LOW-PHASE-NOISE CMOS RING OSCILLATORS.
Fig. 10.
Bias structure for an
N -stage ring oscillator.
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following derivation, we assume that the current mirrors have a ratio of 1 : m as shown in Fig. 10. In general, the oscillation frequency is proportional to , where is the load capacitance for each delay cell. for a three-stage ring As an example, includes a voltage-dependent part, oscillator. Even though in its variation is usually much smaller than the variation in the presence of noise. We can, therefore, derive the relation in (15) using this assumption (15) of each When operated in the long channel regime, the , where is the delay cell is given by tail current. This is valid for all the reasonable gate overdrive voltages . Using (15), it can be shown that (16) is valid for small signal amplitudes
Fig. 11. bias.
Up-conversion mechanism for low-frequency noise in the tail and
(16) IV. NOISE UP-CONVERSION
In a fully differential ring oscillator, low-frequency noise close to dc from the bias and the tail devices is up-converted to the vicinity of the carrier frequency by frequency modulation. This is not modeled by our analysis in the previous section or any previously published work. In this section, we analyze this noise up-conversion mechanism and validate it via simulations and measurement results. A. Theoretical Analysis An -stage ring oscillator is generally biased as shown in of the Fig. 10. Noise in the tail current devices causes the delay cell to change, hence varying the instantaneous oscillation frequency. We derive mathematical expressions to show the impact of bias noise on the overall oscillator phase noise. We will first consider thermal noise, and then extend our analysis to include flicker noise. This up-conversion mechanism can be illustrated with the help of Fig. 11. First, the noise is band-limited by the poles , , , , . This low-pass filtered at the drains of of the delay cells, and results in noise then modulates the in the frequency variation. Finally, since in the frequency dotime domain, they satisfy main. This analysis suggests that the phase noise has a shape at low offset frequencies and drops off at a faster rate for higher offset frequencies. However, since the low-pass bandwidth is usually much larger than the oscillation frequency, the faster phase noise roll-off is rarely observed because other noise sources start to dominate. So it is of little interest. Additionally, we are usually more concerned with the up-conversion of the low-frequency noise. This is more of an issue when flicker noise is present and causes the phase noise to rise at a more rapid rate at low offset frequencies. separately from We treat the noise from the bias transistor , , , in Fig. 10, the noise contributed by transistors is correlated for all because the low-frequency noise from , , , is not. In the stages while the noise from
is , The thermal-noise density from is the for . The noise power is amplified where times by each tail device. We can also replace by with for the tail devices. Hence, the normalized variation in frequency is given by (17) (17) Finally, we can write the resulting phase noise as shown in (18)
(18) to is treated in a similar manner to The noise from except that the noise is uncorrelated for each the noise from tail device. When we consider the frequency variation due to a single delay cell, (16) has to be modified as shown in (19) where and are the and for the th delay cell (19) delay stages, the resulting phase Considering that there are noise expression is given by (20) (20) is 1/4 of , since the variThe SSB phase noise ation in phase generates correlated phase noise on both sides of the carrier. Therefore, the total noise contributed by the bias
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transistor (21)
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[(18)] and the
tail devices [(20)] is given by
(21) The up-conversion of flicker noise can be treated in a similar fashion. If the flicker noise is modeled as in (22) [15] (22) and are flicker noise parameters. Then (21) can where be modified for flicker noise as shown in (23) (23)
Fig. 12.
Bias and a delay cell for a three-stage ring oscillator.
0
, the up-conversion Since is usually much larger than is likely to be more severe than that from of the noise from could be the tail devices. In practice, the flicker noise from the major noise source at low offset frequencies. To take into account of short channel effects, the drain-to-source current can be modeled as shown in (24) [16]
TABLE II AND
0
(24) and are empirical numbers. They approach 0 for where long channel devices and take on larger values for short channel devices. We use this format for short channel devices, because it maintains the simplicity of our equations. Here represents the linear reduction in mobility due to short channel effects, and represents the reduction of the exponent from the quadratic and to the linear for extremely short devices. Values for can be obtained from simulations or by equating (24) with traditional short channel equations [14]. By following a similar derivation as above, it can be shown that (25) becomes smaller for short channel The factor devices. As a result, both (21) and (23) have to be multiplied by to account for short channel effects. B. Simulation Results We have simulated a three-stage ring oscillator as an example whose bias circuit and one of the delay cells are shown in Fig. 12. The frequency of the oscillator is controlled by the supplied through . We apply the analysis bias current methodology proposed in by injecting a current pulse into the nodes 1, 2, and 3 throughout a complete clock cycle and observe the phase shift after it settles into steady state again. ) which are modulated by the thermal The effective ISFs ( and flicker noise are calculated for each individual device. ’s are imAs mentioned in [3], the rms values for the ’s are portant for thermal noise and the mean values of the important for flicker noise. Table II lists the rms values for ’s and mean values for ’s for all the tran-
Fig. 13.
Simulation of frequency variation versus bias current variation.
sistors. It can be seen that the thermal noise contribution of all the devices are similar in magnitude, though the contribution is slightly larger than the others. However, for flicker of and dominate, suggesting that noise the contributions of the majority of the low-frequency phase noise is contributed by the bias devices. in the bias. In We have only included a single device reality, more devices are often used for the bias. For example, a voltage-to-current converter is usually needed between the loop filter and the VCO in a PLL. Any low-frequency noise generated is equivalent to an increase in the noise from and in could potentially dominate the low-frequency phase noise. We verify (16) in our noise up-conversion model by simulating the circuit in Fig. 12. We vary the bias current, and observe the variation in frequency in the steady state. We assume is proportional to and is the same for dc and . Fig. 13 provides the comany low-frequency variation in and . parison between and are drawn as In Fig. 13 both is given a functions of the bias current. In the simulations
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(a)
(b) Fig. 15. VCO block diagram (a) traditional view (b) rigorous view.
Fig. 14.
Phase noise with different bypass capacitors.
fixed value so that is swept linearly. Therefore, the curve of drops at a slope of 20 dB/decade. The two curves match extremely well for low bias currents. The error increases with larger bias current because of short channel effects and current mirror mismatch due to the channel length modulation. increases, the mismatch between the drain voltWhen and increases. This causes not to increase as ages of . As a result, the oscillation frequency becomes much as , and the curve of falls further less sensitive to in Fig. 13 for the increased below the curve of bias currents. Despite short channel effects and channel length modulation effects, our simulations confirm our model for noise up-conversion. Our conclusions are further strengthened by our measurement results discussed next. C. Measurement Results Again, we use measurement results for the Maneatis oscillator shown in Fig. 5. Fig. 14 provides the measurement results for the circuit tested under two conditions. In the first experiment, a 100- F bypass capacitor is connected between the bias is filtered point and ground so that most of the noise from out and does not cause phase noise. In the second experiment, a 11.7-nF capacitor is used instead.3 Due to the higher low-pass is corner frequency, some of the low-frequency noise from up-converted to phase noise by frequency modulation. With a large bypass capacitor, the phase noise curve retains the characteristic of the thermal noise. With a small bypass capacitor, the phase noise curve starts to rise faster at low offset freregion. This implies that the flicker quencies and enters the noise from the bias transistor can dominate at low frequencies which confirms our previous theoretical analysis. In a practical PLL design, the bias point is an internal node and no large off-chip capacitor is available to bypass the flicker and other transistors in the bias circuit. Furnoise from thermore, no additional low-frequency poles can be placed at the VCO frequency control port in a PLL due to stability concerns. Therefore, without this filtering possibility the flicker noise level can become so high that it is even dominant at frequencies beyond the loop bandwidth and cannot be suppressed by the PLL. This is particularly an important issue for low-band3We use such large capacitor values because the filter corner frequency is set by g =C where C is the bypass capacitor value.
Fig. 16. Three-stage differential ring oscillator.
width PLLs. Therefore, for integrated VCO designs, the current mirror bias structure should be avoided if possible. V. POWER SUPPLY/SUBSTRATE NOISE So far, we have analyzed the impact on phase noise caused by intrinsic device noise. When the oscillator is fabricated on the same silicon substrate and shares the same power supply with digital circuits, there is a significant amount of noise due to the digital switching activity coupled through the common power supply and the substrate. In this section, we will analyze the impact of the supply and substrate noise. A. Theoretical Analysis The output frequency of the VCO is traditionally considered only as a function of the control voltage, and the VCO is viewed as a block which does frequency modulation (FM). It has one input port and one output port. This is shown in Fig. 15(a). However, a more rigorous view of the VCO is shown in Fig. 15(b). , but also the power The VCO is not only controlled by supply and the substrate. In addition to frequency variations (FM), changes in the inputs also cause instantaneous phase shift at the output, resulting in phase modulation (PM) as well. Since a change in the output frequency causes the phase noise to accumulate, FM is usually the dominant factor, and PM can be neglected. In the following discussion, we will focus on the power supply noise. The impact of the substrate noise can be derived similarly. We will study the ISF for the power supply first. For an -stage differential ring oscillator operating at frequency , it can be shown that its ISF is a periodic function with a , i.e. frequency of (26) Let us consider the three-stage differential ring oscillator as shown in Fig. 16. Fig. 17 illustrates the waveforms for the internal nodes A, A′, B, B′, C, and C′. It is seen from Fig. 17 that the oscillator goes through six equivalent states in a clock cycle,
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Fig. 17. Waveforms showing the six equivalent states for a three-stage oscillator.
hence the ISF for has a frequency of . This can be generalized to an -stage differential ring oscillator whose ISF for has a frequency of . Based on the analysis in [4], only supply and substrate noise will make major whose frequency is close to dc and . It contribution to the VCO phase noise where can be shown that for supply noise close to dc, the SSB phase is the noise is given by (27) where is the noise amplitude, is the noise frequency dc term for and
Fig. 18.
Sideband PSD when sinusoidal ripple is added to the power supply.
As a result, the rms value for the period jitter is defined by (31). It is interesting to note that it is independent of the frequency of the supply and substrate noise (31)
B. Simulation Results (27) , the SSB phase noise is given For supply noise close to is by (28) where is the th Fourier coefficient for and the offset frequency from (28) From (27) and (28), it can be seen that, for supply noise either , the resulting phase noise is inversely proclose to dc or . However, the previous statement is not preportional to is a function of frequency. We shall provide cisely true when more details of this discrepancy later in this section. In most is at multiple high-frequency applications, the frequency gigahertz and above. However, the majority of the power supply noise is closer to dc than to any of the harmonic frequencies. As a result, the low-frequency supply noise has more of an impact on the ring-oscillator phase noise, and (27) can be used for most practical design considerations. There are also applications where the clock jitter is more of a concern. It is beneficial to discuss the impact of the supply and substrate noise in terms of jitter. In particular, we will use the which is the variation of the clock period. term period jitter where With low-frequency supply noise the instantaneous frequency of oscillation is given by (29) Hence
(30)
Due to the presence of decoupling capacitors on the circuit board and the bond wire inductance, it is hard to precisely control and measure the ripple that the circuit sees on the power supply. Therefore, we use simulations results to verify our power supply noise model on a three-stage Maneatis ring oscillator. We introduce a sinusoidal ripple with a peak voltage of 0.1 V added to the power supply for these simulations. Fig. 18 shows the sideband power spectral density (PSD) as a . In particular, the frequency function of the offset frequency , , and where of the ripple signal is at MHz and . It can be seen from the figure that, for frequencies close to , the PSD for the phase noise drops at a rate of dc and increases for higher frequencies. The lower 20 dB/dec as rate for frequencies less than 100 MHz is because the delay cell has a fully differential topology whose power supply rejection ratio (PSRR) improves at low frequencies. In other words, its becomes smaller at low frequencies. As a result, the curve stops increasing at low offset frequencies. for We have also simulated the oscillator with the ripple freclose to . As shown in Fig. 18, we do not see a quency slope as in the case of and . Instead, it only changes slightly over frequency. Additionally, we note that and its absolute value is lower than for both for low offset frequencies. In a practical CMOS PLL design, high frequency supply and substrate noise is usually more problematic due to reduced isolation at higher frequencies [17]. In [17], the noise power increases at a rate of 20 dB/decade over frequency until about 500 MHz. If we neglect the impact of supply and substrate noise on the other components in a PLL and use the results in [17] and Fig. 18, the supply and substrate noise causes spurs beyond the
DAI AND HARJANI: DESIGN OF LOW-PHASE-NOISE CMOS RING OSCILLATORS.
PLL bandwidth until about 500 MHz with approximately equal amplitude. As a result, it is important to minimize . Fully differential topologies improve the immunity to the supply and substrate noise at low frequencies. Unfortunately, they do not help much at high frequencies as their PSRR degrades. The impact of supply and substrate noise on the other PLL components is beyond the scope of this paper. In general, -stage differential ring oscillators are sensitive to power supply and substrate noise at frequencies close dc, , and its harmonics. Most practical systems are bandlimited and, therefore, the noise near dc is more important. Fully differential structures provide some common-mode rejection for lower frequencies. However, they have limited impact at higher frequencies. This increased rejection may have limited benefit because most VCOs are used within PLLs, where low-frequency noise is suppressed within the loop bandwidth and high-frequency noise is more of a problem. VI. CONCLUSION In this paper, we have introduced a set of ring-oscillator phase noise models which include the additive noise from the delay cells, up-converted noise from the bias and frequency control circuits and the supply/substrate noise. Our models are validated by simulations and measurement results. Our analysis suggests that fast rail-to-rail switching is needed to minimize ring-oscillator phase noise. Current bias circuits have to be avoided if possible to reduce the up-converted low-frequency noise. The supply and substrate noise degrade the oscillator phase noise . Fully differential topologies improve around dc and PSRR at low frequencies, but they provide little help at high frequencies. We have developed phase-noise models that not only predict ring-oscillator phase noise, but also provide an intuitive direction for low-phase-noise oscillator design. APPENDIX
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(33)
Equation (6) can be derived by replacing final expression in (33). B. Derivation for (9)
With the soft-clipping model, the voltage waveform is given by (7) and the ISF is given by (8). Now the rms value for the ISF is given in (34)
(34)
, (34) can be approximated by (35), which is For consistent with the linear model (35) value of the function drops sharply as increases from 0. Therefore, the integral in (34) is dominated by the contributions for values close to 0. In order to simplify the can be made for calculation, the approximation . This has insignificant impact on the result in (34) when . Now (34) can be approximated by (36)
For
In this Appendix we provide mathematical derivations for the phase noise with the hard-clipping model given in (6) and the phase noise with the soft-clipping model given in (9). A. Derivation for (6)
in (4) with the
the
The ISF expression in (5) can be rewritten in a different form , , 2, … as shown in (32) where for
(else).
(32)
The rms value for the ISF can be derived as shown in (33)
(36)
Let
. Then the result in (36) can be further
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derived as shown in (37)
[14] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1998, ch. 3. [15] Meta-Software, Cambridge, MA, HSPICE User’s Manual: Software for IC Design, version 96.1 ed., Feb. 1996. [16] D. P. Foty, MOSFET Modeling With SPICE: Principles and Practice. Englewood Cliffs, NJ: Prentice-Hall, 1996. [17] K. Joardar, “A simple approach to modeling cross-talk in integrated circuits,” IEEE J. Solid State Circuits, vol. 29, pp. 1212–1219, Oct. 1994.
(37) Combining (37) and (4), we can obtain the expression for the SSB phase noise as shown in (9). REFERENCES [1] T. C. Weigandt, B. Kim, and P. R. Gray, “Analysis of timing jitter in CMOS ring oscillators,” in Proc. IEEE Int. Symp. Circuits and Systems, vol. 4, London, U.K., June 1994, pp. 27–30. [2] B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J. SolidState Circuits, vol. 31, pp. 331–343, Mar. 1996. [3] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, pp. 179–194, Feb. 1998. [4] A. Hajimiri, S. Limotyrakis, and T. H. Lee, “Jitter and phase noise in ring oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 790–804, June 1999. [5] M. Thamsirianunt and T. A. Kwasniewski, “CMOS VCOs for pll frequency synthesis in GHz digital mobile radio communications,” IEEE J. Solid-State Circuits, vol. 32, pp. 1511–1524, Oct. 1997. [6] C.-H. Park and B. Kim, “A low-noise, 900-MHz VCO in 0.6-m CMOS,” IEEE J. Solid-State Circuits, vol. 34, pp. 586–591, May 1999. [7] H. Djahanshahi and C. A. T Salama, “Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications,” IEEE J. Solid-State Circuits, vol. 35, pp. 847–855, June 2000. [8] D. B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proc. IEEE, pp. 329–330, Feb. 1966. [9] J. Craninckx and M. S. J. Steyaert, “A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler,” IEEE J. Solid-State Circuits, vol. 30, pp. 1474–1482, Dec. 1995. , “A 1.8-GHz low-phase-noise CMOS VCO using optimized [10] hollow spiral inductors,” IEEE J. Solid-State Circuits, vol. 32, pp. 736–744, May 1997. [11] P. Kinget, “A fully integrated 2.7V 0.35m CMOS VCO for 5GHz wireless applications,” in IEEE ISSCC Dig. Tech. Papers, Feb. 1998, pp. 226–227. [12] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, pp. 1723–1732, Nov. 1996. [13] MOSIS website.. [Online]. Available: http://www.mosis.org
Liang Dai (S’96–M’01) was born in Beijing, China, in 1971. He received the B.S. degree in physics from Beijing University, Beijing, in 1995 and the M.S.E.E. and Ph.D. degrees from the University of Minnesota, Minneapolis, in 1998 and 2002, respectively. From 1998 to 1999, he worked as a Summer Intern at Lucent Technologies, Allentown, PA. Currently, he is a Staff Design Engineer at Prominent Communications, Inc., San Diego, CA. His main research interests involve high-performance mixed signal and RF IC design for communications systems. Dr. Dai was awarded the IEEE SSCS Predoctoral Fellowship from 2000 to 2001.
Ramesh Harjani (S’87–M’89–SM’00) received the B.S. degree in electrical engineering from the Birla Institute of Technology and Science, Pilani, India, the M.S. degree in electrical engineering from the Indian Institute of Technology, New Delhi, and the Ph.D. degree in electrical engineering from Carnegie Mellon University, Pittsburgh, PA, in 1982, 1984, and 1989, respectively. He was with Mentor Graphics Corporation, San Jose, CA, and spent several summers at Lucent Technologies in Allentown, PA. Currently, he is an Associate Professor in the Department of Electrical Engineering, University of Minnesota and a Member of the graduate faculty of the Department of Biomedical Engineering at the same university. He is a Cofounder of Bermai, Inc., a startup company developing CMOS chips for wireless applications. He is a coauthor of Design of Modulators for Oversampled Converters (New York: Kluwer, 1998) and Design of High-Performance CMOS Voltage-Controlled Oscillators (New York: Kluwer, 2002). His research interests include wireless communications circuits, low power analog design, sensor interface electronics and analog and mixed-signal circuit test. Dr. Harjani received the National Science Foundation Research Initiation Award in 1991. He received a Best Paper Award at the 1987 IEEE/ACM Design Automation Conference and an Outstanding paper award at the 1998 GOMAC. His research group was the winner of the SRC Copper Design Challenge “RF Front-End Design with Copper Passive Components.” He was an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING from 1995 to 1997 and the Chair of the IEEE Circuits and Systems Society Technical Committee on Analog Signal Processing from 1999 to 2000. He is a Distinguished Lecturer of the IEEE Circuits and Systems Society for 2001–2002.
