Department of Electrical and Computer Engineering McGill University ...
Department of Electrical and Computer Engineering McGill University ECSE 221A Introduction to Computer Engineering I Mid Term Exam Examiner: F.P. Ferrie Question 1
Date: March 1, 2004
(2 points)
Calculate the number of significant figures (decimal) that can be represented using the IEEE 754 floating point representation if the mantissa were extended to 24 bits. Question 2
(4 points)
Encode the number –8.41 x 1023 using IEEE 754 encoding and express your result as a 8-digit hexadecimal number. Question 3
(2 points)
Divide 10010010 by 1101 using binary division. Show your work and express the result in octal notation. Question 4
(2 points)
Explain why most floating point representations encode the exponent using a bias instead of a twos-complement scheme. Question 5
(2 points)
Determine what is produced by the following "C" program: int main() { char c=0x41; printf("Variable c contains %c\n",c|0x20); } Question 6
(2 points)
How many bits are required to encode a voltage in the range [-4,16] V assuming a resolution of 1.0 mV? Question 7
(2 points)
Let F(a,b,c) be a binary-valued function of 3 binary-valued variables, a, b, and c. How many different functions F are possible? (turn page over – more questions on back)
Question 8
(6 points)
Derive the minimal ∑∏ and ∏∑ forms for a function F =
∑ (0,1,2,4,6,12,14) .
Prove the
A,B ,C ,D
resulting forms are equal, and show the corresponding NAND-NAND and NOR-NOR implementations. Draw the circuit diagram for a 2-input NAND gate and 2-input NOR gate respectively using LogicWorks X-gates (no resistors). € Question 9
(4 points)
Assuming that full adders are available, draw the circuit diagram for a 4-bit full adder, clearly labeling all inputs and outputs. Determine the propagation delay for this circuit assuming that the full-adder modules are fabricated using NAND-NAND logic, and with all gates having an identical propagation delay of 5nS. Question 10 (2 points) Write down the state transition table for a J-K flip-flop and derive the corresponding next state equation Qˆ = F(J, K,Q) . Question 11 (2 points) Fill in the timing diagram corresponding to the circuit shown below. You may do this directly on the question sheet (make sure to put your name on the question sheet and hand it in with your answer booklet). +5V
D Clk
S
Q
Q
C R Q
R
200 R Clk Q
400
Date: March 1, 2004
(2 points)
Calculate the number of significant figures (decimal) that can be represented using the IEEE 754 floating point representation if the mantissa were extended to 24 bits. Question 2
(4 points)
Encode the number –8.41 x 1023 using IEEE 754 encoding and express your result as a 8-digit hexadecimal number. Question 3
(2 points)
Divide 10010010 by 1101 using binary division. Show your work and express the result in octal notation. Question 4
(2 points)
Explain why most floating point representations encode the exponent using a bias instead of a twos-complement scheme. Question 5
(2 points)
Determine what is produced by the following "C" program: int main() { char c=0x41; printf("Variable c contains %c\n",c|0x20); } Question 6
(2 points)
How many bits are required to encode a voltage in the range [-4,16] V assuming a resolution of 1.0 mV? Question 7
(2 points)
Let F(a,b,c) be a binary-valued function of 3 binary-valued variables, a, b, and c. How many different functions F are possible? (turn page over – more questions on back)
Question 8
(6 points)
Derive the minimal ∑∏ and ∏∑ forms for a function F =
∑ (0,1,2,4,6,12,14) .
Prove the
A,B ,C ,D
resulting forms are equal, and show the corresponding NAND-NAND and NOR-NOR implementations. Draw the circuit diagram for a 2-input NAND gate and 2-input NOR gate respectively using LogicWorks X-gates (no resistors). € Question 9
(4 points)
Assuming that full adders are available, draw the circuit diagram for a 4-bit full adder, clearly labeling all inputs and outputs. Determine the propagation delay for this circuit assuming that the full-adder modules are fabricated using NAND-NAND logic, and with all gates having an identical propagation delay of 5nS. Question 10 (2 points) Write down the state transition table for a J-K flip-flop and derive the corresponding next state equation Qˆ = F(J, K,Q) . Question 11 (2 points) Fill in the timing diagram corresponding to the circuit shown below. You may do this directly on the question sheet (make sure to put your name on the question sheet and hand it in with your answer booklet). +5V
D Clk
S
Q
Q
C R Q
R
200 R Clk Q
400
