McGill University Department of Electrical and Computer Engineering ...
McGill University Department of Electrical and Computer Engineering ECSE 221 Introduction to Computer Engineering I Assignment 3 – Sequential Logic Due: Monday, March 9th 2012 at 5:00 pm Question 1 Implement a J-K edge-triggered flip-flop using the design shown in the notes. Make sure not to introduce any additional delays in the circuit. Ensure that each gate has exactly Tpd = 1 nS (this should be the default). Your task is to determine the flip-flop timing parameters: Tsu, Th, and Tpd. Analysis of this circuit is fairly complicated, so an empirical approach will be used. First, we need to determine appropriate values of Tsu and Th that will permit correct operation of the circuit. A good starting point is to use the delay measured from S or R to Q as an initial value for both Tsu and Th. A LogicWorks simulation will quickly verify whether this choice is correct; Tpd can simply be read off the timing diagram. To determine Tsu and Th, you need to devise a simulation that incrementally reduces one parameter while holding the other fixed. The point at which the simulation fails determines the critical point for the respective timing parameters.
Question 2 Consider the following circuit diagram:
a) First, determine the 6 flip-flop equations corresponding to J0, K0, J1, K1, J2, and K2 respectively. This is accomplished by tracing through the schematic. Next derive the next-state equation corresponding to each flip-flop, and use these equations to fill in the state transition table corresponding to the circuit. Also produce the corresponding state diagram. b) The state transition table describes the logical behaviour of the circuit, but does not provide any information about timing. You look up the specifications for the circuit components and determine that the flip-flops have set-up, hold, and propagation delay times of 4 nS, 4 nS, and 16 nS respectively. All gates all have identical propagation delay times of 5nS, regardless of the number of inputs. Use this information to determine the maximum operating frequency of the circuit and to produce a detailed timing diagram showing the relationship of the Q0, Q1, and Q2 outputs to the clock and M inputs. c) Assuming that the actual clock is fixed at 5 Khz (considerably less than the maximum operating frequency of the circuit), the entire circuit can easily be replaced by an inexpensive microcontroller chip. For such purposes, write a function in C that implements the state machine corresponding to the circuit according to the following prototype: void MyStateMachine (char M, char *Q2, char *Q1, char *Q0); You may assume that this routine is called periodically every 200 uS. Show that your code implements the state machine correctly by writing a suitable test routine.
Question 3 The Universal Counter shown in the notes is comprised of 4 1-bit Universal Counter Cells. Starting with the counter as your building block, do the following: a) Modify the 4-bit counter design to include an enable, E, input, so that the counter is forced into HOLD mode when E=0 and the counter is counting UP or DOWN. Assuming that all flip-flops have identical characteristics, i.e., Tsu = 1nS, Th = 1nS, Tpd = 5nS, all gates have Tpd = 2nS, and that multiplexers are implemented as in the notes, determine the maximum frequency of operation of this counter. Construct a LogicWorks simulation to demonstrate breakdown of the counter at frequencies higher than the maximum you predicted. b) Use your counter module to design a modulo-N (actually N+1 since the count starts from 0) counter according to the following diagram:
Clk clock input Clr’ asynchronous clear (active low) E count enable M7..0 maximum count from zero (8-bit) Q7..0 count output (8-bit) CO carry output (to cascade more counters)
Perform a timing analysis and predict the maximum frequency of operation of this counter. Verify your calculations with a LogicWorks simulation as in Part (b).
Use the UCC to build the Universal Counter as follows:
Question 4 A 4-bit counter is to be designed according to the following specifications.
M1 0 0 1 1
M0 0 1 0 1
Function Hold: [Q3..Q0] retain their state on the next clock Count Up: [Q3..Q0] [Q3..Q0]+1 Count Down: [Q3..Q0] [Q0..Q0]-1 Synchronous Clear: [Q3..Q0] [0..0]
a) Produce the state diagram and state transition table corresponding to this counter. Make sure to clearly label your diagram. b) Implement your counter using a PROM and a 4-bit register (available in LogicWorks). c) Perform a timing analysis for your circuit, assuming that Ta (PROM) = 10 nS, and that the register has Tsu = 1 nS, Th = 0 nS, and Tpd = 2 nS. Determine the maximum frequency of operation. d) Produce a LogicWorks simulation of your counter. Scale the delays accordingly so that simulation mimics the expected timing of the physical implementation.
Question 2 Consider the following circuit diagram:
a) First, determine the 6 flip-flop equations corresponding to J0, K0, J1, K1, J2, and K2 respectively. This is accomplished by tracing through the schematic. Next derive the next-state equation corresponding to each flip-flop, and use these equations to fill in the state transition table corresponding to the circuit. Also produce the corresponding state diagram. b) The state transition table describes the logical behaviour of the circuit, but does not provide any information about timing. You look up the specifications for the circuit components and determine that the flip-flops have set-up, hold, and propagation delay times of 4 nS, 4 nS, and 16 nS respectively. All gates all have identical propagation delay times of 5nS, regardless of the number of inputs. Use this information to determine the maximum operating frequency of the circuit and to produce a detailed timing diagram showing the relationship of the Q0, Q1, and Q2 outputs to the clock and M inputs. c) Assuming that the actual clock is fixed at 5 Khz (considerably less than the maximum operating frequency of the circuit), the entire circuit can easily be replaced by an inexpensive microcontroller chip. For such purposes, write a function in C that implements the state machine corresponding to the circuit according to the following prototype: void MyStateMachine (char M, char *Q2, char *Q1, char *Q0); You may assume that this routine is called periodically every 200 uS. Show that your code implements the state machine correctly by writing a suitable test routine.
Question 3 The Universal Counter shown in the notes is comprised of 4 1-bit Universal Counter Cells. Starting with the counter as your building block, do the following: a) Modify the 4-bit counter design to include an enable, E, input, so that the counter is forced into HOLD mode when E=0 and the counter is counting UP or DOWN. Assuming that all flip-flops have identical characteristics, i.e., Tsu = 1nS, Th = 1nS, Tpd = 5nS, all gates have Tpd = 2nS, and that multiplexers are implemented as in the notes, determine the maximum frequency of operation of this counter. Construct a LogicWorks simulation to demonstrate breakdown of the counter at frequencies higher than the maximum you predicted. b) Use your counter module to design a modulo-N (actually N+1 since the count starts from 0) counter according to the following diagram:
Clk clock input Clr’ asynchronous clear (active low) E count enable M7..0 maximum count from zero (8-bit) Q7..0 count output (8-bit) CO carry output (to cascade more counters)
Perform a timing analysis and predict the maximum frequency of operation of this counter. Verify your calculations with a LogicWorks simulation as in Part (b).
Use the UCC to build the Universal Counter as follows:
Question 4 A 4-bit counter is to be designed according to the following specifications.
M1 0 0 1 1
M0 0 1 0 1
Function Hold: [Q3..Q0] retain their state on the next clock Count Up: [Q3..Q0] [Q3..Q0]+1 Count Down: [Q3..Q0] [Q0..Q0]-1 Synchronous Clear: [Q3..Q0] [0..0]
a) Produce the state diagram and state transition table corresponding to this counter. Make sure to clearly label your diagram. b) Implement your counter using a PROM and a 4-bit register (available in LogicWorks). c) Perform a timing analysis for your circuit, assuming that Ta (PROM) = 10 nS, and that the register has Tsu = 1 nS, Th = 0 nS, and Tpd = 2 nS. Determine the maximum frequency of operation. d) Produce a LogicWorks simulation of your counter. Scale the delays accordingly so that simulation mimics the expected timing of the physical implementation.
