McGill University Department of Electrical and Computer ...
McGill University Department of Electrical and Computer Engineering Course: ECSE 323 -Digital Systems Design Winter 2012 Assignment #2 – Friday Student Name and ID:
TOPIC: Tabular Method & CMOS Logic Exercise 1
(45 points)
Use the tabular method of Quine-McCluskey to find a minimum cost SOP realization for the function f(x1, …, x4) = Σm(0,4,6,8,9,15) + D(3,7,11,13) Exercise 2
a) Which gate is not a valid CMOS gate?
(5 points)
b) By observing the PUN and PDN of the invalid logic gate, find the functionality of both PUN and PDN. (10 points) c) Regarding the invalid CMOS gate, find three input combinations, under which both PUN and PDN are turned off? (10 points) d) Does the invalid CMOS gate suffer from static power consumption? Explain why? (10 points) Exercise 3 A Berkeley student has designed a CMOS gate as follows:
a) Find an input combination, which results in a static power consumption problem. (5 points) b) For the above input combination find the voltage at the node Y. Note that we have Vdd=2V, and all the NMOS (PMOS) transistors in their ON mode are modeled with a single resistor with the conductance of 2G (G). Is this voltage at node Y a weak-high or a weak-low? (15 points)
McGill University Department of Electrical and Computer Engineering
Course: ECSE 323 -Digital Systems Design Winter 2012 Assignment #2 – Friday Solutions
TOPIC: Tabular Method & CMOS Logic Exercise 1
(Answer) The prime implicants are generated as follows:
The initial prime implicant table is
(45 points)
There are no essential prime implicants. Prime implicant p3 dominates p5 and their costs are the same, so remove p5. Similarly, p7 dominates p6, so remove p6. This gives
Now, p3 and p7 are essential, which leaves
Choosing p2 results in the minimum cost cover
and the function is implemented as
Exercise 2: a) (5 points) Gate#1 is invalid. In CMOS technology, whenever 2 transistors are in parallel in one network, their dual should be in serial in the other network. In gate 1, B and C are in parallel in both PUN and PDN. So, gate 1 is not a valid CMOS gate. b) (10 points) For Gate#1 PUN: A’B’D’+E’C’ PDN: (DE+C(A+B))’=(D’+E’)(C’+A’B’) =E’C’+D’C’+D’A’B’+E’A’B’ not equal to PUN c) (10 points) D=C=0, E=1, AB=01, 10, or 11. Another solution is when E=0, C=1, A=0, B=0, D=1 d) (10 points) No, since there does not exist an input combination under which both PDN and PUN are turned on.
Exercise 3:
a) (5 points) C=1, A=0, B=0 b) (15 points): Y=2*(1/2)/(1/2+2)=0.4V, which is a weak-low voltage (closer to 0)
TOPIC: Tabular Method & CMOS Logic Exercise 1
(45 points)
Use the tabular method of Quine-McCluskey to find a minimum cost SOP realization for the function f(x1, …, x4) = Σm(0,4,6,8,9,15) + D(3,7,11,13) Exercise 2
a) Which gate is not a valid CMOS gate?
(5 points)
b) By observing the PUN and PDN of the invalid logic gate, find the functionality of both PUN and PDN. (10 points) c) Regarding the invalid CMOS gate, find three input combinations, under which both PUN and PDN are turned off? (10 points) d) Does the invalid CMOS gate suffer from static power consumption? Explain why? (10 points) Exercise 3 A Berkeley student has designed a CMOS gate as follows:
a) Find an input combination, which results in a static power consumption problem. (5 points) b) For the above input combination find the voltage at the node Y. Note that we have Vdd=2V, and all the NMOS (PMOS) transistors in their ON mode are modeled with a single resistor with the conductance of 2G (G). Is this voltage at node Y a weak-high or a weak-low? (15 points)
McGill University Department of Electrical and Computer Engineering
Course: ECSE 323 -Digital Systems Design Winter 2012 Assignment #2 – Friday Solutions
TOPIC: Tabular Method & CMOS Logic Exercise 1
(Answer) The prime implicants are generated as follows:
The initial prime implicant table is
(45 points)
There are no essential prime implicants. Prime implicant p3 dominates p5 and their costs are the same, so remove p5. Similarly, p7 dominates p6, so remove p6. This gives
Now, p3 and p7 are essential, which leaves
Choosing p2 results in the minimum cost cover
and the function is implemented as
Exercise 2: a) (5 points) Gate#1 is invalid. In CMOS technology, whenever 2 transistors are in parallel in one network, their dual should be in serial in the other network. In gate 1, B and C are in parallel in both PUN and PDN. So, gate 1 is not a valid CMOS gate. b) (10 points) For Gate#1 PUN: A’B’D’+E’C’ PDN: (DE+C(A+B))’=(D’+E’)(C’+A’B’) =E’C’+D’C’+D’A’B’+E’A’B’ not equal to PUN c) (10 points) D=C=0, E=1, AB=01, 10, or 11. Another solution is when E=0, C=1, A=0, B=0, D=1 d) (10 points) No, since there does not exist an input combination under which both PDN and PUN are turned on.
Exercise 3:
a) (5 points) C=1, A=0, B=0 b) (15 points): Y=2*(1/2)/(1/2+2)=0.4V, which is a weak-low voltage (closer to 0)
