A Chaos Based Integrated Jitter Booster Circuit for True Random ...
A Chaos Based Integrated Jitter Booster Circuit for True Random Number Generators ˙Ihsan C¸ic¸ek 1
1,2 ,
Informatics and Information Security Research Center, TUBITAK BILGEM, 41470, Kocaeli, Turkey 2 Department of Electrical and Electronics Engineering Bogazici University, Istanbul, Turkey
Abstract—In this work, we present a chaos based integrated jitter booster circuit for use in multiple oscillator sampling true random number generator architecture. Multiple ring oscillator based true random number generators need significant number of rings for accumulating the intrinsic jitter of inverters to a useful level. Thus, they occupy large silicon area and consume considerable amount of power. The proposed circuit offers an alternative approach for boosting jitter using the chaotic dynamics generated by non-linear coupling of two ring oscillators that require fewer number of components. The simplicity of the proposed circuit offers high integration potential with inherent low area and power consumption advantages. Chaotic dynamics of the circuit was studied using both numerical and circuit simulations. Measurement results of the test chip implemented at 250nm CMOS technology node confirmed chaotic behavior and jitter boosting capability. To the very best of our knowledge this is the first integrated circuit implementation of a chaotic circuit based on digital gates.
I. I NTRODUCTION True Random Number Generators (TRNGs) are widely accepted as the most critical component of a cryptographic system since a deterministic cryptographic primitive cannot produce more entropy at the output than what is available at its inputs [1], [2]. As a result, the unpredictability and the security of the cryptographic system depends heavily on the TRNG, rendering it as the most critical and crucial part of the system. Traditional amplified noise based TRNGs are far from satisfying the throughput requirements of emerging high speed information security applications due to limited bandwidth of the entropy source [3]. Multiple oscillator sampling architecture shown in Fig. 1 was developed to increase the throughput [1]. The simple architecture is composed of a high speed low jitter %50 duty cycle oscillator, and a low speed high jitter oscillator which samples the former using a flip-flop.
Ff
G¨unhan D¨undar2
50%
D Q
Fs
Looking at the literature, it is possible to observe a paradigm shift in the TRNG designs of the last decade. As a consequence of high level sensitivity and variability of parameters determining the randomness performance, pure analog designs are being abandoned. Instead, TRNGs exploiting analog properties of digital components are becoming more popular due to ease of integration with all digitally implemented cryptographic hardware [4]–[8]. Although they offer high integration potential with digital integrated circuits, the injection locking problem [9], weak power supply rejection against interfering signals, and high power consumption make them an inconvenient choice for mobile applications. According to ergodic theory, both continuous time and discrete time chaotic systems can act like entropy sources [10]. Due to the existence of positive Lyapunov exponents when operating in chaotic regime, these systems become highly sensitive and divergent to the changes in the initial conditions. When this feature is united with their aperiodic nature, they can be used as entropy sources in TRNG applications [11], [12]. The aperiodicity of a chaotic signal implies that the signal has no regular temporal zero crossings as in the case of highly jittered oscillations. The idea of using chaos for enhancing jitter can be an alternative to the multiple ring oscillator sampling approach which uses excessive number of circuit elements increasing the area and power consumption of the TRNG system. In this work, we studied a chaotic circuit designed by Hosokawa et. al. which is composed of two non-linearly coupled ring oscillators [14]. While Hosokawa’s circuit is not particularly designed for jitter amplification purpose, based on our experimental observations [13], we propose that the circuit is capable of boosting the jitter and hence, the randomness, when operated in chaotic regime. In Section II, we explore the chaotic behavior of the dynamic system using numerical simulations of the simplified mathematical model of the circuit. In Section III, we briefly explain the design and simulation of the prototype integrated circuit. Section IV presents the measurements of the integrated circuit prototype fabricated in HHNEC’s eFlash 250nm CMOS technology. II. M ODELING OF T HE C HAOTIC R ING O SCILLATOR
Fig. 1.
Multiple oscillator sampling TRNG architecture.
The chaotic ring oscillator circuit presented in Fig. 2(a) was first introduced by Hosokawa et. al. [14]. The circuit composed of two identical and non linearly coupled ring oscillators based on inverters. A capacitor (C1 ) is used for oscillation frequency
control and two resistors (R1 , R2 ) are used for the control of oscillation amplitude as shown in Fig. 2(a). When linear
P3
P2
P1 Va1
Va2
Va3
where R = Ro(n) Ri(n+1) /(Ro(n) + Ri(n+1) ), n = 1, 2, ... in which Ri is the input and Ro is the output resistance, and C = Co(n) + Ci(n+1) , n = 1, 2, ... in which Ci is the input and Co is the output capacitance of a single inverter. The I-V transfer function of the nonlinear element id = f (vd ) can be linearly approximated as: (va3 − vb3 − VD )/rd for va3 − vb3 > VD id =
N3
N2
R1 Va3
D1
D2 Vb3
R2 P5
P4
P6
Vb1 N4
Vb2 N5
Vb3 N6
(a) Chaotic ring oscillator circuit topology.
R
C
R
GmVa2
C
Id
Va2 GmVa1
GmVa3
Va1
C
R
C1
C
R
for va3 − vb3 < −VD
where rd is the small signal resistance and VD is the threshold voltage of the diode. Differential equations defining the dynamics of the system are normalized and numerically solved using 4th order Runge-Kutta method in MATLAB. Normalized phase portrait of the dynamical system is constructed as shown in Fig. 3(a). The bifurcation diagram is calculated as shown in Fig. 3(b) where R/R2 is used as the chaos controlling parameter. It is important to note that this parameter should be selected at the center of the largest continuous bifurcation interval in order to assure chaotic operation under the influence of parameter variations.
Va3
Normalized Phase Portrait
1
D2
0.5
C
R
Id R2
(b) Chaotic ring oscillator circuit model. Fig. 2.
(va3 − vb3 + VD )/rd
(2)
Vb3 GmVb2
R
for |va3 − vb3 | ≤ VD
R1
Vb2 GmVb1
GmVb3
C
0
1.5
D1 Vb1
Vb3 (V)
N1
C1
0
−0.5
Schematic and simplified model of CRO. −1
operation of the inverters is assumed, a simplified model can be derived for theoretical calculations [14]. Parasitic capacitors at the input nodes of the inverters are accepted to be in parallel with the parasitic capacitors at the output nodes of previous inverters which are combined and modeled by a single capacitor C as presented in Fig. 2(b). We can write KCL equations for every circuit node, using a first order linear approximated model for the nonlinear element formed by anti parallel connection of two diodes which yields the following equations: dva1 dt dva2 dt dva3 dt dvb1 dt dvb2 dt dvb3 dt
= = = = = =
1 Gm va1 − va3 RC C 1 Gm − va2 − va1 RC C (R + R1 ) Gm id − va3 − va2 − (1) (C + C1 )RR1 C + C1 C + C1 1 Gm − vb1 − vb3 RC C 1 Gm − vb2 − vb1 RC C (R + R2 ) Gm id − vb3 − vb2 − RR2 C C C
−1.5 −1.5
−1
−0.5
0
0.5
1
1.5
Va3 (V)
(a) Normalized phase portrait of the dynamic system.
−
(b) Bifurcation diagram of the dynamic system. Fig. 3.
Chaotic behavior characterization of the dynamic system.
According to the bifurcation diagram shown in Fig. 3(b) the circuit exhibits chaotic behavior with respect to a wide range of chaos controlling parameter values which guarantee robust chaotic operation against circuit parameter variations. III. D ESIGN OF T HE CRO BASED J ITTER B OOSTER Theoretical analysis and numerical simulations provided an insight about the boundaries of chaotic behavior. To have a better understanding of circuit operation on silicon we used HSPICE to simulate the chaotic ring oscillator using HHNEC’s 250nm transistor models with the following parameters: WN /LN = 20 µm/1 µm, WP /LP = 60 µm/1 µm, C1 = 3 pF , R1 = 10 kΩ, R2 = 2.5 kΩ. Phase portrait of the simulated circuit is shown in Fig. 4. HSPICE simulation result shown in Fig. 4, presents the phase portrait of the designed circuit and confirms the chaotic operation.
Fig. 5.
Die photograph of the CRO implementation.
and varied while R1 is kept constant to scan the region where the circuit exhibits chaotic behavior.
Fig. 4.
HSPICE simulation results showing the phase portrait.
We measured the phase portrait of the chaotic ring oscillator using the custom designed test fixture board and verified the chaotic mode of operation by the phase portrait measurements. Phase portrait measurements presented in Fig. 7 are in good agreement with simulation results shown in Fig. 3(a) and Fig. 4. In 250nm technology, jitter to period ratio for a ring oscillator is typically less than 10−4 . In the chaotic regime, jitter generated by the circuit is measured to be approx. 1.4 ns, corresponding to a jitter to period ratio of 30% exceeding the minimum requirement of 10% [15]. Jitter measurements are done according to the method described in [16]. Measurement results show that proposed circuit operating in chaotic regime can be used as a jitter booster. It is important to note that chaotic mode of operation increases the variance of the jitter without changing the underlying Gaussian characteristic as indicated by the histogram in Fig. 8.
The dynamic system shown in Fig. 2(a) is implemented on a test chip using 250nm CMOS technology provided by HHNEC. Seven stage ring oscillators are used in the design of the jitter booster. Diode connected MOSFETs are employed to implement the non-linear function generator formed by anti parallel connection of D1 and D2 . In order to have the full control of the prototype R1 , R2 , and C are externally connected. The jitter booster circuit presented in Fig. 5 occupies 108µm x 204µm area on silicon. We used multiple wide guard rings around the implementation to protect the CRO against coupling of external disturbances generated by other deterministic digital circuits fabricated on the same die. IV. M EASUREMENT R ESULTS A test fixture board shown in Fig. 6 is designed for evaluation. The board is powered by 5V and an on board regulator supplies 2.5V to the chip. Externally connected variable resistor R2 is used as the chaos controlling parameter
Fig. 6.
Test fixture of the prototype chip.
circuit when operated in the chaotic regime. Proposed circuit is capable of generating chaotic signals with jitter to period ratio in the excess of 30% up to 200 MHz. The simplicity of the chaotic ring oscillator circuit offers low power and high speed advantages in a compact footprint of 108µm x 204µm. To the very best of our knowledge this is the first integrated circuit implementation of a chaotic circuit based on digital gates. As a future work, we are planning to design a full featured multiple oscillator based true random number generator that employs a chaotic ring oscillator with all integrated components and evaluate its randomness performance. R EFERENCES
Fig. 7.
Measurement results showing the phase portrait.
Fig. 8.
Measurement results showing the boosted jitter.
V. C ONCLUSION In this study, we propose a hardware efficient jitter booster using two nonlinearly coupled ring oscillators operating in the chaotic regime that can increase the jitter level without requiring large number of components. Boundaries of chaotic operation are explored through numerical simulations of the simplifed mathematical model of the circuit. In addition, chaotic operation of the designed circuit is verified with HSPICE simulations using 250nm CMOS technology models. A prototype chip is fabricated using 250nm eFlash process of HHNEC. We observed the jitter boosting capability of the
[1] B. Jun and P. Kocher, “The intel random number generator,” Cryptography Research, Inc. white paper prepared for Inter Corp., Apr. 1999. [2] H. Bock, M. Bucci, and R. Luzzi, “An offset-compensated oscillatorbased random bit source for security applications,” in Cryptographic Hardware and Embedded Systems - CHES 2004, vol. 3156, pp. 27–83, Springer Berlin / Heidelberg, 2004 [3] C. Petrie and J. Connelly, “A noise-based ic random number generator for applications in cryptography,” Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on, vol. 47, no. 5, pp. 615– 621, May 2000. [4] B. Sunar, W. J. Martin, and D. R. Stinson, “A provably secure true random number generator with built-in tolerance to active attacks,” IEEE Trans. Comput., vol. 56, no. 1, pp. 109–119, 2007. [5] S.-K. Yoo, D. Karakoyunlu, B. Birand, and B. Sunar, “Improving the Robustness of Ring Oscillator TRNGs,” ACM Transactions on Reconfigurable Technology and Systems, vol. 3, no. 2, pp. 130, May 2010. [6] J. P. Murphy, “Field-programmable true random number generator,” Electronics Letters, vol.48, no.10, pp.565–566, May 10 2012. [7] K. Wold and C. H. Tan, “Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings,”International Journal of Reconfigurable Computing, pp. 18, June 2009. [8] M. Jessa and M. Jaworski “Enhancing the Randomness of a Combined True Random Number Generator Based on the Ring Oscillator Sampling Method,” Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (RECONFIG ’11),IEEE Computer Society, Washington, DC, USA, pp.274–279, 2011. [9] Markettos, A.T., Moore, S.W. “The Frequency Injection Attack on RingOscillator-Based True Random Number Generators.” In: Clavier, C., Gaj, K. (eds.) CHES 2009. LNCS, vol. 5747, pp. 317–331. Springer, Heidelberg (2009). [10] J. P. Eckmann and D. Ruelle, “Ergodic theory of chaos and strange attractors”, Reviews of Modern Physics, 57 (3, part 1): pp. 617–656, 1985. [11] M.E. Yalcin, J. A. K. Suykens and J. Vandewalle, “True random bit generation from a double-scroll attractor,” IEEE Transactions on Circuits and Systems I, vol. 51, no. 7, pp. 1395–1404, 2004. [12] Stojanovski, T. and Kocarev, L.“Chaos-Based Random Number Generators-Part I: Analysis,” IEEE Trans. Circuits and Systems I: Fundamental Theory and Applications, Vol. 48(3), pp. 281–288, Mar 2001. [13] I. Cicek, G. Dundar,“A hardware efficient chaotic ring oscillator based true random number generator,” 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS), vol., no., pp.430–433, 11-14 Dec. 2011 [14] Y. Hosokawa, Y. Nishio and A. Ushida, “Chaotic Circuit Using Two Simple Ring Oscillators Coupled by Diodes,” Proceedings of International Symposium on Nonlinear Theory and its Applications (NOLTA’99), vol. 1, pp. 107–110, Nov. 1999. [15] M. Bucci, L. Germani, R. Luzzi, A. Trifiletti, and M. Varanonuovo, “A high-speed oscillator-based truly random number source for cryptographic applications on a smart card ic,” vol. 52, no. 4, pp. 403–409, 2003. [16] Tektronix, “Understanding and characterizing timing jitter,”,Sep. 2002.
1,2 ,
Informatics and Information Security Research Center, TUBITAK BILGEM, 41470, Kocaeli, Turkey 2 Department of Electrical and Electronics Engineering Bogazici University, Istanbul, Turkey
Abstract—In this work, we present a chaos based integrated jitter booster circuit for use in multiple oscillator sampling true random number generator architecture. Multiple ring oscillator based true random number generators need significant number of rings for accumulating the intrinsic jitter of inverters to a useful level. Thus, they occupy large silicon area and consume considerable amount of power. The proposed circuit offers an alternative approach for boosting jitter using the chaotic dynamics generated by non-linear coupling of two ring oscillators that require fewer number of components. The simplicity of the proposed circuit offers high integration potential with inherent low area and power consumption advantages. Chaotic dynamics of the circuit was studied using both numerical and circuit simulations. Measurement results of the test chip implemented at 250nm CMOS technology node confirmed chaotic behavior and jitter boosting capability. To the very best of our knowledge this is the first integrated circuit implementation of a chaotic circuit based on digital gates.
I. I NTRODUCTION True Random Number Generators (TRNGs) are widely accepted as the most critical component of a cryptographic system since a deterministic cryptographic primitive cannot produce more entropy at the output than what is available at its inputs [1], [2]. As a result, the unpredictability and the security of the cryptographic system depends heavily on the TRNG, rendering it as the most critical and crucial part of the system. Traditional amplified noise based TRNGs are far from satisfying the throughput requirements of emerging high speed information security applications due to limited bandwidth of the entropy source [3]. Multiple oscillator sampling architecture shown in Fig. 1 was developed to increase the throughput [1]. The simple architecture is composed of a high speed low jitter %50 duty cycle oscillator, and a low speed high jitter oscillator which samples the former using a flip-flop.
Ff
G¨unhan D¨undar2
50%
D Q
Fs
Looking at the literature, it is possible to observe a paradigm shift in the TRNG designs of the last decade. As a consequence of high level sensitivity and variability of parameters determining the randomness performance, pure analog designs are being abandoned. Instead, TRNGs exploiting analog properties of digital components are becoming more popular due to ease of integration with all digitally implemented cryptographic hardware [4]–[8]. Although they offer high integration potential with digital integrated circuits, the injection locking problem [9], weak power supply rejection against interfering signals, and high power consumption make them an inconvenient choice for mobile applications. According to ergodic theory, both continuous time and discrete time chaotic systems can act like entropy sources [10]. Due to the existence of positive Lyapunov exponents when operating in chaotic regime, these systems become highly sensitive and divergent to the changes in the initial conditions. When this feature is united with their aperiodic nature, they can be used as entropy sources in TRNG applications [11], [12]. The aperiodicity of a chaotic signal implies that the signal has no regular temporal zero crossings as in the case of highly jittered oscillations. The idea of using chaos for enhancing jitter can be an alternative to the multiple ring oscillator sampling approach which uses excessive number of circuit elements increasing the area and power consumption of the TRNG system. In this work, we studied a chaotic circuit designed by Hosokawa et. al. which is composed of two non-linearly coupled ring oscillators [14]. While Hosokawa’s circuit is not particularly designed for jitter amplification purpose, based on our experimental observations [13], we propose that the circuit is capable of boosting the jitter and hence, the randomness, when operated in chaotic regime. In Section II, we explore the chaotic behavior of the dynamic system using numerical simulations of the simplified mathematical model of the circuit. In Section III, we briefly explain the design and simulation of the prototype integrated circuit. Section IV presents the measurements of the integrated circuit prototype fabricated in HHNEC’s eFlash 250nm CMOS technology. II. M ODELING OF T HE C HAOTIC R ING O SCILLATOR
Fig. 1.
Multiple oscillator sampling TRNG architecture.
The chaotic ring oscillator circuit presented in Fig. 2(a) was first introduced by Hosokawa et. al. [14]. The circuit composed of two identical and non linearly coupled ring oscillators based on inverters. A capacitor (C1 ) is used for oscillation frequency
control and two resistors (R1 , R2 ) are used for the control of oscillation amplitude as shown in Fig. 2(a). When linear
P3
P2
P1 Va1
Va2
Va3
where R = Ro(n) Ri(n+1) /(Ro(n) + Ri(n+1) ), n = 1, 2, ... in which Ri is the input and Ro is the output resistance, and C = Co(n) + Ci(n+1) , n = 1, 2, ... in which Ci is the input and Co is the output capacitance of a single inverter. The I-V transfer function of the nonlinear element id = f (vd ) can be linearly approximated as: (va3 − vb3 − VD )/rd for va3 − vb3 > VD id =
N3
N2
R1 Va3
D1
D2 Vb3
R2 P5
P4
P6
Vb1 N4
Vb2 N5
Vb3 N6
(a) Chaotic ring oscillator circuit topology.
R
C
R
GmVa2
C
Id
Va2 GmVa1
GmVa3
Va1
C
R
C1
C
R
for va3 − vb3 < −VD
where rd is the small signal resistance and VD is the threshold voltage of the diode. Differential equations defining the dynamics of the system are normalized and numerically solved using 4th order Runge-Kutta method in MATLAB. Normalized phase portrait of the dynamical system is constructed as shown in Fig. 3(a). The bifurcation diagram is calculated as shown in Fig. 3(b) where R/R2 is used as the chaos controlling parameter. It is important to note that this parameter should be selected at the center of the largest continuous bifurcation interval in order to assure chaotic operation under the influence of parameter variations.
Va3
Normalized Phase Portrait
1
D2
0.5
C
R
Id R2
(b) Chaotic ring oscillator circuit model. Fig. 2.
(va3 − vb3 + VD )/rd
(2)
Vb3 GmVb2
R
for |va3 − vb3 | ≤ VD
R1
Vb2 GmVb1
GmVb3
C
0
1.5
D1 Vb1
Vb3 (V)
N1
C1
0
−0.5
Schematic and simplified model of CRO. −1
operation of the inverters is assumed, a simplified model can be derived for theoretical calculations [14]. Parasitic capacitors at the input nodes of the inverters are accepted to be in parallel with the parasitic capacitors at the output nodes of previous inverters which are combined and modeled by a single capacitor C as presented in Fig. 2(b). We can write KCL equations for every circuit node, using a first order linear approximated model for the nonlinear element formed by anti parallel connection of two diodes which yields the following equations: dva1 dt dva2 dt dva3 dt dvb1 dt dvb2 dt dvb3 dt
= = = = = =
1 Gm va1 − va3 RC C 1 Gm − va2 − va1 RC C (R + R1 ) Gm id − va3 − va2 − (1) (C + C1 )RR1 C + C1 C + C1 1 Gm − vb1 − vb3 RC C 1 Gm − vb2 − vb1 RC C (R + R2 ) Gm id − vb3 − vb2 − RR2 C C C
−1.5 −1.5
−1
−0.5
0
0.5
1
1.5
Va3 (V)
(a) Normalized phase portrait of the dynamic system.
−
(b) Bifurcation diagram of the dynamic system. Fig. 3.
Chaotic behavior characterization of the dynamic system.
According to the bifurcation diagram shown in Fig. 3(b) the circuit exhibits chaotic behavior with respect to a wide range of chaos controlling parameter values which guarantee robust chaotic operation against circuit parameter variations. III. D ESIGN OF T HE CRO BASED J ITTER B OOSTER Theoretical analysis and numerical simulations provided an insight about the boundaries of chaotic behavior. To have a better understanding of circuit operation on silicon we used HSPICE to simulate the chaotic ring oscillator using HHNEC’s 250nm transistor models with the following parameters: WN /LN = 20 µm/1 µm, WP /LP = 60 µm/1 µm, C1 = 3 pF , R1 = 10 kΩ, R2 = 2.5 kΩ. Phase portrait of the simulated circuit is shown in Fig. 4. HSPICE simulation result shown in Fig. 4, presents the phase portrait of the designed circuit and confirms the chaotic operation.
Fig. 5.
Die photograph of the CRO implementation.
and varied while R1 is kept constant to scan the region where the circuit exhibits chaotic behavior.
Fig. 4.
HSPICE simulation results showing the phase portrait.
We measured the phase portrait of the chaotic ring oscillator using the custom designed test fixture board and verified the chaotic mode of operation by the phase portrait measurements. Phase portrait measurements presented in Fig. 7 are in good agreement with simulation results shown in Fig. 3(a) and Fig. 4. In 250nm technology, jitter to period ratio for a ring oscillator is typically less than 10−4 . In the chaotic regime, jitter generated by the circuit is measured to be approx. 1.4 ns, corresponding to a jitter to period ratio of 30% exceeding the minimum requirement of 10% [15]. Jitter measurements are done according to the method described in [16]. Measurement results show that proposed circuit operating in chaotic regime can be used as a jitter booster. It is important to note that chaotic mode of operation increases the variance of the jitter without changing the underlying Gaussian characteristic as indicated by the histogram in Fig. 8.
The dynamic system shown in Fig. 2(a) is implemented on a test chip using 250nm CMOS technology provided by HHNEC. Seven stage ring oscillators are used in the design of the jitter booster. Diode connected MOSFETs are employed to implement the non-linear function generator formed by anti parallel connection of D1 and D2 . In order to have the full control of the prototype R1 , R2 , and C are externally connected. The jitter booster circuit presented in Fig. 5 occupies 108µm x 204µm area on silicon. We used multiple wide guard rings around the implementation to protect the CRO against coupling of external disturbances generated by other deterministic digital circuits fabricated on the same die. IV. M EASUREMENT R ESULTS A test fixture board shown in Fig. 6 is designed for evaluation. The board is powered by 5V and an on board regulator supplies 2.5V to the chip. Externally connected variable resistor R2 is used as the chaos controlling parameter
Fig. 6.
Test fixture of the prototype chip.
circuit when operated in the chaotic regime. Proposed circuit is capable of generating chaotic signals with jitter to period ratio in the excess of 30% up to 200 MHz. The simplicity of the chaotic ring oscillator circuit offers low power and high speed advantages in a compact footprint of 108µm x 204µm. To the very best of our knowledge this is the first integrated circuit implementation of a chaotic circuit based on digital gates. As a future work, we are planning to design a full featured multiple oscillator based true random number generator that employs a chaotic ring oscillator with all integrated components and evaluate its randomness performance. R EFERENCES
Fig. 7.
Measurement results showing the phase portrait.
Fig. 8.
Measurement results showing the boosted jitter.
V. C ONCLUSION In this study, we propose a hardware efficient jitter booster using two nonlinearly coupled ring oscillators operating in the chaotic regime that can increase the jitter level without requiring large number of components. Boundaries of chaotic operation are explored through numerical simulations of the simplifed mathematical model of the circuit. In addition, chaotic operation of the designed circuit is verified with HSPICE simulations using 250nm CMOS technology models. A prototype chip is fabricated using 250nm eFlash process of HHNEC. We observed the jitter boosting capability of the
[1] B. Jun and P. Kocher, “The intel random number generator,” Cryptography Research, Inc. white paper prepared for Inter Corp., Apr. 1999. [2] H. Bock, M. Bucci, and R. Luzzi, “An offset-compensated oscillatorbased random bit source for security applications,” in Cryptographic Hardware and Embedded Systems - CHES 2004, vol. 3156, pp. 27–83, Springer Berlin / Heidelberg, 2004 [3] C. Petrie and J. Connelly, “A noise-based ic random number generator for applications in cryptography,” Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on, vol. 47, no. 5, pp. 615– 621, May 2000. [4] B. Sunar, W. J. Martin, and D. R. Stinson, “A provably secure true random number generator with built-in tolerance to active attacks,” IEEE Trans. Comput., vol. 56, no. 1, pp. 109–119, 2007. [5] S.-K. Yoo, D. Karakoyunlu, B. Birand, and B. Sunar, “Improving the Robustness of Ring Oscillator TRNGs,” ACM Transactions on Reconfigurable Technology and Systems, vol. 3, no. 2, pp. 130, May 2010. [6] J. P. Murphy, “Field-programmable true random number generator,” Electronics Letters, vol.48, no.10, pp.565–566, May 10 2012. [7] K. Wold and C. H. Tan, “Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings,”International Journal of Reconfigurable Computing, pp. 18, June 2009. [8] M. Jessa and M. Jaworski “Enhancing the Randomness of a Combined True Random Number Generator Based on the Ring Oscillator Sampling Method,” Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (RECONFIG ’11),IEEE Computer Society, Washington, DC, USA, pp.274–279, 2011. [9] Markettos, A.T., Moore, S.W. “The Frequency Injection Attack on RingOscillator-Based True Random Number Generators.” In: Clavier, C., Gaj, K. (eds.) CHES 2009. LNCS, vol. 5747, pp. 317–331. Springer, Heidelberg (2009). [10] J. P. Eckmann and D. Ruelle, “Ergodic theory of chaos and strange attractors”, Reviews of Modern Physics, 57 (3, part 1): pp. 617–656, 1985. [11] M.E. Yalcin, J. A. K. Suykens and J. Vandewalle, “True random bit generation from a double-scroll attractor,” IEEE Transactions on Circuits and Systems I, vol. 51, no. 7, pp. 1395–1404, 2004. [12] Stojanovski, T. and Kocarev, L.“Chaos-Based Random Number Generators-Part I: Analysis,” IEEE Trans. Circuits and Systems I: Fundamental Theory and Applications, Vol. 48(3), pp. 281–288, Mar 2001. [13] I. Cicek, G. Dundar,“A hardware efficient chaotic ring oscillator based true random number generator,” 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS), vol., no., pp.430–433, 11-14 Dec. 2011 [14] Y. Hosokawa, Y. Nishio and A. Ushida, “Chaotic Circuit Using Two Simple Ring Oscillators Coupled by Diodes,” Proceedings of International Symposium on Nonlinear Theory and its Applications (NOLTA’99), vol. 1, pp. 107–110, Nov. 1999. [15] M. Bucci, L. Germani, R. Luzzi, A. Trifiletti, and M. Varanonuovo, “A high-speed oscillator-based truly random number source for cryptographic applications on a smart card ic,” vol. 52, no. 4, pp. 403–409, 2003. [16] Tektronix, “Understanding and characterizing timing jitter,”,Sep. 2002.
