A Low Power 3.1-7.5 GHz Tunable Pulse Generator for Impulse Radio ...
A Low Power 3.1-7.5 GHz Tunable Pulse Generator for Impulse Radio UWB J.B. Radic*, A.M. Djugova*, L.F. Nagy* and M.S. Videnovic-Misic* *Faculty
of Technical Sciences, University of Novi Sad/Department for Power, Electronics and Communications Engineering, Novi Sad, Serbia [email protected], [email protected], [email protected],[email protected]
Abstract—A novel energy-efficient tunable impulse radio ultra wide band (IR-UWB) pulse generator (PG) for the high data rate 3.1 − 7.5 GHz band applications is proposed. Glitch generator, switched ring oscillator, buffer and pulse shaping filter are the key components. The circuit is scalable both in bandwidth and center frequency. The glitch
generator combines falling edge of the input signal and its delayed inverse, allowing the impulse duration to be tuned over a wide range (250 – 660 ps) by varying the delay between the edges. The generated impulse duration approximately defines the PG’s signal width and thus its spectrum bandwidth. The ring oscillator frequency, which determines the spectrum center frequency, is controlled by the gate control voltage of the PMOS transistor used as an inverter feedback in the ring oscillator. Post-layout simulations show the pulse amplitude of 261 mV and the pulse duration around 700 ps. The total power consumption is only 697 μW with a supply voltage of 1.8 V. The PG is designed in UMC 0.18μm CMOS technology with the total
chip area of 602×587 μm2.
I. INTRODUCTION Since the Federal Communications Commission (FCC) allocated the 3.1 − 10.6 GHz unlicensed spectrum for commercial ultra wideband (UWB) application in February 2002, several technologies have been developed to satisfy the communication market requirements [1]. Carrier-less Impulse Radio Ultra Wide Band (IR-UWB) approach, with extremely short duration pulses (less than 1 ns) transmission, has draw much attention from both academic and industrial circles. It potentially offers several advantages, including high data rates, low cost, low power and complexity (without mixer and power amplifier), reduced multipath fading, high time and range resolution, and low probability of undesired detection and interception [2 − 4]. The IR-UWB appears to be a good candidate for high data rate short-range and low data rate wireless communication and biomedical applications such as wireless personal area networks (WPAN) [5 − 8], interchip communications [9, 10], and UWB biotelemetry [11, 12]. A pulse generator plays the key role in an IR-UWB system design because it produces pulse train which spectrum, with sufficient power level, has to satisfy all FCC requirements. Therefore, it is extremely challenging to design UWB transmitter that complies with the FCC This work was supported in part by the Ministry of Education and Science, Republic of Serbia, on the project no. TR-32016, and by FP7 project no. 256615.
demands while achieving wide bandwidth, low power and low complexity. The pulse generator should also be tunable to provide compensation due to process, voltage and temperature variations (PVT), and changes in the communication channel or antenna performances. In this paper, a new low power and low complexity tunable pulse generator, covering the 3.1 − 7.5 GHz spectrum band, is proposed. The presented topology designed in UMC 0.18μm CMOS technology is analyzed in Section III. Post-layout simulation results are given in Section IV followed by discussion and comparison with the other published pulse generator designs. The Section V concludes the paper. II. FCC SPECTRAL MASK AND REGULATIONS According to the FCC, an UWB system is allowed to transmit information in the 3.1 − 10.6 GHz for all types of communications. To prevent interference with the already existing communication systems such as WiMax, Bluetooth and GSM, the maximum average power level of the UWB transmitter is limited to −41.3 dBm/MHz with a maximum peak power level of 0 dBm/50 MHz [1]. In the GPS band (0.96 – 1.61 GHz), there is even more stringent regulation: less than −75.3 dBm/MHz is needed to avoid interference problems. The Power Spectral Density (PSD) in frequency interval from 1.61 GHz to 3.1 GHz depends on the type of application (indoor, outdoor, GPS, wall & medical imaging, through-wall imaging & surveillance system). Fig. 1 shows the FCC mask and regulations for the indoor and outdoor UWB communications (including Part 15 limit) [1] that pulse spectrum has to comply. Due to many reported interferences with wireless local area network (WLAN) systems operating in the 5 – 6 GHz
Figure 1. FCC indoor and outdoor spectral mask for UWB applications [1].
band, the UWB band is usually subdivided into two bands: 3 − 5 GHz (lower-band) and 6 − 10.6 GHz (higher-band). Although the higher-band operation offers advantages like wider bandwidth, higher data rate, and immunity from interference with WiMax, the lower UWB band is much more explored due to its less complex system implementation. Furthermore, circuit consumption is reduced because of the technology employed and antenna complexity is decreased by using the band below 5 GHz. The FCC rules define only the frequency bands and the radiated power spectral density (PSD) but there are no requirements on the time-domain shapes. However, as the shape of the pulse generator signal determines its spectrum characteristic and effectively dictates specific system (UWB transmitter) requirements, its generation is one of the essential considerations in the UWB design. Pulse shapes usually used in the impulse radio technology are based on the Gaussian pulse and its derivatives. For indoor systems, the 5th or higher order derivative of the Gaussian pulse should be used to comply with the allocated indoor spectrum mask [13]. III. PROPOSED PULSE GENERATOR ARCHITECTURE The proposed topology is shown in Fig. 2. It is composed of a glitch generator, a switched oscillator, a two-stage buffer, and a pulse shaping filter. The switched oscillator consists of a three-stage ring oscillator, (inverter stages M1 – M3), two feedback resistors Rosc, a control transistor M6, and a pair of oscillation-enabling switches (transistors M4 and M5). The ring oscillator is one of the most commonly used topologies in the pulse generator design due to its simple architecture occupying small chip area. Furthermore, it offers fast transient response as it has short start-up time and small resistance at each inverter feedback nod. Advantages mentioned above are the most important requirements for low power and high date rate UWB applications. The resistors Rosc, feedbacks in the second and third inverter stage, increase the ring oscillating frequency by decreasing the input (Miller) capacitance [14]. PMOS transistor M6 is used for the frequency tuning to enable compensation due to the process-voltage-temperature (PVT) variations and additional spectrum fitting within the FCC spectral mask [12]. This can be accomplished by changing the transistor M6 gate control voltage Vctrl. The oscillation-enabling switches control the oscillation process based on the on-off signal. The ring oscillator is
turned on by transistor M4 at the on-off signal high level. The inverter stages output voltage values are determined by the size ratio of the corresponding PMOS and NMOS transistors. During the control signal low level, the transistor M4 is switched off, and no signal is generated at the oscillator output (the output voltage is close to Vdd). Since the ring oscillator and the buffer stage are switched off during the inactive period, the power consumption is minimized. Furthermore, transistor M5 connects the M1 transistor output (the M2 transistor input) to Vdd, and thus provides the oscillation start from the initial state at the rising edge of the on-off signal. As the ring oscillator is switched on/off in accordance with the on-off signal state, the control signal duration defines approximately the length of the pulse generator signal and thus its bandwidth. The shorter the on-off signal, the wider the output signal bandwidth is obtained. To provide signal covering frequency range in the order of several GHz, the control signal should be sharp and narrow (duration less than 1 ns). Moreover, it is very desirable to enable tuning of the oscillation-enabling pulse duration to allow additional spectrum fitting within the FCC spectral mask and compensation due to process variations and changes in communication system. A sub-nanosecond control pulse is made by the glitch generator driven by the input trigger in signal (controlled by a microcontroller). The glitch generator consists of three inverters, a digitally controlled capacitor bank and a NOR gate. The main block in the circuit is the CMOS NOR gate fed by the input signal and its delayed inverse. As the gate output is high only if both inputs are low, the short pulse is created at the falling edge of the in signal. The generated signal duration is determined by the period when the both gate inputs are low or the delay of the inverted signal. This time interval is specified by the propagation delay through inverter and the capacitance of the digitally controlled capacitor bank. The capacitance bank is composed of capacitors Cb1 and Cb2, and transistor switches M11 and M12. To provide steep rising and falling edge of the control signal for a high out-of-band rejection, the capacitor bank is introduced between the inverter stages. Digital signals D1, and D2 switch off/on adequate capacitors and thus determine the total bank capacitance directly proportional to the on-off signal duration. This allows the delay and the pulse duration to be varied by changing the digital control signals. With the bank capacitance digital tuning, the pulse can have duration approximately ranging from 250 ps to 660 ps. The two-stage buffer isolates the ring oscillator from the pulse shaping filter loading and improves the pulse
Figure 2. Proposed IR-UWB pulse generator.
generator current driving capability. The high-pass filter composed of the inductor L and two capacitors C1 and C2 additionally accommodates the pulse in the allowed FCC spectral mask. IV.
POST-LAYOUT SIMULATION RESULTS AND COMPARISON
The proposed topology was designed in mixed mode/RF UMC 0.18μm CMOS technology with supply voltage of 1.8 V. Simulations were performed using SpectreRF Simulator from Cadence Design System. Since one of the portable system’s biggest issues is battery life, the pulse generator was optimized with the main aim to minimize the power consumption. Additionally, the signal spectrum should meet efficiently the FCC spectrum demands and cover the lower UWB bandwidth, while still keeping acceptable values for remaining Figures of Merits (FOMs). Regarding the circuit’s spectrum characteristics or the spectrum center frequency, the main problem was limited set of transistor sizes available in the used technology as the ring oscillator frequency depends directly on transistors sizes. With the increase in transistors sizes the oscillation period T rises while the oscillating frequency decreases (f0=1/T) proportionally. For the standard three-stage ring oscillator design (without any feedback) with the smallest NMOS transistors (W/L=25μm/0.18μm) and approximately two times larger PMOS transistors (W/L=45μm/0.18μm), the oscillation frequency of 3.77 GHz was obtained. It should be noted that the PMOS transistor are usually made larger than NMOS transistor in inverter topology to compensate for the lower carrier mobility of holes and set VTH closer to Vdd/2. Although the obtained f0 value is close to the center of the lower UWB bandwidth, it is not high enough as effects that deteriorate this parameter, such as the fabrication process and the PVT variations, are not taken into account. It should be mentioned that higher oscillation frequency could be achieved without PMOS transistor M5. However, this transistor enables the oscillation start from the same initial state. To increase the ring oscillator frequency, the resistive feedback was used in the second and third inverter stage. PMOS transistor M6 was introduced as the first inverter feedback and means of the f0 control. Further increase in the frequency could be achieved with resistive feedback in the first buffer stage.
Nevertheless, this method would noticeably increase the power consumption. The photography of the pulse generator layout is shown in Fig. 3. The integrated circuit (IC) occupies a die area of 602 × 587 μm2 including bonding pads. It supports the on-off keying (OOK) modulation. This type of the modulation is chosen because of its simplicity and thus the less complex transmitter realization. The post-layout simulation results in time and spectrum domain for the generated UWB pulse are given in Figs. 4 and 5. The pulse duration is around 0.7 ns and the peak-to-peak amplitude Vpp on a 50 Ω output load is 261 mV. Signal Power Spectral Density occupies the spectrum range from 3.1 GHz to 7.5 GHz with more than 20 dB of side-lobe rejection, and fully meet the FCC spectral mask except in the frequency range around 1 GHz. The PSD has maximum value of -44.2 dBm/MHz at 4.7 GHz. This peak value could be increased to the FCC maximum allowed value by choosing the appropriate value of the transistor M6 gate control voltage Vctrl and combination of digital signals D1 and D2. But in that case the signal bandwidth would be decreased. The pulse generator operates in burst mode with low duty cycle and pulse repetition frequency (PRF) of 100 MHz, and thus consumes very little power. The average power consumption, including the glitch generator, the buffer stages and the filter, is only 698 μW, corresponding to 6.98 pJ energy consumption per pulse (for the PRF of 100 MHz). In general, the nature of the IR-UWB communication allows saving power between each pulses and consuming energy only during the pulse generation. Table 1 summarizes the performance of the proposed
Figure 4.
Figure 3. Proposed IR-UWB pulse generator layout.
Pulse generator output waveform.
Figure 5. Pulse generator output in spectrum domain.
TABLE I.
SIMULATIONS RESULTS SUMARY AND COMPARISON WITH REPORTED PULSE
[3]
GENERATORS
Reference
This work
Ref [16]
Ref [17]
Ref [18]
Power cons. [mW]
0.698
55
2.5
3.8
BW (-10 dB) [GHz]
3.1 − 7.5
3.1 − 5.1
3.0 − 7.0
3.3 − 6.3
Amplitude (Vpp) [mV]
261
80
1000
150
700
1000
600
500-900
0.35
N/A
0.02*
0.44
100
N/A
1000
525 – 910
IHP 0.25μm BiCMOS
0.35μm CMOS
0.13μm CMOS
Pulse length [pS] Die area [mm2] PRF [MHz]
[5]
[6]
[7]
[8]
UMC 0.18μm CMOS * the core (active) area only Technology
[4]
IR-UWB pulse generator compared to the FOMs of the recently published works. Although, it can be difficult to make fair comparisons when different specifications and technologies are used, it is clear that the proposed circuit has by far the lowest power consumption and the peak-topeak amplitude higher than in Refs [16], [18]. The chip area is reduced compared to Ref [18], while the core (active area) is only given in Ref [17]. Other Figures of Merits are comparable to the results given by the authors. The proposed architecture is suitable for low voltage and ultra-low power UWB wireless applications covering the 3.1 GHz to 7.5 GHz frequency range. V. CONCLUSION A new energy-efficient tunable pulse generator has been designed in UMC 0.18µm CMOS technology for high data rate 3.1 – 7.5 UWB applications. The spectrum and time domain signal adjustment is provided with the adequate PMOS gate control voltage and by tuning capacitance of the digitally controlled capacitor bank. This allows the control pulse duration to be varied over a wide range (250 − 660 ps). The post-layout simulation results of the proposed ring oscillator-based architecture demonstrate very low average power consumption (less than 698 μW at 100 MHz pulse repetition rate), high peak-to-peak amplitude and small chip area (602×587 μm2 including bonding pads).
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
REFERENCES [1]
[2]
First Report and Order: Revision of Part 15 of the Commission’s Rules Regarding Ultra-Wideband Transmission Systems Federal Communications Commission (FCC), ET Docket 98-153, Adopted February 14, 2002, Released Apr. 22, 2002. J. R. Fernandes and D. Wentzloff, “Recent Andvances in IR-UWB Transceivers: An Overview,” in Proceedings of the IEEE
[18]
International Symposium on Circuits and Systems, Paris, May 30 – June 2 2010, pp. 3284−3287. M. Ghavami, L. B. Michael, and R. Kohno, Ultra Wideband Signals and Systems in Communications Engineering, John Wiley&Sons Ltd, 2004. K. Siwiak and D. McKeown, Ultra-Wideband Radio Technology, John Wiley&Sons Ltd, 2004. A. Medi, W. Namgoong, “A high data-rate energy-efficient interference-tolerant fully integrated CMOS frequency channelized UWB transceiver for impulse radio,” IEEE Journal of Solid-State Circuits, vol. 43, no 4, pp. 974–980, April 2008. M. Demirkan, R. Spencer, “A pulse-based ultra-wideband transmitter in 90-nm CMOS for WPANs,” IEEE Journal of SolidState Circuits, vol. 43, no 12, pp. 2820–2828, Dec. 2008. J. Hu, Y. Zhu, S. Wang, H. Wu, “Energy efficient, reconfigurable, distributed pulse generation and detection in UWB impulse radios,” in Proceedings of the IEEE International Conference on Ultra-Wideband, Vancouver, BC, 9 – 11 Sept. 2009, pp. 773–777. V. Kulkarni, M. Muqsith, K. Niitsu, H. Ishikuro, T. Kuroda, “A 750Mb/s, 12pJ/b, 6-to-10GHz CMOS IR-UWB transmitter with embedded on-chip antenna,” IEEE Journal of Solid-State Circuits, vol. 44, no. 2, pp. 394–403, Feb. 2009. Y. Zheng, Y. Zhang, Y. Tong, “A novel wireless interconnect technology using impulse radio for interchip communications,” IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 4, pp. 1912–1920, June 2006. N. Sasaki, K. Kimoto, W. Moriyama, T. Kikkawa, “A single-chip ultra-wideband receiver with silicon integrated antennas for interchip wireless interconnection,” IEEE Journal of Solid-State Circuits, vol. 44, no. 2, pp. 382–393, Feb. 2009. M.S. Chae, Z. Yang, M. Yuce, L. Hoang, W. Liu, “A 128-channel 6mW wireless neural recording IC with spike feature extraction and UWB transmitter,” IEEE Transactions on Neural Systems and Rehabilitation Engineering, vol. 17, no. 4, pp. 312–321, Aug. 2009. C. Kim, S. Nooshabadi, “Design of a tunable all-digital UWB pulse generator CMOS chip for wireless endoscope,” IEEE Transactions on Biomedical Circuits and Systems, vol. 4, no. 2, pp.118–124, April 2010. H. Kim, Y. Joo, and S. Jung, “A tunable CMOS UWB pulse generator,” in Proceedings of the IEEE International Conference on Ultra-Wideband, Waltham, MA, 24 27 Sept. 2006, pp. 109−112. J. Radic, A. Djugova, L. Nadj, and M. Videnovic-Misic, “Feedback Influence on Performance of Ring Oscillator for IR-UWB Pulse Generator in 0.18um CMOS technology,” in Proceedings of the IEEE International Conference on Microelectronics, Nis, 13 – 16 May 2012, pp. 357−360. J. Radic, A. Djugova, L. Nadj, and M. Videnovic-Misic, “Resistive Feedback Influence on Ring Oscillator Performance for IR-UWB Pulse Generator in 0.13um CMOS technology,” in Proceedings of Small Systems Simulation Symposium, Nis, 12 – 14 Feb. 2012, pp. 73−76. X. Fan, G. Fischer, B. Dietrich, “An integrated 3.1 -5.1 GHz pulse generator for ultra-wideband wireless localization systems,” Advance in Radio Science, vol. 4, pp. 247−250, 2006. J. R. Fernandes, H. B. Gonçalves, L. B. Oliveira, and M. M. Silva, “A Pulse Generator for UWB-IR Based on a Relaxation Oscillator,” IEEE Transactions on Circuits and Systems–II: Express Briefs, vol. 55, No. 3, pp. 239–243, 2008. A.M. El-Gabaly, C.E. Saavedra, “A 5-GHz energy-efficient tunable pulse generator for ultra-wideband applications using a variable attenuator for pulse shaping,” International Journal of Circuit Theory and Applications, doi: 10.1002/cta.792, 2011.
of Technical Sciences, University of Novi Sad/Department for Power, Electronics and Communications Engineering, Novi Sad, Serbia [email protected], [email protected], [email protected],[email protected]
Abstract—A novel energy-efficient tunable impulse radio ultra wide band (IR-UWB) pulse generator (PG) for the high data rate 3.1 − 7.5 GHz band applications is proposed. Glitch generator, switched ring oscillator, buffer and pulse shaping filter are the key components. The circuit is scalable both in bandwidth and center frequency. The glitch
generator combines falling edge of the input signal and its delayed inverse, allowing the impulse duration to be tuned over a wide range (250 – 660 ps) by varying the delay between the edges. The generated impulse duration approximately defines the PG’s signal width and thus its spectrum bandwidth. The ring oscillator frequency, which determines the spectrum center frequency, is controlled by the gate control voltage of the PMOS transistor used as an inverter feedback in the ring oscillator. Post-layout simulations show the pulse amplitude of 261 mV and the pulse duration around 700 ps. The total power consumption is only 697 μW with a supply voltage of 1.8 V. The PG is designed in UMC 0.18μm CMOS technology with the total
chip area of 602×587 μm2.
I. INTRODUCTION Since the Federal Communications Commission (FCC) allocated the 3.1 − 10.6 GHz unlicensed spectrum for commercial ultra wideband (UWB) application in February 2002, several technologies have been developed to satisfy the communication market requirements [1]. Carrier-less Impulse Radio Ultra Wide Band (IR-UWB) approach, with extremely short duration pulses (less than 1 ns) transmission, has draw much attention from both academic and industrial circles. It potentially offers several advantages, including high data rates, low cost, low power and complexity (without mixer and power amplifier), reduced multipath fading, high time and range resolution, and low probability of undesired detection and interception [2 − 4]. The IR-UWB appears to be a good candidate for high data rate short-range and low data rate wireless communication and biomedical applications such as wireless personal area networks (WPAN) [5 − 8], interchip communications [9, 10], and UWB biotelemetry [11, 12]. A pulse generator plays the key role in an IR-UWB system design because it produces pulse train which spectrum, with sufficient power level, has to satisfy all FCC requirements. Therefore, it is extremely challenging to design UWB transmitter that complies with the FCC This work was supported in part by the Ministry of Education and Science, Republic of Serbia, on the project no. TR-32016, and by FP7 project no. 256615.
demands while achieving wide bandwidth, low power and low complexity. The pulse generator should also be tunable to provide compensation due to process, voltage and temperature variations (PVT), and changes in the communication channel or antenna performances. In this paper, a new low power and low complexity tunable pulse generator, covering the 3.1 − 7.5 GHz spectrum band, is proposed. The presented topology designed in UMC 0.18μm CMOS technology is analyzed in Section III. Post-layout simulation results are given in Section IV followed by discussion and comparison with the other published pulse generator designs. The Section V concludes the paper. II. FCC SPECTRAL MASK AND REGULATIONS According to the FCC, an UWB system is allowed to transmit information in the 3.1 − 10.6 GHz for all types of communications. To prevent interference with the already existing communication systems such as WiMax, Bluetooth and GSM, the maximum average power level of the UWB transmitter is limited to −41.3 dBm/MHz with a maximum peak power level of 0 dBm/50 MHz [1]. In the GPS band (0.96 – 1.61 GHz), there is even more stringent regulation: less than −75.3 dBm/MHz is needed to avoid interference problems. The Power Spectral Density (PSD) in frequency interval from 1.61 GHz to 3.1 GHz depends on the type of application (indoor, outdoor, GPS, wall & medical imaging, through-wall imaging & surveillance system). Fig. 1 shows the FCC mask and regulations for the indoor and outdoor UWB communications (including Part 15 limit) [1] that pulse spectrum has to comply. Due to many reported interferences with wireless local area network (WLAN) systems operating in the 5 – 6 GHz
Figure 1. FCC indoor and outdoor spectral mask for UWB applications [1].
band, the UWB band is usually subdivided into two bands: 3 − 5 GHz (lower-band) and 6 − 10.6 GHz (higher-band). Although the higher-band operation offers advantages like wider bandwidth, higher data rate, and immunity from interference with WiMax, the lower UWB band is much more explored due to its less complex system implementation. Furthermore, circuit consumption is reduced because of the technology employed and antenna complexity is decreased by using the band below 5 GHz. The FCC rules define only the frequency bands and the radiated power spectral density (PSD) but there are no requirements on the time-domain shapes. However, as the shape of the pulse generator signal determines its spectrum characteristic and effectively dictates specific system (UWB transmitter) requirements, its generation is one of the essential considerations in the UWB design. Pulse shapes usually used in the impulse radio technology are based on the Gaussian pulse and its derivatives. For indoor systems, the 5th or higher order derivative of the Gaussian pulse should be used to comply with the allocated indoor spectrum mask [13]. III. PROPOSED PULSE GENERATOR ARCHITECTURE The proposed topology is shown in Fig. 2. It is composed of a glitch generator, a switched oscillator, a two-stage buffer, and a pulse shaping filter. The switched oscillator consists of a three-stage ring oscillator, (inverter stages M1 – M3), two feedback resistors Rosc, a control transistor M6, and a pair of oscillation-enabling switches (transistors M4 and M5). The ring oscillator is one of the most commonly used topologies in the pulse generator design due to its simple architecture occupying small chip area. Furthermore, it offers fast transient response as it has short start-up time and small resistance at each inverter feedback nod. Advantages mentioned above are the most important requirements for low power and high date rate UWB applications. The resistors Rosc, feedbacks in the second and third inverter stage, increase the ring oscillating frequency by decreasing the input (Miller) capacitance [14]. PMOS transistor M6 is used for the frequency tuning to enable compensation due to the process-voltage-temperature (PVT) variations and additional spectrum fitting within the FCC spectral mask [12]. This can be accomplished by changing the transistor M6 gate control voltage Vctrl. The oscillation-enabling switches control the oscillation process based on the on-off signal. The ring oscillator is
turned on by transistor M4 at the on-off signal high level. The inverter stages output voltage values are determined by the size ratio of the corresponding PMOS and NMOS transistors. During the control signal low level, the transistor M4 is switched off, and no signal is generated at the oscillator output (the output voltage is close to Vdd). Since the ring oscillator and the buffer stage are switched off during the inactive period, the power consumption is minimized. Furthermore, transistor M5 connects the M1 transistor output (the M2 transistor input) to Vdd, and thus provides the oscillation start from the initial state at the rising edge of the on-off signal. As the ring oscillator is switched on/off in accordance with the on-off signal state, the control signal duration defines approximately the length of the pulse generator signal and thus its bandwidth. The shorter the on-off signal, the wider the output signal bandwidth is obtained. To provide signal covering frequency range in the order of several GHz, the control signal should be sharp and narrow (duration less than 1 ns). Moreover, it is very desirable to enable tuning of the oscillation-enabling pulse duration to allow additional spectrum fitting within the FCC spectral mask and compensation due to process variations and changes in communication system. A sub-nanosecond control pulse is made by the glitch generator driven by the input trigger in signal (controlled by a microcontroller). The glitch generator consists of three inverters, a digitally controlled capacitor bank and a NOR gate. The main block in the circuit is the CMOS NOR gate fed by the input signal and its delayed inverse. As the gate output is high only if both inputs are low, the short pulse is created at the falling edge of the in signal. The generated signal duration is determined by the period when the both gate inputs are low or the delay of the inverted signal. This time interval is specified by the propagation delay through inverter and the capacitance of the digitally controlled capacitor bank. The capacitance bank is composed of capacitors Cb1 and Cb2, and transistor switches M11 and M12. To provide steep rising and falling edge of the control signal for a high out-of-band rejection, the capacitor bank is introduced between the inverter stages. Digital signals D1, and D2 switch off/on adequate capacitors and thus determine the total bank capacitance directly proportional to the on-off signal duration. This allows the delay and the pulse duration to be varied by changing the digital control signals. With the bank capacitance digital tuning, the pulse can have duration approximately ranging from 250 ps to 660 ps. The two-stage buffer isolates the ring oscillator from the pulse shaping filter loading and improves the pulse
Figure 2. Proposed IR-UWB pulse generator.
generator current driving capability. The high-pass filter composed of the inductor L and two capacitors C1 and C2 additionally accommodates the pulse in the allowed FCC spectral mask. IV.
POST-LAYOUT SIMULATION RESULTS AND COMPARISON
The proposed topology was designed in mixed mode/RF UMC 0.18μm CMOS technology with supply voltage of 1.8 V. Simulations were performed using SpectreRF Simulator from Cadence Design System. Since one of the portable system’s biggest issues is battery life, the pulse generator was optimized with the main aim to minimize the power consumption. Additionally, the signal spectrum should meet efficiently the FCC spectrum demands and cover the lower UWB bandwidth, while still keeping acceptable values for remaining Figures of Merits (FOMs). Regarding the circuit’s spectrum characteristics or the spectrum center frequency, the main problem was limited set of transistor sizes available in the used technology as the ring oscillator frequency depends directly on transistors sizes. With the increase in transistors sizes the oscillation period T rises while the oscillating frequency decreases (f0=1/T) proportionally. For the standard three-stage ring oscillator design (without any feedback) with the smallest NMOS transistors (W/L=25μm/0.18μm) and approximately two times larger PMOS transistors (W/L=45μm/0.18μm), the oscillation frequency of 3.77 GHz was obtained. It should be noted that the PMOS transistor are usually made larger than NMOS transistor in inverter topology to compensate for the lower carrier mobility of holes and set VTH closer to Vdd/2. Although the obtained f0 value is close to the center of the lower UWB bandwidth, it is not high enough as effects that deteriorate this parameter, such as the fabrication process and the PVT variations, are not taken into account. It should be mentioned that higher oscillation frequency could be achieved without PMOS transistor M5. However, this transistor enables the oscillation start from the same initial state. To increase the ring oscillator frequency, the resistive feedback was used in the second and third inverter stage. PMOS transistor M6 was introduced as the first inverter feedback and means of the f0 control. Further increase in the frequency could be achieved with resistive feedback in the first buffer stage.
Nevertheless, this method would noticeably increase the power consumption. The photography of the pulse generator layout is shown in Fig. 3. The integrated circuit (IC) occupies a die area of 602 × 587 μm2 including bonding pads. It supports the on-off keying (OOK) modulation. This type of the modulation is chosen because of its simplicity and thus the less complex transmitter realization. The post-layout simulation results in time and spectrum domain for the generated UWB pulse are given in Figs. 4 and 5. The pulse duration is around 0.7 ns and the peak-to-peak amplitude Vpp on a 50 Ω output load is 261 mV. Signal Power Spectral Density occupies the spectrum range from 3.1 GHz to 7.5 GHz with more than 20 dB of side-lobe rejection, and fully meet the FCC spectral mask except in the frequency range around 1 GHz. The PSD has maximum value of -44.2 dBm/MHz at 4.7 GHz. This peak value could be increased to the FCC maximum allowed value by choosing the appropriate value of the transistor M6 gate control voltage Vctrl and combination of digital signals D1 and D2. But in that case the signal bandwidth would be decreased. The pulse generator operates in burst mode with low duty cycle and pulse repetition frequency (PRF) of 100 MHz, and thus consumes very little power. The average power consumption, including the glitch generator, the buffer stages and the filter, is only 698 μW, corresponding to 6.98 pJ energy consumption per pulse (for the PRF of 100 MHz). In general, the nature of the IR-UWB communication allows saving power between each pulses and consuming energy only during the pulse generation. Table 1 summarizes the performance of the proposed
Figure 4.
Figure 3. Proposed IR-UWB pulse generator layout.
Pulse generator output waveform.
Figure 5. Pulse generator output in spectrum domain.
TABLE I.
SIMULATIONS RESULTS SUMARY AND COMPARISON WITH REPORTED PULSE
[3]
GENERATORS
Reference
This work
Ref [16]
Ref [17]
Ref [18]
Power cons. [mW]
0.698
55
2.5
3.8
BW (-10 dB) [GHz]
3.1 − 7.5
3.1 − 5.1
3.0 − 7.0
3.3 − 6.3
Amplitude (Vpp) [mV]
261
80
1000
150
700
1000
600
500-900
0.35
N/A
0.02*
0.44
100
N/A
1000
525 – 910
IHP 0.25μm BiCMOS
0.35μm CMOS
0.13μm CMOS
Pulse length [pS] Die area [mm2] PRF [MHz]
[5]
[6]
[7]
[8]
UMC 0.18μm CMOS * the core (active) area only Technology
[4]
IR-UWB pulse generator compared to the FOMs of the recently published works. Although, it can be difficult to make fair comparisons when different specifications and technologies are used, it is clear that the proposed circuit has by far the lowest power consumption and the peak-topeak amplitude higher than in Refs [16], [18]. The chip area is reduced compared to Ref [18], while the core (active area) is only given in Ref [17]. Other Figures of Merits are comparable to the results given by the authors. The proposed architecture is suitable for low voltage and ultra-low power UWB wireless applications covering the 3.1 GHz to 7.5 GHz frequency range. V. CONCLUSION A new energy-efficient tunable pulse generator has been designed in UMC 0.18µm CMOS technology for high data rate 3.1 – 7.5 UWB applications. The spectrum and time domain signal adjustment is provided with the adequate PMOS gate control voltage and by tuning capacitance of the digitally controlled capacitor bank. This allows the control pulse duration to be varied over a wide range (250 − 660 ps). The post-layout simulation results of the proposed ring oscillator-based architecture demonstrate very low average power consumption (less than 698 μW at 100 MHz pulse repetition rate), high peak-to-peak amplitude and small chip area (602×587 μm2 including bonding pads).
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
REFERENCES [1]
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