A Low-Quiescent Current Two-Input/Output Buffer Amplifier for LCDs
A Low-Quiescent Current Two-Input/Output Buffer Amplifier for LCDs Chih-Wen Lu Department of Engineering and System Science National Tsing Hua University Hsinchu, Taiwan, R.O.C. [email protected]
Ping-Yeh Yin Department of Electrical Engineering National Chi Nan University Puli, Taiwan, R.O.C. [email protected]
Kuo, Hsuan-Lun Department of Engineering and System Science National Tsing Hua University Hsinchu, Taiwan, R.O.C. [email protected]
Abstract—This study proposes a low-quiescent current twoinput/output buffer amplifier for LCD applications. A current reuse technique is employed in the output stage of the buffer amplifier to reduce the quiescent current consumption. An experimental prototype 6-bit LCD column driver with the proposed buffer amplifiers implemented in a 0.35-μm CMOS technology demonstrates that an average value of 0.6 μA static current is consumed in one channel driver. The settling time to settle within 0.2% of the final voltage is 6 μs under a 30-KΩresistance and 30-pF-capacitance load. The area of this twoinput/output buffer amplifier is 21.5 μm × 190 μm.
I.
INTRODUCTION
With the increase in use of compact, light-weighted, lowpower Liquid-Crystal Displays (LCDs), there is a large demand to develop a low-power dissipation LCD driver [1-2]. An LCD driver is generally composed of column drivers, gate drivers, a timing controller, and a reference source. The column drivers are especially important for achieving highspeed driving, high resolution, and low-power dissipation. A column driver generally includes registers, data latches, digital-to-analog converters (DACs) and output buffers. Among these, the output buffers determine the speed, resolution, and power dissipation of the column drivers [3-5]. Due to the hundreds of buffer amplifiers built into a single chip, the buffer amplifier should occupy a small die area, and its static power consumption should be small. In order to improve the lifetime of the liquid crystal material, the liquid crystal of active matrix liquid crystal displays should be driven by a so-called inversion method, which alternates the positive and negative polarities between the liquid-crystal cell with respect to a common backside electrode. There are three inversion methods, which are frame, line and dot inversions for LCD driving. The dot inversion method is preferred in the high-resolution displays [6]. In the previous work [6], a rail-to-rail dot-inversion driving scheme, which utilizes two complementary differential
978-1-4673-0219-7/12/$31.00 ©2012 IEEE
Salvatore Pennisi Department of Electrical Electronics and Systems Engineering University of Catania Catania, Italy [email protected]
amplifiers to drive a pair of column lines, was proposed. Figure 1 shows the driving method. Two channels of driving circuits, in which one channel takes the responsibility for driving negative polarity and the other for driving positive polarity, are grouped to drive a pair of adjacent column lines. PMOS input buffers are used to drive positive-to-negative polarity operation. NMOS input buffers are used for the transition of negative-to-positive polarity. The PMOS input buffers have a large discharge capability and vice versa for the NMOS input buffers. In this work, we combine these two buffers as a two-input/output buffer amplifier. A current reuse technique is employed in the proposed buffer amplifier to reduce the quiescent power consumption.
Figure 1 A rail-to-rail dot-inversion driving scheme. II.
PROPOSED BUFFER AMPLIFIER
A. Analysis of a Typical Two-Stage Op Amp A class-AB op amp is usually connected to a unity buffer for driving highly capacitive column lines of the display panel. Because the buffer amplifiers are required to have a high open-loop gain to obtain a low value of the systematic offset voltage, a two-stage amplifier is usually used in LCD drivers. A two-stage amplifier requires compensation for stability. Some buffer amplifiers adopt the output node as a dominant pole to achieve enough stability without a Miller capacitance [3, 6]. However, a charge conservation technique is commonly
1975
used in some LCD drivers to reduce the dynamic power dissipation [7]. Before a new scanning driving, all column lines are isolated from the buffers. Since the buffer amplifiers experience no load for a period of time, these amplifiers require the Miller compensation. Figure 2 shows an equivalent circuit of a typical two-stage op amp where gm1 and gm2 are the transconductances of the first and second stages, respectively; rO1 and rO2 are the output resistances of the first and second stages, respectively; CO1 and CO2 are the parasitic capacitances at output nodes of the first and second stages, respectively; CC is the Miller compensation capacitor; and RL and CL are resistive and capacitive loads, respectively. The open-loop transfer function, AO(s), can be obtained from Figure 2. That is:
⎛ s ⎞⎛ s ⎞ Adc ⎜1 + ⎟⎜1 + ⎟ ωZ 1 ⎠⎝ ωZ 2 ⎠ ⎝ AO ( s ) = ⎛ s ⎞⎛ s ⎞⎛ s ⎞ ⎜1 + ⎟⎜ 1 + ⎟ ⎜1 + ⎟ ω ω ω P1 ⎠⎝ P 2 ⎠⎝ P3 ⎠ ⎝
(1)
where Adc = g m1 g m 2 rO1rO 2
(2)
1 ωZ 1 = CL RL
(3)
gm 2 CC
(4)
ωZ 2 = −
operated under no load, the open-loop transfer function, AO' ( s ) , can be expressed as:
⎛ s ⎞ ⎜1 + ' ⎟ ω Z ⎠ ⎝ AO' ( s ) = Adc ⎛ s ⎞⎛ s ⎞ ⎜1 + ' ⎟⎜ 1 + ' ⎟ ⎝ ωP1 ⎠⎝ ωP 2 ⎠
(9)
where
Adc = g m1 g m 2 ro1ro 2
(10)
gm2 CC
(11)
ωZ' = − ωP' 1 ≅
1 ro1ro 2 g m 2 CC
(12)
ωP' 2 ≅
gm2 CO1 + CO 2
(13)
The zero of ωZ' is a negative value, so it can not compensate for the pole of ωP' 2 . Figure 3 shows the open-loop frequency characteristic of a two-stage op amp with/without CL and RL loads where the solid line and dashed line show the frequency characteristics with and without CL and RL loads, respectively. The phase margin of the op amp can be calculated from the equations below.
ωP1 ≅
1 ro1ro 2 g m 2 CC + CL rO 2
(5)
⎛ω ⎞ tan −1 ⎜ t ⎟ = 90D − PM ⎝ ωZ ⎠
(14)
ωP 2 ≅
CC g m 2 + CL ro1 CC CL
(6)
gm2 1 = g m1 tan 90D − PM
(15)
ωP 3 ≅
1 ( CO1 + CO 2 ) RL
(7)
(
The larger ratio of gm2 over gm1, the larger the phase margin. If we want to achieve a phase margin of 75°, the value of gm2 should be 3.7 times of the value of gm1. Hence, the output stage of the buffer amplifier consumes more quiescent power than that of the first stage.
The unity gain frequency is
ωt ≅ Adc ωP1 =
g m1 g m 2 CC g m 2 + CL rO1
)
(8)
AO ( jω )
ωP1
ωP' 1
ωZ 1 ωP 2 ωt
Figure 2 Equivalent circuit of a typical two-stage op amp. The equivalent circuit contains three poles. However, the third pole is far away from the other poles and zeros, so it is insignificantly affect the phase margin. The zero of ωZ1 compensates for the pole of ωP2. If the buffer amplifier is
ωt'
ωZ' ωP' 2
ωZ 2
ω ωP 3
Figure 3 Open-loop frequency characteristic of a two-stage op amp with/without CL and RL loads.
1976
B. Proposed Two-Input/Output Buffer Amplifier To reduce the quiescent power dissipation, we combine the NMOS input and PMOS input buffer amplifiers into a twoinput/output buffer amplifier where a current reuse technique is employed in the output stage. Figure 4 shows the architecture of the proposed two-input/output buffer amplifier. It consists of an NMOS input and a PMOS input one-stage differential amplifiers, a complementary common source amplifier, M11-M12, and a floating bias circuit, Ib1, Ib2, and M13-M16. Two outputs, out1 and out2, are isolated by M13 and M15. M13-M14 and M15-M16 form two floating current mirrors. The quiescent current, I11 and I12, of the complementary common source amplifier, M11-M12, is biased by the two floating current mirrors. That is:
⎡ (W L )13 (W L )15 ⎤ I11 = I12 = I b1 ⎢1 + + ⎥ ⎣⎢ (W L )14 (W L )16 ⎦⎥
the circuit may suffer from a systematic output dc offset voltage. However, the dc offset voltage can be eliminated by sizing the transistors so as to satisfy the following constraint:
I b 3 (W L )11 I b 4 (W L )12 = 2 (W L )9 2 (W L )4
where Ib4 is the bias current for PMOS input one-stage differential amplifier.
(16)
Vbias2
M7
M6
Vbias2
I11
M1 M2 M4
Ib2
out2 in2
I11 out1
M13 M15
M14
M16
Ib4
CC4 in2
M3
M13 M15
CC1 CC2
in1
M8
M11
Ib3
Vbias1
M16
M14
M17
Ib1
out1 Ib1
M10
M9
where Ib1 = Ib2. Although two additional bias currents, Ib1 and Ib2, are required, they consume smaller currents than that of the complementary common source amplifier. The output, out1, has a large charging capability and the output, out2, has a large discharging function. Hence, the proposed twoinput/output buffer amplifier us suitable for the application in the LCD driver architecture of Figure 1. NMOS input one -stage diff. amp. M11 in1
(17)
⎡ (W L )13 (W L )15 ⎤ = I b1 ⎢1 + + ⎥ ⎢⎣ (W L )14 (W L )16 ⎥⎦
M5 Vbias1
Ib2
out2
CC3 I12
M18 M12
Figure 5 Schematic of the proposed buffer amplifier.
I12
III.
M12 PMOS input one -stage diff. amp.
Figure 4 Architecture of the proposed two-input/output buffer amplifier. Figure 5 shows the schematic of the proposed buffer amplifier. The NMOS input and PMOS input one-stage differential amplifiers are consisted of M1-M5 and M6-M10, respectively. The capacitors, CC1 – CC4 are the Miller compensation capacitors. In the stable state, the currents flowing in M9 and M10 are both Ib3/2 where Ib3 is the bias current for NMOS input one-stage differential amplifier. The drain voltage of M10 equals to that of M9. The quiescent current of M11 is then mirrored from M9. Similarly, the quiescent current of M12 is mirrored from M4. Since the complementary common source amplifier is biased by the floating bias circuit and two one-stage differential amplifiers,
MEASUREMENT RESULTS
To verify the performance of the proposed buffer amplifier, a 6-bit 12-channel LCD column driver with the proposed buffer amplifiers was designed and was fabricated using a 0.35-μm CMOS technology. Figure 6 shows the die photograph. The area of one two-input/output buffer amplifier is 21.5 μm × 190 μm. The two-input/output buffer amplifier consumes 1.2-μA static current. This means that only 0.6-μA static current is consumed in one channel driver. Figure 7 shows the measured output waveform with a 30KΩ-resistance and 30pF-capacitance load when the digital data change from “000000” to “111111”. The settling time to settle within 0.2% of the final voltage is 6 μs. Figure 8 shows the measured results for DNL/INL in a linear 6 bit gray scale for 24 channels. The maximum DNL and INL are respectively measured as 0.024 LSB and 0.072 LSB with 1LSB = 32 mV. Table 1 summarizes the performance of the buffer amplifier compared with the stat-of-the-art.
1977
3 two-input/output buffer amplifiers
6 DACs
Resistor string
Bias ckt 3 two-input/output buffer amplifiers
6 DACs
This work
[2]
[3]
[4]
Process tech.
0.35-μm CMOS
0.13-μm CMOS
0.35-μm CMOS
0.35-μm CMOS
VDD
5V
5V
3.3 V
5V
Quiescent current
0.6 μA/channel
2 μA
7.4 μA
NA
Loads
RL = 30KΩ
RL=10KΩ
CL = 30 pF
CL=24 pF
CL = 600 pF
CL = 400 pF
Settling time
6μs (0.2%)
1.95 μs (10 mV)
8 μs (0.2%)
0.95 μs
Area
21.5 μm × 190 μm (two channels)
100 μm × 45 μm
86 μm × 73.5 μm
100 μm × 100 μm
Figure 6 Die photograph.
IV.
CONCLUSIONS
This work presents a low-quiescent current twoinput/output buffer amplifier. A current reuse technique is employed in the output stage of the buffer amplifier to reduce the quiescent current consumption. An experimental prototype 6-bit LCD column driver with the proposed buffer amplifiers was implemented in a 0.35-μm CMOS technology. The circuit draws an average value of 0.6 μA static current in one channel driver and exhibits the settling time of 6 μs for settling within 0.2 % of the final voltage under a 30 kΩ and a 30 pF capacitance loads. The measured data show that the proposed buffer amplifier is very suitable for dot-inversion LCD column drivers. ACKNOWLEDGMENT Figure 7 Measured output waveform with a 30KΩ-resistance and 30pF-capacitance load when the digital data change from “000000” to “111111”.
DNL (LSB)
0.050
REFERENCES [1]
0.025 0.000
[2]
-0.025 -0.050
0.10
INL (LSB)
The authors would like to thank the Chip Implementation Center of the National Science Council for their support in chip fabrication.
[3]
0
10
20
30
40
50
60 [4]
0.05 0.00 -0.05 -0.10
[5]
0
10
20 30 40 50 Input Digital Data
60
[6]
Figure 8 Measured results for DNL/INL in a linear 6 bit gray scale for 24 channels.
[7]
Table 1 Performance Summary.
1978
Y.-K. Choi, et al, “A Compact Low-Power CDAC Architecture for Mobile TFT-LCD Driver ICs,” ISSCC Dig. Tech. Papers, pp. 176-177, Feb. 2008. R. Ito, T. Itakura, and H. Minamizaki, “A class AB amplifier for LCD driver,” 2007 Symposium on VLSI Circuits Digest of Technology Papers, 14-16 June 2007, pp. 148-149. M-C Weng and J-C Wu, “A Compact Low-Power Rail-to-Rail Class-B Buffer for LCD Column Driver,” IEICE Trans. Electron., Vol. E85-C, No. 8 August, pp. 1659-1663, 2002. G-T Hong and C-H Shen, “A low Offset High Voltage Swing Rail-toRail Buffer Amplifier with for LCD Driver,” 2007 IEEE Conference on Electron Devices and Solid-State Circuits, 2007 EDSSC, pp. 10251030, 20-22 Dec. 2007. Davide Marano, Gaetano Palumbo, and Salvatore Pennisi, "Low-Power Dual-Active Class-AB Buffer Amplifier with Self-Biasing Network for LCD Column Drivers," ISCAS 2010, Paris, pp. 2832-2835. C-W. Lu and K.J. Hsu, “A high-speed low-power rail-to-rail column driver for AMLCD application,” IEEE Journal of Solid-State Circuits, vol. 39, No. 8, pp. 1313-1320, Aug. 2004. J-S Kim, D-K Jeong, and G. Kim, “A Multi-Level Multi-Phase ChargeRecycling Method for Low-Power AMLCD Column Drivers,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 1, January, pp. 74-84, 2000.
Ping-Yeh Yin Department of Electrical Engineering National Chi Nan University Puli, Taiwan, R.O.C. [email protected]
Kuo, Hsuan-Lun Department of Engineering and System Science National Tsing Hua University Hsinchu, Taiwan, R.O.C. [email protected]
Abstract—This study proposes a low-quiescent current twoinput/output buffer amplifier for LCD applications. A current reuse technique is employed in the output stage of the buffer amplifier to reduce the quiescent current consumption. An experimental prototype 6-bit LCD column driver with the proposed buffer amplifiers implemented in a 0.35-μm CMOS technology demonstrates that an average value of 0.6 μA static current is consumed in one channel driver. The settling time to settle within 0.2% of the final voltage is 6 μs under a 30-KΩresistance and 30-pF-capacitance load. The area of this twoinput/output buffer amplifier is 21.5 μm × 190 μm.
I.
INTRODUCTION
With the increase in use of compact, light-weighted, lowpower Liquid-Crystal Displays (LCDs), there is a large demand to develop a low-power dissipation LCD driver [1-2]. An LCD driver is generally composed of column drivers, gate drivers, a timing controller, and a reference source. The column drivers are especially important for achieving highspeed driving, high resolution, and low-power dissipation. A column driver generally includes registers, data latches, digital-to-analog converters (DACs) and output buffers. Among these, the output buffers determine the speed, resolution, and power dissipation of the column drivers [3-5]. Due to the hundreds of buffer amplifiers built into a single chip, the buffer amplifier should occupy a small die area, and its static power consumption should be small. In order to improve the lifetime of the liquid crystal material, the liquid crystal of active matrix liquid crystal displays should be driven by a so-called inversion method, which alternates the positive and negative polarities between the liquid-crystal cell with respect to a common backside electrode. There are three inversion methods, which are frame, line and dot inversions for LCD driving. The dot inversion method is preferred in the high-resolution displays [6]. In the previous work [6], a rail-to-rail dot-inversion driving scheme, which utilizes two complementary differential
978-1-4673-0219-7/12/$31.00 ©2012 IEEE
Salvatore Pennisi Department of Electrical Electronics and Systems Engineering University of Catania Catania, Italy [email protected]
amplifiers to drive a pair of column lines, was proposed. Figure 1 shows the driving method. Two channels of driving circuits, in which one channel takes the responsibility for driving negative polarity and the other for driving positive polarity, are grouped to drive a pair of adjacent column lines. PMOS input buffers are used to drive positive-to-negative polarity operation. NMOS input buffers are used for the transition of negative-to-positive polarity. The PMOS input buffers have a large discharge capability and vice versa for the NMOS input buffers. In this work, we combine these two buffers as a two-input/output buffer amplifier. A current reuse technique is employed in the proposed buffer amplifier to reduce the quiescent power consumption.
Figure 1 A rail-to-rail dot-inversion driving scheme. II.
PROPOSED BUFFER AMPLIFIER
A. Analysis of a Typical Two-Stage Op Amp A class-AB op amp is usually connected to a unity buffer for driving highly capacitive column lines of the display panel. Because the buffer amplifiers are required to have a high open-loop gain to obtain a low value of the systematic offset voltage, a two-stage amplifier is usually used in LCD drivers. A two-stage amplifier requires compensation for stability. Some buffer amplifiers adopt the output node as a dominant pole to achieve enough stability without a Miller capacitance [3, 6]. However, a charge conservation technique is commonly
1975
used in some LCD drivers to reduce the dynamic power dissipation [7]. Before a new scanning driving, all column lines are isolated from the buffers. Since the buffer amplifiers experience no load for a period of time, these amplifiers require the Miller compensation. Figure 2 shows an equivalent circuit of a typical two-stage op amp where gm1 and gm2 are the transconductances of the first and second stages, respectively; rO1 and rO2 are the output resistances of the first and second stages, respectively; CO1 and CO2 are the parasitic capacitances at output nodes of the first and second stages, respectively; CC is the Miller compensation capacitor; and RL and CL are resistive and capacitive loads, respectively. The open-loop transfer function, AO(s), can be obtained from Figure 2. That is:
⎛ s ⎞⎛ s ⎞ Adc ⎜1 + ⎟⎜1 + ⎟ ωZ 1 ⎠⎝ ωZ 2 ⎠ ⎝ AO ( s ) = ⎛ s ⎞⎛ s ⎞⎛ s ⎞ ⎜1 + ⎟⎜ 1 + ⎟ ⎜1 + ⎟ ω ω ω P1 ⎠⎝ P 2 ⎠⎝ P3 ⎠ ⎝
(1)
where Adc = g m1 g m 2 rO1rO 2
(2)
1 ωZ 1 = CL RL
(3)
gm 2 CC
(4)
ωZ 2 = −
operated under no load, the open-loop transfer function, AO' ( s ) , can be expressed as:
⎛ s ⎞ ⎜1 + ' ⎟ ω Z ⎠ ⎝ AO' ( s ) = Adc ⎛ s ⎞⎛ s ⎞ ⎜1 + ' ⎟⎜ 1 + ' ⎟ ⎝ ωP1 ⎠⎝ ωP 2 ⎠
(9)
where
Adc = g m1 g m 2 ro1ro 2
(10)
gm2 CC
(11)
ωZ' = − ωP' 1 ≅
1 ro1ro 2 g m 2 CC
(12)
ωP' 2 ≅
gm2 CO1 + CO 2
(13)
The zero of ωZ' is a negative value, so it can not compensate for the pole of ωP' 2 . Figure 3 shows the open-loop frequency characteristic of a two-stage op amp with/without CL and RL loads where the solid line and dashed line show the frequency characteristics with and without CL and RL loads, respectively. The phase margin of the op amp can be calculated from the equations below.
ωP1 ≅
1 ro1ro 2 g m 2 CC + CL rO 2
(5)
⎛ω ⎞ tan −1 ⎜ t ⎟ = 90D − PM ⎝ ωZ ⎠
(14)
ωP 2 ≅
CC g m 2 + CL ro1 CC CL
(6)
gm2 1 = g m1 tan 90D − PM
(15)
ωP 3 ≅
1 ( CO1 + CO 2 ) RL
(7)
(
The larger ratio of gm2 over gm1, the larger the phase margin. If we want to achieve a phase margin of 75°, the value of gm2 should be 3.7 times of the value of gm1. Hence, the output stage of the buffer amplifier consumes more quiescent power than that of the first stage.
The unity gain frequency is
ωt ≅ Adc ωP1 =
g m1 g m 2 CC g m 2 + CL rO1
)
(8)
AO ( jω )
ωP1
ωP' 1
ωZ 1 ωP 2 ωt
Figure 2 Equivalent circuit of a typical two-stage op amp. The equivalent circuit contains three poles. However, the third pole is far away from the other poles and zeros, so it is insignificantly affect the phase margin. The zero of ωZ1 compensates for the pole of ωP2. If the buffer amplifier is
ωt'
ωZ' ωP' 2
ωZ 2
ω ωP 3
Figure 3 Open-loop frequency characteristic of a two-stage op amp with/without CL and RL loads.
1976
B. Proposed Two-Input/Output Buffer Amplifier To reduce the quiescent power dissipation, we combine the NMOS input and PMOS input buffer amplifiers into a twoinput/output buffer amplifier where a current reuse technique is employed in the output stage. Figure 4 shows the architecture of the proposed two-input/output buffer amplifier. It consists of an NMOS input and a PMOS input one-stage differential amplifiers, a complementary common source amplifier, M11-M12, and a floating bias circuit, Ib1, Ib2, and M13-M16. Two outputs, out1 and out2, are isolated by M13 and M15. M13-M14 and M15-M16 form two floating current mirrors. The quiescent current, I11 and I12, of the complementary common source amplifier, M11-M12, is biased by the two floating current mirrors. That is:
⎡ (W L )13 (W L )15 ⎤ I11 = I12 = I b1 ⎢1 + + ⎥ ⎣⎢ (W L )14 (W L )16 ⎦⎥
the circuit may suffer from a systematic output dc offset voltage. However, the dc offset voltage can be eliminated by sizing the transistors so as to satisfy the following constraint:
I b 3 (W L )11 I b 4 (W L )12 = 2 (W L )9 2 (W L )4
where Ib4 is the bias current for PMOS input one-stage differential amplifier.
(16)
Vbias2
M7
M6
Vbias2
I11
M1 M2 M4
Ib2
out2 in2
I11 out1
M13 M15
M14
M16
Ib4
CC4 in2
M3
M13 M15
CC1 CC2
in1
M8
M11
Ib3
Vbias1
M16
M14
M17
Ib1
out1 Ib1
M10
M9
where Ib1 = Ib2. Although two additional bias currents, Ib1 and Ib2, are required, they consume smaller currents than that of the complementary common source amplifier. The output, out1, has a large charging capability and the output, out2, has a large discharging function. Hence, the proposed twoinput/output buffer amplifier us suitable for the application in the LCD driver architecture of Figure 1. NMOS input one -stage diff. amp. M11 in1
(17)
⎡ (W L )13 (W L )15 ⎤ = I b1 ⎢1 + + ⎥ ⎢⎣ (W L )14 (W L )16 ⎥⎦
M5 Vbias1
Ib2
out2
CC3 I12
M18 M12
Figure 5 Schematic of the proposed buffer amplifier.
I12
III.
M12 PMOS input one -stage diff. amp.
Figure 4 Architecture of the proposed two-input/output buffer amplifier. Figure 5 shows the schematic of the proposed buffer amplifier. The NMOS input and PMOS input one-stage differential amplifiers are consisted of M1-M5 and M6-M10, respectively. The capacitors, CC1 – CC4 are the Miller compensation capacitors. In the stable state, the currents flowing in M9 and M10 are both Ib3/2 where Ib3 is the bias current for NMOS input one-stage differential amplifier. The drain voltage of M10 equals to that of M9. The quiescent current of M11 is then mirrored from M9. Similarly, the quiescent current of M12 is mirrored from M4. Since the complementary common source amplifier is biased by the floating bias circuit and two one-stage differential amplifiers,
MEASUREMENT RESULTS
To verify the performance of the proposed buffer amplifier, a 6-bit 12-channel LCD column driver with the proposed buffer amplifiers was designed and was fabricated using a 0.35-μm CMOS technology. Figure 6 shows the die photograph. The area of one two-input/output buffer amplifier is 21.5 μm × 190 μm. The two-input/output buffer amplifier consumes 1.2-μA static current. This means that only 0.6-μA static current is consumed in one channel driver. Figure 7 shows the measured output waveform with a 30KΩ-resistance and 30pF-capacitance load when the digital data change from “000000” to “111111”. The settling time to settle within 0.2% of the final voltage is 6 μs. Figure 8 shows the measured results for DNL/INL in a linear 6 bit gray scale for 24 channels. The maximum DNL and INL are respectively measured as 0.024 LSB and 0.072 LSB with 1LSB = 32 mV. Table 1 summarizes the performance of the buffer amplifier compared with the stat-of-the-art.
1977
3 two-input/output buffer amplifiers
6 DACs
Resistor string
Bias ckt 3 two-input/output buffer amplifiers
6 DACs
This work
[2]
[3]
[4]
Process tech.
0.35-μm CMOS
0.13-μm CMOS
0.35-μm CMOS
0.35-μm CMOS
VDD
5V
5V
3.3 V
5V
Quiescent current
0.6 μA/channel
2 μA
7.4 μA
NA
Loads
RL = 30KΩ
RL=10KΩ
CL = 30 pF
CL=24 pF
CL = 600 pF
CL = 400 pF
Settling time
6μs (0.2%)
1.95 μs (10 mV)
8 μs (0.2%)
0.95 μs
Area
21.5 μm × 190 μm (two channels)
100 μm × 45 μm
86 μm × 73.5 μm
100 μm × 100 μm
Figure 6 Die photograph.
IV.
CONCLUSIONS
This work presents a low-quiescent current twoinput/output buffer amplifier. A current reuse technique is employed in the output stage of the buffer amplifier to reduce the quiescent current consumption. An experimental prototype 6-bit LCD column driver with the proposed buffer amplifiers was implemented in a 0.35-μm CMOS technology. The circuit draws an average value of 0.6 μA static current in one channel driver and exhibits the settling time of 6 μs for settling within 0.2 % of the final voltage under a 30 kΩ and a 30 pF capacitance loads. The measured data show that the proposed buffer amplifier is very suitable for dot-inversion LCD column drivers. ACKNOWLEDGMENT Figure 7 Measured output waveform with a 30KΩ-resistance and 30pF-capacitance load when the digital data change from “000000” to “111111”.
DNL (LSB)
0.050
REFERENCES [1]
0.025 0.000
[2]
-0.025 -0.050
0.10
INL (LSB)
The authors would like to thank the Chip Implementation Center of the National Science Council for their support in chip fabrication.
[3]
0
10
20
30
40
50
60 [4]
0.05 0.00 -0.05 -0.10
[5]
0
10
20 30 40 50 Input Digital Data
60
[6]
Figure 8 Measured results for DNL/INL in a linear 6 bit gray scale for 24 channels.
[7]
Table 1 Performance Summary.
1978
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