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ADPLL design parameters determinations through noise modeling Bo Jiang, Tian Xia n University of Vermont, Burlington, VT 05405, USA
ar t ic l e i nf o
a b s t r a c t
Article history: Received 7 June 2014 Accepted 15 August 2014
This paper presents a methodology to determine all-digital phase-locked loop (ADPLL) circuit variables based on required design specifications, including output phase noise, fractional spur and locking time. An analytical model is developed to characterize the effects of different noise sources on ADPLL output phase noise and fractional spur. Applying the proposed noise model, circuit variables in ADPLL can be properly selected to meet phase noise, fractional spur and locking time requirements. For model validation, we collect ADPLL circuit designs published in recent literatures and perform model analysis. The analysis results and hardware measurements obtain good agreements. & 2014 Elsevier B.V. All rights reserved.
Keywords: ADPLL Phase noise Spur Fractional-N PLL Digitally controlled oscillator Frequency divider Phase–frequency detector
1. Introduction ADPLL is recently emerging to replace analog charge pump PLL [1] in many RF transceivers on account of its superior features including programmability, high noise immunity, small area, low voltage and ease of integration [2–4]. Generally, there are two main ADPLL architectures as shown in Fig. 1. Comparing with analog charge pump PLL, architecture-I ADPLL in Fig. 1(a) replaces the standard phase frequency detector (PFD), charge pump with a time-to-digital converter (TDC) based PFD that quantities the phase difference between reference clock and the feedback signal. The resulting phase difference is fed into the digital loop filter (DLF) instead of the analog filter to eliminate the high frequency noise. A programmable divider with ΔΣ modulator is used in the feedback path to set up the fractional divide ratio. In architectureII ADPLL, as shown in Fig. 1(b), the phase detector (PD) is designed by combining a counter and a TDC for comparing the difference between reference clock frequency control word (FCW) and the feedback frequency control word without a frequency divider in the feedback path. Like in an analog PLL, phase noise, spur and locking time are key characteristics of ADPLL frequency synthesizer. In the literature, there are numerous studies analyzing analog PLLs [5–10]. However, due to its unique architecture, there are new variables in ADPLL that must be carefully configured in order to meet performance requirements. These variables include TDC resolution, bit-width of
n
Corresponding author. Tel.: +1 802 656 8996. E-mail address: [email protected] (T. Xia).
different digital units, DLF coefficients and digitally controlled oscillator (DCO) resolution. In an ADPLL, besides oscillator noise, on account of the limited bit-width of different digital units, quantization noise is the major noise that may deteriorate performance. Therefore, the traditional analog PLL's analytic model cannot be applied directly for ADPLL design characterizations. Currently, there are limited researches dedicated to analyzing the relationship between performance and circuit variables that are applicable to both architectures of ADPLLs. In [11], TDC noise and DCO noise are analyzed for architecture-II ADPLL. In [12], authors present a zdomain model of architecture-II ADPLL without noise analysis. In [13], authors develop a z-domain model for analyzing DCO noise and TDC noise for architecture-II ADPLL. In [14–16], authors develop time domain models for ADPLL. In [17], authors propose a linear discrete time multi-rate model for ADPLL. However, the study of circuit variables and performance that are applicable for both architecture-I and architecture-II ADPLLs is lacking. Moreover, these analytical do provide guidance in determining variables based on performance constraints. ADPLL frequency synthesizer's phase noise and locking time are important performance parameters. When used in a communication system, low quality phase noise will reduce the effective signal to noise ratio, cause large bit error and bring down data rate. Therefore, it is important to investigate the relationship between ADPLL variables and phase noise and locking time performances. In [18], authors present a method to calculate the DLF variables according to bandwidth and phase margin. In [19], DLF coefficients are determined by loop bandwidth and damping ratio. However, no design procedure for determining ADPLL variables based on the phase noise specification is provided in these publications. In this
http://dx.doi.org/10.1016/j.vlsi.2014.08.001 0167-9260/& 2014 Elsevier B.V. All rights reserved.
Please cite this article as: B. Jiang, T. Xia, ADPLL design parameters determinations through noise modeling, INTEGRATION, the VLSI journal (2014), http://dx.doi.org/10.1016/j.vlsi.2014.08.001i
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paper, we extend our research in [20] to provide a design procedure for determining ADPLL DLF coefficients based on phase noise, locking time, bandwidth and damping ratio. This paper is organized as follows. Section 2 introduces noise model of ADPLL. Section 3 analyzes the fractional spur. Section 4 derives the closed loop transfer function of each noise source. Section 5 presents the method to determine the variables values considering performance constraints. Case studies are demonstrated in Section 6 to verify the proposed model. Section 7 contains the concluding remarks.
2. Phase noise model of ADPLL In order to evaluate phase noise, fractional spur and locking time, an ADPLL behavior model is developed. There are s-domain model and the z-domain model for architecture-II ADPLL presented in [11,13], respectively. In this paper, comprehensive analytical models of both architecture-I and architecture-II ADPLL as shown in Fig. 2, will be developed. In both architectures, there are five dominant noise sources, which are input reference clock noise ηref , TDC noise ηTDC , DCO oscillator noise ηDCO , DCO quantization noise ηDQ N and delta sigma modulator noise ηDSM . Generally, dominant noise in ADPLLs can be
categorized as oscillator noise and quantization noise. Reference oscillator contributes oscillator noise. DCO noise is composed of oscillator noise and quantization noise. TDC quantization noise caused by limited TDC resolution is the dominant noise source in PFD block. DCO quantization noise is caused by the limited bit number of DCO control bits. ΔΣ modulator also generates quantization noise for its limited output bit width. ADPLL output signal phase noise can be characterized from all noise sources. Sout ðf Þ ¼ ∑Si ðf Þ UjH i ðzÞj2
ð1Þ
where Si ðf Þ and H i ðzÞ represent the noise spectrum density and the corresponding closed loop transfer function of each noise in ADPLL. Below, each noise source will be analyzed. 2.1. Reference clock noise Reference clock noise is categorized as the oscillator noise. Its phase noise power spectrum density Sr ðf Þcan be described using oscillator phase noise model [16]: 2
SOSC ðf Þ ¼ k0 þk1 =f þ k2 =f þ k3 =f 2
3
ð2Þ
3
where k0 , k1 =f , k2 =f , and k3 =f represent thermal noise, flicker noise [23], carrier noise and inter-modulation of both carrier and transistor noise, respectively. 2.2. DCO quantization noise DCO noise is composed of oscillator noise and quantization noise [21,22]. The DCO oscillator noise SDCO ðf Þ can be described using Eq. (2). The DCO quantization noise is determined by the bit number of DCO control code. When DCO dithering resolution bit is NDCO , DCO quantization noise σ 2DQ N equalsð2 NDCO Þ2 =12. The PSD equals: SDQ N ¼
1 12 Uð2NDCO Þ2 U f r
ð3Þ
where f r is reference signal frequency and K DCO is DCO gain. 2.3. Delta sigma modulator noise
Fig. 1. ADPLL architecture. (a) Architecture-I, and (b) Architecture-II.
The multi-stage noise shaping (MASH) ΔΣ modulator is widely used in fractional-N ADPLLs. The quantization noise contributed by ΔΣ modulator is treated as an additive noise source [25]. For a ΔΣ modulator with transfer functionHΔΣ ðzÞ, the PSD of phase fluctuations equalsπ 2 jH ΔΣ ðzÞj2 =ð3f sΔ j1 z 1 j2 Þ. f sΔ is the sampling frequency of ΔΣ modulator. The z-domain transfer function of an mth-order MASH ΔΣ modulator isH ΔΣ ðzÞ ¼ ð1 z 1 Þm . The
Fig. 2. The z-domain phase noise model of phase-domain ADPLL. (a) Architecture-I ADPLL. (b) Architecture-II ADPLL.
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quantization noise spectrum density is deduced as [25]: SDS ðf Þ ¼ π 2 ½2 sin ðπ f =f sΔ Þ2ðm 1Þ =ð3f sΔ Þ
3. ADPLL fractional spur ð4Þ
2.4. TDC-PFD noise TDC quantization noise is the dominant noise source in phase detector. Fig. 3 shows a widely used N-bit TDC, where the input phase error goes through a delay chain. Flip-flops are connected to the outputs of inverters and sample the state of the delay chain. By using an edge detector and an encoder, the phase difference is converted to digital codes. TDC's resolution equals single inverter delayτT . For ADPLL, the gain of TDC GT is the ratio of TDC output code and input phase difference between the reference clock and the feedback signal. GT ¼ 1=ð2πτT f r Þ
ð5Þ
where f r is the reference signal frequency. For a BT -bit TDC, the maximum phase detection range is: P max ¼ ð2BT 1Þ=GT
ð6Þ
The standard deviation of TDC quantization noise σ 2TDC equalsτ2T =12. Normalizing σ TDC by ADPLL output signal period T out and converting it to phase in radians results in σ TDC ϕ ¼ 2πσ TDC =T out . Thus the TDC quantization noise PSD equals [11]: ST ¼
σ 2TDC ϕ fr
¼
ð2πσ TDC Þ f r T 2out
2
ðπτT f out Þ 3f r
2
¼
3
ð7Þ
where f out is ADPLL output signal frequency. From this equation, it is clear that ST can be reduced by increasing TDC resolution with a smallerτT . For instance, for a given f r and f DCO to f r ratioN, reducing τT by half will reduce ST by 3 dB.
2.5. Digital low pass filter analysis In ADPLL designs, proportional plus integral (PPI) filter as shown in Fig. 4 is widely adopted. The transfer function of PPI filter is H DF ðzÞ ¼ α þ β=ð1 z 1 Þ. Comparing with charge pump PLL, ADPLL can adjust its loop bandwidth by tuning the digital loop filter coefficients easily. For the low pass filter in an analog PLL, the filter circuit noise is mainly caused by electrical elements' thermal noise. However, in ADPLL digital low pass filter, the quantization noise is the dominant noise source. The DLF output connects to DCO, whose output has the same bit-width as that of DCO control word.
Spurious level of ADPLL output is another important parameter. In fractional-N ADPLL, one important spur specification is the fractional spur. The digital ΔΣ modulator is the fundamental source of fractional spurious tones in fractional-N ADPLL while the limited TDC output bit-width can further increase fractional spur level. For an mth-order MASH DSM applied in ADPLL, at locking state, the phase difference varies from ð2m 2Þπ =N to 2m π =N. In order to minimize the fractional spur level, TDC output should cover the phase difference range, thus: P max Z
ð2m þ 1 2Þπ 2m 1 ) 2BT 1 Z N N U f r U τT
ð8Þ
The primary frequency of the fractional spur isf spur ¼ F f rac f r . F f rac represents the fractional part of divider value N. The PSD of fractional spur in dB can be deduced as [33]: ! Δf max þ rollof f ðf spur Þ Sspur ¼ 20 log 2f spur ! ΔC max U K DCO þ rollof f ðf spur Þ ð9Þ ¼ 20 log 2f spur where ΔC max is the maximum control code variation and rollof f ðf Þ is defined as the magnitude of the closed loop transfer function of reference signal subtracting the factor of 20 log N. rollof f ðf Þ ¼ 20 log ðjH cl ðzÞjz ¼ ej2πf T r Þ 20 log N
ð10Þ
It is clear that ΔC max ¼ 2 1 when ΔΣ modulator is located in DCO function block. For ADPLL with ΔΣ modulator only existing in divider block, the maximum phase variation ϕdr at locking state equals 2π ð2m 1Þf r =f out . Thus ΔC max equals: m
ΔC max ¼ ϕdr GT ðα þ βÞ ¼ 2π f r GT ðα þ βÞð2m 1Þ=f out
ð11Þ
In order to verify Eq. (9), we compare the fractional spur PSD calculated from Eq. (9) and from measurement in [27]. The ADPLL in [27] is an architecture-I APDLL with a 1st order and a 2ndorder ΔΣ modulators in divider and DCO block, respectively. Its parameters are include: reference signal frequency equals 40 MHz, TDC resolution τT ¼ 1 ps, DCO gain K DCO ¼ 2 KHz=LSB, divider value
Fig. 4. z-domain of proportional plus integral filter.
Fig. 3. Traditional N-bit TDC in ADPLL.
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where GI ¼ 2π GT K DCO T ref =N, GII ¼ 2π GT K DCO T ref =FCW,T ref is reference clock period. 4.2. Transfer function of DCO oscillator noise Fig. 2 shows that, the transfer function of DCO features a high pass filter. The phase domain transfer function of DCO oscillator noise in each architecture can be expressed as: H ηDCO ðzÞI ¼
ðz 1Þ2 ðz 1Þ þGI ðαz þ β z αÞ 2
ðz 1Þ2
H ηDCO ðzÞII ¼
ðz 1Þ þGII ½αðz 1Þ þ β z 2
ð14Þ
ð15Þ
Fig. 5. Fractional spur of ADPLL in [27].
4.3. Transfer function of the DCO quantization noise
Table 1 Output phase noise differences between simulation and measurement at some typical frequencies. Fractional Spur
Output ADPLL Arch. frequency (GHz)
Prim. Prim. PSD (dBc) Freq. (Hz)
In architecture-I ADPLL, the transfer function of the DCO quantization noise in phase domain equals: H ηDQ N ðzÞI ¼
NGI ðz 1Þ=GT ðz 1Þ2 þ GI ðαz þ βz αÞ
In architecture-II ADPLL, it is: H ηDQ N ðzÞII ¼
Ref. [27] Simu. 10.88 M 118.7 Meas. 10M 118 Ref. [28] Simu. 15M 145.8 Meas. 15M 142.5 Ref. [29] Simu. 21.8 K 52.7 Meas. 20K 45
3.610878
I
1.5
I
5.37602183
II
T r K DCO ðz 1Þ ðz 1Þ2 þ GII ½αðz 1Þ þ βz
ð17Þ
4.4. Transfer function of the TDC noise Here, the phase domain transfer function of the TDC noise in architecture-I ADPLL is derived as:
N ¼ 90:27195, DLF coefficients α ¼ 2 and β ¼ 2 . The bandwidth of the PLL is 500 KHz. Fractional spur measurement from [27] is shown in Fig. 5. In our study, we focus on the primary fractional spur which occurs atf spur ¼ F f rac f r ¼ 0:27195 40 MHz ¼ 10:88 MHz. The measured fractional spur PSD equals 118 dBc while from direct calculation, it equals 118.7 dBc. The difference is 0.7 dB. To make further validations, ADPLL circuits from [28,29] are also selected, where an architecture-I ADPLL with the 1st order ΔΣ modulator in DCO [28] and an architecture-II ADPLL with the 2nd order ΔΣ modulator in DCO [29] are implemented respectively. The simulation and measurement results are summarized in Table 1. The maximum fractional spur PSD difference between simulation projection and measurement is less than 7.7 dB. 3
ð16Þ
6
H ηTDC ðzÞI ¼
ð18Þ
In architecture-II ADPLL, it is: H ηTDC ðzÞII ¼
GII ½αðz 1Þ þ β z
ðz 1Þ2 þ GII ½αðz 1Þ þ βz
ð19Þ
4.5. Transfer function of the ΔΣ modulator noise
ΔΣ modulator can be deployed not only in divider function block but also in DCO block. When used in divider block, it is to generate fractional divider value. When used in DCO block, it is for DCO dithering. The transfer functions of digital ΔΣ modulator in DCO block H ηDSM ðzÞI and in divider block H ηDSM ðzÞI in architecture-I 1 2 ADPLL can be expressed below: H ηDSM ðzÞI ¼ 1
4. Transfer function of ADPLL
NGI ðαz þ β z αÞ=GT
ðz 1Þ2 þ GI ðαz þ β z αÞ
2 NΔΣ U N U GI ðz 1Þ=GT ðz 1Þ2 þGI ðαz þ βz αÞ 2 NΔΣ =N
ð20Þ
4.1. Transfer function of the reference signal noise
H ηDSM ðzÞI ¼
The transfer function of the reference signal features a low pass filter in ADPLL. For noise frequencies below the loop bandwidth, reference signal noise has a significant effect on the total phase noise. For noise frequencies above the loop bandwidth, the effect of reference signal noise is attenuated. The phase domain transfer function of the reference signal noise of architecture-I and architecture-II ADPLLs are:
Since there is no divider function block in architecture-II ADPLL, the transfer function of ΔΣ modulator in DCO block is:
H ηref ðzÞI ¼
NGI ðαz þ β z αÞ
ðz 1Þ2 þ GI ðαz þ β z αÞ
H ηref ðzÞII ¼
GII ½αðz 1Þ þ βz
ðz 1Þ þ GII ½αðz 1Þ þ β z 2
2
ðz 1Þ þGI ðαz þ βz αÞ
H ηDSM ðzÞII ¼ 1
2
2 NΔΣ K DCO ðz 1Þ ðz 1Þ2 þ GII ½αðz 1Þ þ β z
ð21Þ
ð22Þ
where N ΔΣ is the input bit number of ΔΣ modulator.
ð12Þ
5. ADPLL variable determination
ð13Þ
DLF coefficients are important parameters in ADPLL design. In the literature, there have been considerable researches investigating ADPLL DLF designs [18,19]. Nearly all of them focus on
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accomplishing bandwidth and stability. Few have included phase noise constraint into design considerations. Here, an analytic approach will be developed to determine DLF coefficients by considering more comprehensive performance constraints, basically adding phase noise into design consideration in conjunction with bandwidth and loop stability. Eqs. (12) and (13) are z-domain closed loop transfer functions of architecture-I and architecture-II ADPLLs. Although a discretetime system is naturally described by z-transform, it is common to approximate it with a linear continuous-time system and describe it in the s-domain when PLL bandwidth is much lower than the sampling frequency. In ADPLL design, the sampling frequency equals the reference clock frequency. The loop bandwidth f BW is usually set 10 times lower than the reference signal frequency to ensure system stability with a sufficient phase margin. Therefore, within the bandwidth, when f BW o of r , the bilinear transform can be applied [13]: z ¼ esT r 1 þ sT r
ð23Þ
The s-domain closed loop transfer function of reference signal can be approximated as: 0
H clI ðsÞ ¼ N U
0 2
ðα0 þ β Þf r s þ β f r 0
0 2
s2 þ ðα0 þ β Þf r s þ β f r
ð24Þ
0
where α0 ¼ GL , β ¼ GL β . In architecture-I ADPLL GL ¼ GI , and in architecture-II ADPLL GL ¼ GII . Comparing Eq. (24) with a classic 2nd order s-domain transfer function: HðsÞ ¼ N
2ζωn s þ ω2n s2 þ 2ζωn s þ ω2n
ð25Þ
ωn is natural frequency and ζ is damping ratio. We get: 0
0 2
ðα0 þ β Þf r ¼ 2ζωn ; β f r ¼ ω2n
ð26Þ
The natural frequency and damping ratio can be calculated from Eqs. (27) and (28): qffiffiffiffiffiffiffiffiffi ð27Þ f n ¼ ωn =2π ¼ GL β Uf r =2π
ζ¼
qffiffiffiffiffiffiffiffiffi GL βðα þ β Þ=ð2β Þ
ð28Þ
Locking time T S and loop bandwidth f BW for both architecture-I and architecture-II ADPLLs can be calculated by the following equations [19]: T S ¼ 4=ðωn ζ Þ ¼ 8T r =½GL ðα þ βÞ f BW
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 4 2 ¼ f n ð1 2ζ Þ þ 4ζ 4ζ þ 2
ð29Þ ð30Þ
Assuming the locking time and phase noise constraints are: T S rT L
ð31Þ
0:45 r ζ r 1:5
ð32Þ
5
Sout ð1M Þ r S1M
ð34Þ
Plugging Eqs. (27) and (28) into formulas (31) and (32). Upon manipulations, we have: 8T r =ðGL T L Þ r α þ β 0:45 r
ð35Þ
qffiffiffiffiffiffiffiffiffi GL βðα þ βÞ=ð2β Þ r 1:5
ð36Þ
For demonstration, an architecture-I ADPLL with the following parameters has been simulated: reference clock frequency f r ¼ 13 MHz, feedback divider N ¼ 100:25, TDC resolution τT ¼ 50 ps, the 2nd order MASH DSM with sampling frequency f sΔ ¼ f r is in divider block, dithering resolution bitN DCO ¼ 11, The performance constraints are: K DCO ¼ 100 KHz=LSB. T L r 200 μs, Sf n r 75 dBc=Hz, S1M r 110 dBc=Hz. Table 2 summarizes phase noise of each functional block. Accordingly, the total ADPLL output phase noise can be computed using Eq. (1). Fig. 6 illustrates the relationship between ADPLL locking time and DLF coefficients. According to formula (35), for locking time to be shorter than the design specification, for instanceT L ¼ 200 μs, the DLF coefficients should meet the requirement specified by formula (37). 8T r =½GL ðα þ βÞ r 200 μs ) α þ β Z 0:026
ð37Þ
After substituting ADPLL parameters into formula (36) we have: qffiffiffiffi qffiffiffiffi ð38Þ 2:64 β β r α r 8:82 β β By plugging phase noise performance constraints, phase noise of equations in Table 2 and close loop transfer functions of each noise source into formulas (33) and (34), we can derive: 1:7 U β þ 1:1 þ 87β ½0:12β ðβ þ 2αÞ þ β þ α pffiffiffiffi pffiffiffiffi r 3:16 105 0:34 β ½0:12ðα þ β Þ þ 2 cos ð0:34 β Þ 22
ð39Þ
3:25α2 þ14:12β þ0:24α þ 2:06β þ 0:07αβ r 1
ð40Þ
1=2
3=2
2
Based on formulas (37)–(40), we can plot the boundary condition lines in Fig. 7. The shadow area specifies the possible DLF
Table 2 Phase noise of each functional unit. REF
11:2
Sr ðf Þ ¼ 10 15 þ 10 f
9:4
f
ST ¼ 1:075 10
DCO
SDQ N ¼ 1:53 10 15 2
SDCO ðf Þ ¼ 100:33 =f þ 106 =f
Ref. [24]
f
9
PFD
DSM
7:0
þ 10 2 þ 10 3
Eq. (7) Eq. (3) 3
SDS ¼ π 2 ½2 sin ðπf =f sΔ Þ2 =3ðf sΔ Þ
Ref. [26] Eq. (4)
where T L is locking time constrain. Regarding the phase noise, it is usually evaluated at a selected frequency offset (i.e. 1 MHz) from the central frequency. Additionally, for an under damped ðζ o 1Þ PLL system, its closed loop transfer function has a peak value at the natural frequency, which will lead to an increased phase noise at this particular frequency point. Therefore, in the design analysis, we choose to characterize ADPLL output phase noise at frequency points f n and 1 MHz offset respectively for phase noise constraint characterizations. The output phase noise constraints are: phase noise at natural frequency Sout ðf n Þ and 1 MHz Sout ð1M Þ not exceeding Sf n and S1M , respectively. Sout ðf n Þ rSf n
ð33Þ
Fig. 6. ADPLL locking time with different DLF coefficients.
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coefficient values for α and β that can meet all the requirements including locking time, phase noise and system stability. Fig. 8 plots ADPLL output phase noise with different DLF coefficients. As illustrated, when α ¼ 2 1 and β ¼ 2 5 , the maximum in band phase noise is 89 dBc=Hz, the phase noise at 1 MHz frequency offset is 110 dBc=Hz. Accordingly, the locking time is calculated to be 9:8 μs. When α ¼ 2 2 and β ¼ 2 7 , the maximum in band phase noise is 82 dBc=Hz, the phase noise at 1 MHz frequency offset is 111 dBc=Hz and the locking time is 20:2 μs. Apparently, there is a trade off among ADPLL locking time, maximum in band phase noise and phase noise at specific frequency offset (i.e. frequency offset at 1 MHz). Lower phase noise requires smaller DLF coefficients, while faster locking speed needs larger DLF coefficients. In another word, to obtain lower phase noise, DLF coefficients should be selected from the lower left corner of the shadow area in Fig. 7. While to achieve a faster locking speed, DLF coefficients should be selected from the upper right corner of shadow area in Fig. 7. Therefore, it is important to set proper DLF coefficient values to achieve performance balance. DCO resolution is determined by last significant bit of DCO input control code. The limited frequency resolution leads to DCO quantization noise. We have to consider the DCO resolution when DCO quantization noise is comparable to DCO oscillator noise. We use NDCO ¼ 6, K DCO ¼ 100 KHz=LSB in above case study. DCO quantization noise of DCO is 151 dBc which is at least 12 dB smaller than DCO oscillator noise at frequency offset range from 1 KHz to 5 MHz. Hence, the quantization noise of DCO in this case study can be neglected.
6. Case study In order to verify the developed analytical model, we select ADPLLs in references [28,29] as study cases. We develop models based on ADPLL topology presented in these papers and perform noise simulations. By comparing simulation results and measurement data provided in the original manuscripts, we are able to evaluate the proposed phase noise model effectiveness.
6.1. Architecture-I ADPLL In [28], a 1.5 GHz ADPLL is developed. The loop bandwidth is 20 KHz. Other parameters are listed as follows: reference signal frequency f r is 45 MHz. Output frequency is 1.5 GHz. Divider ratio N is 33.3333. K DCO equals 577 Hz/LSB. TDC resolution equals 10 ps. The order number of ΔΣ modulators in DCO block is 1, respectively. The sampling frequency of those two ΔΣ modulators are f sΔ ¼ 0:75 GHz. The DLF coefficients α ¼ 22 and β ¼ 2 6 are computed from loop bandwidth and phase margin. A 45 MHz crystal oscillator [31] phase noise equals: Sr ðf Þ ¼ 10 16:1 þ 10 10:2 =f þ 10 7:6 =f þ 10 6:1 =f 2
3
The free running 1.5 GHz DCO oscillator phase noise in [28] is approximated as: SDCO ðf Þ ¼ 10 15:5 þ 10 8:2 =f þ 10 4:2 =f þ 100:9 =f 2
3
By using the analytical modeling method developed in proceeding sections, we are able to characterize the noise contributions of different noise sources as shown in Fig. 9. As can be seen clearly, the in-band phase noise is mainly contributed by noises in reference clock and PFD function block. In out-of-band frequency range, the total phase noise is mainly affected by the noises in PFD, DCO and ΔΣ modulator. The primary fractional spur occurs at offset frequency f spur ¼ F f rac f r ¼ 15 MHz. From Eq. (14), rollof f ðf spur Þ is calculated to be 48:5 dB. The primary fractional spur PSD equals: " # ð21 1Þ U577 Sspur ¼ 20 log 48:5 dB ¼ 142:8 dBc 2 15 MHz
Fig. 7. DLF coefficients determination.
For validation, we obtain ADPLL circuit hardware measurement results. The difference between the simulated and measured total phase noise at different frequency points are listed in Table 3. It shows that our model simulation achieves good agreement with hardware results.
Fig. 8. Output phase noise with different DLF coefficients.
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oscillators in references [31,32].
6.2. Architecture-II ADPLL
Sr ðf Þ ¼ 10 14:7 þ 10 10:3 =f þ 10 8:3 =f þ 10 4:8 =f 2
In [29], a 4.9–6.9 GHz fractional-N ADPLL for radio telecommunication is presented. The loop bandwidth is 200 KHz. Other important parameters are: reference clock frequency f r ¼ 48 MHz, output frequency is 5.376021831 GHz, FCW is 112.0004548125. K DCO ¼ 26 kHz, TDC-PD resolution τT ¼ 15 ps, TDC output bit-width is 9 and the 2nd order MASH ΔΣ modulator in DCO block with sampling frequency f sΔ ¼ f r is employed. There is an extra 9-bit fine tuning code in DCO block. The DLF coefficients are α ¼ 2 5 and β ¼ 2 10 . Phase noise PSD of the 48 MHz reference clock and LC-tank DCO at 5.3 GHz output are approximated as follows, which are in agreements with the similar
Table 3 Output phase noise differences between simulation and measurement at some typical frequencies. Phase noise (dBc/Hz) at frequency offset
SPUR
10 K Hz
Freq. (Hz) PSD
100 K Hz
1 M Hz
10 M Hz
Simu. 92.4 124.7 140.4 150.1 15M Meas 96.3 124.8 141.5 149.5 15M Error 3.9 dB 0.1 dB 1.1 dB 0.6 dB 0
142.8 dBc 142.5 dBc 0.3 dB
SDCO ðf Þ ¼ 10 13:8 þ 10 0:2 =f
3
2
From our model analysis, the contribution of each noise to the total output phase noise is plotted in Fig. 10. The in-band phase noise is mainly contributed by the reference clock noise and TDCPD noise. In high noise frequency range, the total noise is affected by the noises of TDC-PD, DCO and ΔΣ modulator. The primary fractional spur occurs at the offset frequency f spur ¼ F f rac f r ¼ 21:8 KHz. Since the fractional spur locates within loop bandwidth, the rollof f ðf spur Þ equals 0 dB. The primary fractional spur PSD equals Sspur ¼ 20 log
! ð22 1Þ U 26 kHz=29 þ 0 dB ¼ 49:1 dBc 2 21:8 kHz
The difference between the simulated and measured total phase noise at different frequency points are listed in Table 4. Also, the simulation results from proposed model show good agreement with hardware results. In the presented phase noise model, other noise sources such as power supply noise and thermal noise are not considered, which is the major cause of the deviation between the simulation results and the measurement results. Those noises heavily depend
Fig. 9. Simulated phase noise of each noise source and total phase noise at 1.5 GHz output frequency.
Fig. 10. Simulated phase noise of each noise source and total phase noise at 5.376021831 GHz output frequency.
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Table 4 Output phase noise differences between simulation and measurement at some typical frequencies. Phase Noise (dBc/Hz) at frequency offset
Simu. Meas Error
SPUR
10 K Hz
100 K Hz
1 M Hz
10 M Hz Freq. (Hz) PSD
95.2 96.9 1.7 dB
92.1 90.7 1.4 dB
116.7 116.4 0.3 dB
134 137 3dB
21.8K 20K 1.8K
49.1 dBc 45dBc 4.1 dB
on the operating conditions of the system that ADPLL is embedded in, such as the on-chip power grid signal integrity etc., whose noise characterizations are not available in the work presented in this paper. Actually, if these noise data are provided, their effects on ADPLL output phase noise can also be projected. 7. Conclusion This paper develops an analytic noise model for both architecture-I and architecture-II ADPLLs. By analyzing fractional spur, noise contribution and transfer function of each function block, the total phase noise and fractional spur can be projected. The total phase noise and primary fractional spur between simulation results and measurement data collected show reasonable agreements. Furthermore, we plot boundary condition lines according to phase noise, locking time and damping ratio constrains in order to determine proper DLF coefficients. This analysis method can effectively project phase noise and fractional spur and can be used as design guidance for ADPLL variables determination and optimization. References [1] J. Segundo, L. Quintanilla, J. Arias, L. Enriquez, J.M. Hernandez, J. Vicente, A PLLbased synthesizer for tunable digital clock generation in a continuous-time ΣΔ A/D converter, Integr. VLSI J. 42 (1) (2009) 24–33. [2] R.B. Staszewski, et al., All-digital PLL and transmitter for mobile phones, IEEE J. Solid-State Circuits 40 (12) (2005) 2469–2482. [3] M.E. Heidari Minjae Lee, A.A. Abidi, A. Low-Noise Wideband, Digital Phaselocked loop based on a coarseCFine time-to-digital converter with subpicosecond resolution, IEEE J. Solid-State Circuits 44 (10) (2009) 2809–2816. [4] M.E.S. Elrabaa, A portable high-frequency digitally controlled oscillator (DCO), Integr. VLSI J. (2013). [5] M.H. Perrott, M.D. Trott, C.G. Sodini, A modeling approach for fractional-N frequency synthesizers allowing straightforward noise analysis, IEEE J. SolidState Circuits 37 (2002) 1028–1038. [6] B. Jiang, T. Xia, G. Wang, PLL low pass filter design considering unified specification constraints, Analog Integr. Circuits Signal Process. (2014) 1–8. [7] F. Herzel, S.A. Osmany, J.C. Scheytt, Analytical phase-noise modeling and charge pump optimization for fractional-N PLLs, IEEE Trans. Circuits Syst. I: Regul. Pap. 57 (2010) 1914–1924 (Aug.). [8] A. Hajimiri, S. Limotyrakis, T.H. Lee, Jitter and phase noise in ring oscillators, IEEE J. Solid-State Circuits 34 (6) (1999) 790–804. [9] T. Xia, Analytical model for spread-spectrum clock generator circuit characterization, Int. J. Circuit Theory Appl. (2010). [10] Nicola Da Dalt, A. Design-Oriented, Study of the nonlinear dynamics of digital bang–bang PLLs, IEEE Trans. Circuits Syst.-I: Regul. Pap. 52 (1) (2005) 21–31 (Jan.). [11] R.B. Staszewski, D. Leipold, Chih-Ming Hung, P.T. Balsara, TDC-based frequency synthesizer for wireless applications, in: Proceedings of IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, August 2004, pp. 215–218. [12] R.B. Staszewski, P.T. Balsara, Phase-Domain All-Digital Phase-Locked Loop, in: Proceedings of IEEE Transactions on Circuits and Systems-II: Express Briefs, 52, 3, March 2005, pp. 159–163. [13] S. Mendel, C. Vogel, A z-domain model and analysis of phase-domain alldigital phase-locked loops, Norchip (2007) 1–6. [14] Ioannis L. Syllaios, Poras T. Balsara, R.B. Staszewski, Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications, in: Proceedings of IEEE Custom Intergrated Circuits Conference (CICC), 2007, pp. 861–864. [15] Ioannis L. Syllaios, Robert Bogdan Staszewski, Poras T. Balsara, Time-Domain Modeling of an RF All-Digital PLL, in: Proceedings of IEEE Transactions on Circuits and Systems-II: Express Briefs, 55, 6, June 2008, pp. 601–605.
[16] Ioannis L. Syllaios, Poras T. Balsara, Multi-clock domain analysis and modeling of all-digital frequency synthesizers, IEEE Int. Symp. Circuits Syst. (ISCAS) (2011) 153–156. [17] Ioannis L. Syllaios, Poras T. Balsara, Linear time-variant modeling and analysis of all-digital phase-locked loops, IEEE Trans. Circuits Syst.-I: Regul. Pap. 59 (11) (2012) 2495–2506. [18] V. Kratyuk, P.K. Hanumolu, Un-Ku Moon K. Mayaram, A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy, IEEE Trans. Circuits Syst. II: Express Briefs 54 (2007) 1–6. [19] Jason Meiners Wen Li, Introduction to phase-locked loop system modeling, Texas Instrum. Inc. Analog Appl. J. (2000) 5–11. [20] B. Jiang, T. Xia, ADPLL variables determinations based on phase noise, spur and locking time, in: Proceedings of IEEE System-on-Chip Conference, Sep. 2012, pp. 39–44. [21] Marco Zanuso Paolo Madoglio, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita, Quantization Effects in All-Digital Phase-Locked Loops, IEEE Trans. Circuits Syst.-II: Express Briefs 54 (12) (2007) 1120–1124. [22] R.B. Staszewski, C. Hung, N. Barton, M. Lee, D. Leipold, A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones, IEEE J. SolidState Circuits 40 (11) (2005) 2203–2211. [23] M. Erturk, T. Xia, R. Anna, K.M. Newton, E. Adler, Statistical BSIM model for MOSFET 1/f noise, Electronics Letters 41 (22) (2005) 1208–1210. [24] Phase Noise/Jitter In Crystal Oscillators, Rakon, 2009. [25] Dram De Muer, Michiel S.J. Steyaert, On the analysis of ΔΣ fractional-N frequency synthesizers for high-spectral purity, IEEE Trans. Cricuits Syst.-II: Analog Digit. Signal Process. 50 (2003) 784–793. [26] A. Italia, C.M. Ippolito, G. Palmisano, A 1-mW 1.13-1.9 GHz CMOS LC VCO using shunt-connected switched-coupled inductors, IEEE Trans. Circuits Syst. I: Regul. Pap. 59 (2012) 1145–1155. [27] D. Tasca, M. Zanuso, G. Marzin, S. Levantino, C. Samori, A.L. Lacaita, A 2.9-4.0 GHz fractional-N digital PLL with bang-bang phase detector and 560-fsrms integrated jitter at 4.5-mW power, IEEE J. Solid-State Circuits 46 (12) (2011) 2745–2758. [28] Julie R. Hu, Richard C. Rubyy, Brian P. Otis, A 1.5 GHz 0.2psRMSJitter 1.5 mW Divider-less FBAR ADPLL in 65 nm CMOS, IEEE Cust. Integr. Circuits Conf. (CICC) (2012) 1–4. [29] N. Pavlovic, J. Bergervoet, A 5.3 GHz digital-to-time-converter-based fractional-N all-digital PLL, in: Proceedings of IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011, pp. 54–56. [31] WF5028 series 0.8 V operation Crystal Oscillator Mudule ICs, Seiko NPC Corporation. Jan. 2008. [32] Yuan-Kai Wu, Cheng-Chen Liu, Jhin-Fang Huang, A dual-band CMOS voltagecontrolled oscillator implemented with dual-resonance LC tank, IEEE Microw. Wirel.Compon. Lett. 19 (2009) 816–818. [33] Steve Williams and Tony Caviglia, Simulating PLL reference spurs, in: 〈www. rfdesing.com〉, Mar, 2006.
Bo Jiang was born in Hangzhou, P.R. China. He received the B.S. and M.S. degrees in Electrical Engineering from Xi’an University of Technology and Xi’an Jiaotong University, Xi’an, P.R. China, in 2003 and 2006, respectively. He is currently working toward the Ph.D. degree in Electrical Engineering at the University of Vermont. His research interests include low noise phase locked loop (PLL) and all digital PLL frequency synthesizer circuit design and modeling.
Tian Xia received the B.E. degree in Electrical Engineering from the Huazhong University of Science and Technology, Wuhan, China, in 1994, the M.S. degree from the Nanjing University of Posts and Telecom munications, Nanjing, China, in 2000, and the Ph.D. degree in Electrical and Computer Engineering from the University of Rhode Island, Kingston, U.S., in 2003. During the summers of 2002 and 2003, he did his internship in IBM T.J. Watson Research Center, Yorktown Heights, NY. He is now an Associate Professor with the School of Engineering at the University of Vermont. His current research interests are in mixedsignal and RF circuit design and test. He is the recipient of the Best Paper Award of IEEE North Atlantic Test Workshop (NATW) 2005, the Best Paper Award of IEEE System on Chip Conference (SOCC) 2012. Dr. Xia received IBM Faculty Awards in 2005, 2006 and 2008. He was the program chair of IEEE North Atlantic Test Workshop 2011, 2012, 2013, 2014; Guest editor of Journal of Electronic Test: Theory and Application (JETTA) 2013, and has been the Associate Editor of Journal of Circuits, Systems, and Computers (JCSC) since 2013.
Please cite this article as: B. Jiang, T. Xia, ADPLL design parameters determinations through noise modeling, INTEGRATION, the VLSI journal (2014), http://dx.doi.org/10.1016/j.vlsi.2014.08.001i
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INTEGRATION, the VLSI journal journal homepage: www.elsevier.com/locate/vlsi
ADPLL design parameters determinations through noise modeling Bo Jiang, Tian Xia n University of Vermont, Burlington, VT 05405, USA
ar t ic l e i nf o
a b s t r a c t
Article history: Received 7 June 2014 Accepted 15 August 2014
This paper presents a methodology to determine all-digital phase-locked loop (ADPLL) circuit variables based on required design specifications, including output phase noise, fractional spur and locking time. An analytical model is developed to characterize the effects of different noise sources on ADPLL output phase noise and fractional spur. Applying the proposed noise model, circuit variables in ADPLL can be properly selected to meet phase noise, fractional spur and locking time requirements. For model validation, we collect ADPLL circuit designs published in recent literatures and perform model analysis. The analysis results and hardware measurements obtain good agreements. & 2014 Elsevier B.V. All rights reserved.
Keywords: ADPLL Phase noise Spur Fractional-N PLL Digitally controlled oscillator Frequency divider Phase–frequency detector
1. Introduction ADPLL is recently emerging to replace analog charge pump PLL [1] in many RF transceivers on account of its superior features including programmability, high noise immunity, small area, low voltage and ease of integration [2–4]. Generally, there are two main ADPLL architectures as shown in Fig. 1. Comparing with analog charge pump PLL, architecture-I ADPLL in Fig. 1(a) replaces the standard phase frequency detector (PFD), charge pump with a time-to-digital converter (TDC) based PFD that quantities the phase difference between reference clock and the feedback signal. The resulting phase difference is fed into the digital loop filter (DLF) instead of the analog filter to eliminate the high frequency noise. A programmable divider with ΔΣ modulator is used in the feedback path to set up the fractional divide ratio. In architectureII ADPLL, as shown in Fig. 1(b), the phase detector (PD) is designed by combining a counter and a TDC for comparing the difference between reference clock frequency control word (FCW) and the feedback frequency control word without a frequency divider in the feedback path. Like in an analog PLL, phase noise, spur and locking time are key characteristics of ADPLL frequency synthesizer. In the literature, there are numerous studies analyzing analog PLLs [5–10]. However, due to its unique architecture, there are new variables in ADPLL that must be carefully configured in order to meet performance requirements. These variables include TDC resolution, bit-width of
n
Corresponding author. Tel.: +1 802 656 8996. E-mail address: [email protected] (T. Xia).
different digital units, DLF coefficients and digitally controlled oscillator (DCO) resolution. In an ADPLL, besides oscillator noise, on account of the limited bit-width of different digital units, quantization noise is the major noise that may deteriorate performance. Therefore, the traditional analog PLL's analytic model cannot be applied directly for ADPLL design characterizations. Currently, there are limited researches dedicated to analyzing the relationship between performance and circuit variables that are applicable to both architectures of ADPLLs. In [11], TDC noise and DCO noise are analyzed for architecture-II ADPLL. In [12], authors present a zdomain model of architecture-II ADPLL without noise analysis. In [13], authors develop a z-domain model for analyzing DCO noise and TDC noise for architecture-II ADPLL. In [14–16], authors develop time domain models for ADPLL. In [17], authors propose a linear discrete time multi-rate model for ADPLL. However, the study of circuit variables and performance that are applicable for both architecture-I and architecture-II ADPLLs is lacking. Moreover, these analytical do provide guidance in determining variables based on performance constraints. ADPLL frequency synthesizer's phase noise and locking time are important performance parameters. When used in a communication system, low quality phase noise will reduce the effective signal to noise ratio, cause large bit error and bring down data rate. Therefore, it is important to investigate the relationship between ADPLL variables and phase noise and locking time performances. In [18], authors present a method to calculate the DLF variables according to bandwidth and phase margin. In [19], DLF coefficients are determined by loop bandwidth and damping ratio. However, no design procedure for determining ADPLL variables based on the phase noise specification is provided in these publications. In this
http://dx.doi.org/10.1016/j.vlsi.2014.08.001 0167-9260/& 2014 Elsevier B.V. All rights reserved.
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paper, we extend our research in [20] to provide a design procedure for determining ADPLL DLF coefficients based on phase noise, locking time, bandwidth and damping ratio. This paper is organized as follows. Section 2 introduces noise model of ADPLL. Section 3 analyzes the fractional spur. Section 4 derives the closed loop transfer function of each noise source. Section 5 presents the method to determine the variables values considering performance constraints. Case studies are demonstrated in Section 6 to verify the proposed model. Section 7 contains the concluding remarks.
2. Phase noise model of ADPLL In order to evaluate phase noise, fractional spur and locking time, an ADPLL behavior model is developed. There are s-domain model and the z-domain model for architecture-II ADPLL presented in [11,13], respectively. In this paper, comprehensive analytical models of both architecture-I and architecture-II ADPLL as shown in Fig. 2, will be developed. In both architectures, there are five dominant noise sources, which are input reference clock noise ηref , TDC noise ηTDC , DCO oscillator noise ηDCO , DCO quantization noise ηDQ N and delta sigma modulator noise ηDSM . Generally, dominant noise in ADPLLs can be
categorized as oscillator noise and quantization noise. Reference oscillator contributes oscillator noise. DCO noise is composed of oscillator noise and quantization noise. TDC quantization noise caused by limited TDC resolution is the dominant noise source in PFD block. DCO quantization noise is caused by the limited bit number of DCO control bits. ΔΣ modulator also generates quantization noise for its limited output bit width. ADPLL output signal phase noise can be characterized from all noise sources. Sout ðf Þ ¼ ∑Si ðf Þ UjH i ðzÞj2
ð1Þ
where Si ðf Þ and H i ðzÞ represent the noise spectrum density and the corresponding closed loop transfer function of each noise in ADPLL. Below, each noise source will be analyzed. 2.1. Reference clock noise Reference clock noise is categorized as the oscillator noise. Its phase noise power spectrum density Sr ðf Þcan be described using oscillator phase noise model [16]: 2
SOSC ðf Þ ¼ k0 þk1 =f þ k2 =f þ k3 =f 2
3
ð2Þ
3
where k0 , k1 =f , k2 =f , and k3 =f represent thermal noise, flicker noise [23], carrier noise and inter-modulation of both carrier and transistor noise, respectively. 2.2. DCO quantization noise DCO noise is composed of oscillator noise and quantization noise [21,22]. The DCO oscillator noise SDCO ðf Þ can be described using Eq. (2). The DCO quantization noise is determined by the bit number of DCO control code. When DCO dithering resolution bit is NDCO , DCO quantization noise σ 2DQ N equalsð2 NDCO Þ2 =12. The PSD equals: SDQ N ¼
1 12 Uð2NDCO Þ2 U f r
ð3Þ
where f r is reference signal frequency and K DCO is DCO gain. 2.3. Delta sigma modulator noise
Fig. 1. ADPLL architecture. (a) Architecture-I, and (b) Architecture-II.
The multi-stage noise shaping (MASH) ΔΣ modulator is widely used in fractional-N ADPLLs. The quantization noise contributed by ΔΣ modulator is treated as an additive noise source [25]. For a ΔΣ modulator with transfer functionHΔΣ ðzÞ, the PSD of phase fluctuations equalsπ 2 jH ΔΣ ðzÞj2 =ð3f sΔ j1 z 1 j2 Þ. f sΔ is the sampling frequency of ΔΣ modulator. The z-domain transfer function of an mth-order MASH ΔΣ modulator isH ΔΣ ðzÞ ¼ ð1 z 1 Þm . The
Fig. 2. The z-domain phase noise model of phase-domain ADPLL. (a) Architecture-I ADPLL. (b) Architecture-II ADPLL.
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quantization noise spectrum density is deduced as [25]: SDS ðf Þ ¼ π 2 ½2 sin ðπ f =f sΔ Þ2ðm 1Þ =ð3f sΔ Þ
3. ADPLL fractional spur ð4Þ
2.4. TDC-PFD noise TDC quantization noise is the dominant noise source in phase detector. Fig. 3 shows a widely used N-bit TDC, where the input phase error goes through a delay chain. Flip-flops are connected to the outputs of inverters and sample the state of the delay chain. By using an edge detector and an encoder, the phase difference is converted to digital codes. TDC's resolution equals single inverter delayτT . For ADPLL, the gain of TDC GT is the ratio of TDC output code and input phase difference between the reference clock and the feedback signal. GT ¼ 1=ð2πτT f r Þ
ð5Þ
where f r is the reference signal frequency. For a BT -bit TDC, the maximum phase detection range is: P max ¼ ð2BT 1Þ=GT
ð6Þ
The standard deviation of TDC quantization noise σ 2TDC equalsτ2T =12. Normalizing σ TDC by ADPLL output signal period T out and converting it to phase in radians results in σ TDC ϕ ¼ 2πσ TDC =T out . Thus the TDC quantization noise PSD equals [11]: ST ¼
σ 2TDC ϕ fr
¼
ð2πσ TDC Þ f r T 2out
2
ðπτT f out Þ 3f r
2
¼
3
ð7Þ
where f out is ADPLL output signal frequency. From this equation, it is clear that ST can be reduced by increasing TDC resolution with a smallerτT . For instance, for a given f r and f DCO to f r ratioN, reducing τT by half will reduce ST by 3 dB.
2.5. Digital low pass filter analysis In ADPLL designs, proportional plus integral (PPI) filter as shown in Fig. 4 is widely adopted. The transfer function of PPI filter is H DF ðzÞ ¼ α þ β=ð1 z 1 Þ. Comparing with charge pump PLL, ADPLL can adjust its loop bandwidth by tuning the digital loop filter coefficients easily. For the low pass filter in an analog PLL, the filter circuit noise is mainly caused by electrical elements' thermal noise. However, in ADPLL digital low pass filter, the quantization noise is the dominant noise source. The DLF output connects to DCO, whose output has the same bit-width as that of DCO control word.
Spurious level of ADPLL output is another important parameter. In fractional-N ADPLL, one important spur specification is the fractional spur. The digital ΔΣ modulator is the fundamental source of fractional spurious tones in fractional-N ADPLL while the limited TDC output bit-width can further increase fractional spur level. For an mth-order MASH DSM applied in ADPLL, at locking state, the phase difference varies from ð2m 2Þπ =N to 2m π =N. In order to minimize the fractional spur level, TDC output should cover the phase difference range, thus: P max Z
ð2m þ 1 2Þπ 2m 1 ) 2BT 1 Z N N U f r U τT
ð8Þ
The primary frequency of the fractional spur isf spur ¼ F f rac f r . F f rac represents the fractional part of divider value N. The PSD of fractional spur in dB can be deduced as [33]: ! Δf max þ rollof f ðf spur Þ Sspur ¼ 20 log 2f spur ! ΔC max U K DCO þ rollof f ðf spur Þ ð9Þ ¼ 20 log 2f spur where ΔC max is the maximum control code variation and rollof f ðf Þ is defined as the magnitude of the closed loop transfer function of reference signal subtracting the factor of 20 log N. rollof f ðf Þ ¼ 20 log ðjH cl ðzÞjz ¼ ej2πf T r Þ 20 log N
ð10Þ
It is clear that ΔC max ¼ 2 1 when ΔΣ modulator is located in DCO function block. For ADPLL with ΔΣ modulator only existing in divider block, the maximum phase variation ϕdr at locking state equals 2π ð2m 1Þf r =f out . Thus ΔC max equals: m
ΔC max ¼ ϕdr GT ðα þ βÞ ¼ 2π f r GT ðα þ βÞð2m 1Þ=f out
ð11Þ
In order to verify Eq. (9), we compare the fractional spur PSD calculated from Eq. (9) and from measurement in [27]. The ADPLL in [27] is an architecture-I APDLL with a 1st order and a 2ndorder ΔΣ modulators in divider and DCO block, respectively. Its parameters are include: reference signal frequency equals 40 MHz, TDC resolution τT ¼ 1 ps, DCO gain K DCO ¼ 2 KHz=LSB, divider value
Fig. 4. z-domain of proportional plus integral filter.
Fig. 3. Traditional N-bit TDC in ADPLL.
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where GI ¼ 2π GT K DCO T ref =N, GII ¼ 2π GT K DCO T ref =FCW,T ref is reference clock period. 4.2. Transfer function of DCO oscillator noise Fig. 2 shows that, the transfer function of DCO features a high pass filter. The phase domain transfer function of DCO oscillator noise in each architecture can be expressed as: H ηDCO ðzÞI ¼
ðz 1Þ2 ðz 1Þ þGI ðαz þ β z αÞ 2
ðz 1Þ2
H ηDCO ðzÞII ¼
ðz 1Þ þGII ½αðz 1Þ þ β z 2
ð14Þ
ð15Þ
Fig. 5. Fractional spur of ADPLL in [27].
4.3. Transfer function of the DCO quantization noise
Table 1 Output phase noise differences between simulation and measurement at some typical frequencies. Fractional Spur
Output ADPLL Arch. frequency (GHz)
Prim. Prim. PSD (dBc) Freq. (Hz)
In architecture-I ADPLL, the transfer function of the DCO quantization noise in phase domain equals: H ηDQ N ðzÞI ¼
NGI ðz 1Þ=GT ðz 1Þ2 þ GI ðαz þ βz αÞ
In architecture-II ADPLL, it is: H ηDQ N ðzÞII ¼
Ref. [27] Simu. 10.88 M 118.7 Meas. 10M 118 Ref. [28] Simu. 15M 145.8 Meas. 15M 142.5 Ref. [29] Simu. 21.8 K 52.7 Meas. 20K 45
3.610878
I
1.5
I
5.37602183
II
T r K DCO ðz 1Þ ðz 1Þ2 þ GII ½αðz 1Þ þ βz
ð17Þ
4.4. Transfer function of the TDC noise Here, the phase domain transfer function of the TDC noise in architecture-I ADPLL is derived as:
N ¼ 90:27195, DLF coefficients α ¼ 2 and β ¼ 2 . The bandwidth of the PLL is 500 KHz. Fractional spur measurement from [27] is shown in Fig. 5. In our study, we focus on the primary fractional spur which occurs atf spur ¼ F f rac f r ¼ 0:27195 40 MHz ¼ 10:88 MHz. The measured fractional spur PSD equals 118 dBc while from direct calculation, it equals 118.7 dBc. The difference is 0.7 dB. To make further validations, ADPLL circuits from [28,29] are also selected, where an architecture-I ADPLL with the 1st order ΔΣ modulator in DCO [28] and an architecture-II ADPLL with the 2nd order ΔΣ modulator in DCO [29] are implemented respectively. The simulation and measurement results are summarized in Table 1. The maximum fractional spur PSD difference between simulation projection and measurement is less than 7.7 dB. 3
ð16Þ
6
H ηTDC ðzÞI ¼
ð18Þ
In architecture-II ADPLL, it is: H ηTDC ðzÞII ¼
GII ½αðz 1Þ þ β z
ðz 1Þ2 þ GII ½αðz 1Þ þ βz
ð19Þ
4.5. Transfer function of the ΔΣ modulator noise
ΔΣ modulator can be deployed not only in divider function block but also in DCO block. When used in divider block, it is to generate fractional divider value. When used in DCO block, it is for DCO dithering. The transfer functions of digital ΔΣ modulator in DCO block H ηDSM ðzÞI and in divider block H ηDSM ðzÞI in architecture-I 1 2 ADPLL can be expressed below: H ηDSM ðzÞI ¼ 1
4. Transfer function of ADPLL
NGI ðαz þ β z αÞ=GT
ðz 1Þ2 þ GI ðαz þ β z αÞ
2 NΔΣ U N U GI ðz 1Þ=GT ðz 1Þ2 þGI ðαz þ βz αÞ 2 NΔΣ =N
ð20Þ
4.1. Transfer function of the reference signal noise
H ηDSM ðzÞI ¼
The transfer function of the reference signal features a low pass filter in ADPLL. For noise frequencies below the loop bandwidth, reference signal noise has a significant effect on the total phase noise. For noise frequencies above the loop bandwidth, the effect of reference signal noise is attenuated. The phase domain transfer function of the reference signal noise of architecture-I and architecture-II ADPLLs are:
Since there is no divider function block in architecture-II ADPLL, the transfer function of ΔΣ modulator in DCO block is:
H ηref ðzÞI ¼
NGI ðαz þ β z αÞ
ðz 1Þ2 þ GI ðαz þ β z αÞ
H ηref ðzÞII ¼
GII ½αðz 1Þ þ βz
ðz 1Þ þ GII ½αðz 1Þ þ β z 2
2
ðz 1Þ þGI ðαz þ βz αÞ
H ηDSM ðzÞII ¼ 1
2
2 NΔΣ K DCO ðz 1Þ ðz 1Þ2 þ GII ½αðz 1Þ þ β z
ð21Þ
ð22Þ
where N ΔΣ is the input bit number of ΔΣ modulator.
ð12Þ
5. ADPLL variable determination
ð13Þ
DLF coefficients are important parameters in ADPLL design. In the literature, there have been considerable researches investigating ADPLL DLF designs [18,19]. Nearly all of them focus on
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accomplishing bandwidth and stability. Few have included phase noise constraint into design considerations. Here, an analytic approach will be developed to determine DLF coefficients by considering more comprehensive performance constraints, basically adding phase noise into design consideration in conjunction with bandwidth and loop stability. Eqs. (12) and (13) are z-domain closed loop transfer functions of architecture-I and architecture-II ADPLLs. Although a discretetime system is naturally described by z-transform, it is common to approximate it with a linear continuous-time system and describe it in the s-domain when PLL bandwidth is much lower than the sampling frequency. In ADPLL design, the sampling frequency equals the reference clock frequency. The loop bandwidth f BW is usually set 10 times lower than the reference signal frequency to ensure system stability with a sufficient phase margin. Therefore, within the bandwidth, when f BW o of r , the bilinear transform can be applied [13]: z ¼ esT r 1 þ sT r
ð23Þ
The s-domain closed loop transfer function of reference signal can be approximated as: 0
H clI ðsÞ ¼ N U
0 2
ðα0 þ β Þf r s þ β f r 0
0 2
s2 þ ðα0 þ β Þf r s þ β f r
ð24Þ
0
where α0 ¼ GL , β ¼ GL β . In architecture-I ADPLL GL ¼ GI , and in architecture-II ADPLL GL ¼ GII . Comparing Eq. (24) with a classic 2nd order s-domain transfer function: HðsÞ ¼ N
2ζωn s þ ω2n s2 þ 2ζωn s þ ω2n
ð25Þ
ωn is natural frequency and ζ is damping ratio. We get: 0
0 2
ðα0 þ β Þf r ¼ 2ζωn ; β f r ¼ ω2n
ð26Þ
The natural frequency and damping ratio can be calculated from Eqs. (27) and (28): qffiffiffiffiffiffiffiffiffi ð27Þ f n ¼ ωn =2π ¼ GL β Uf r =2π
ζ¼
qffiffiffiffiffiffiffiffiffi GL βðα þ β Þ=ð2β Þ
ð28Þ
Locking time T S and loop bandwidth f BW for both architecture-I and architecture-II ADPLLs can be calculated by the following equations [19]: T S ¼ 4=ðωn ζ Þ ¼ 8T r =½GL ðα þ βÞ f BW
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 4 2 ¼ f n ð1 2ζ Þ þ 4ζ 4ζ þ 2
ð29Þ ð30Þ
Assuming the locking time and phase noise constraints are: T S rT L
ð31Þ
0:45 r ζ r 1:5
ð32Þ
5
Sout ð1M Þ r S1M
ð34Þ
Plugging Eqs. (27) and (28) into formulas (31) and (32). Upon manipulations, we have: 8T r =ðGL T L Þ r α þ β 0:45 r
ð35Þ
qffiffiffiffiffiffiffiffiffi GL βðα þ βÞ=ð2β Þ r 1:5
ð36Þ
For demonstration, an architecture-I ADPLL with the following parameters has been simulated: reference clock frequency f r ¼ 13 MHz, feedback divider N ¼ 100:25, TDC resolution τT ¼ 50 ps, the 2nd order MASH DSM with sampling frequency f sΔ ¼ f r is in divider block, dithering resolution bitN DCO ¼ 11, The performance constraints are: K DCO ¼ 100 KHz=LSB. T L r 200 μs, Sf n r 75 dBc=Hz, S1M r 110 dBc=Hz. Table 2 summarizes phase noise of each functional block. Accordingly, the total ADPLL output phase noise can be computed using Eq. (1). Fig. 6 illustrates the relationship between ADPLL locking time and DLF coefficients. According to formula (35), for locking time to be shorter than the design specification, for instanceT L ¼ 200 μs, the DLF coefficients should meet the requirement specified by formula (37). 8T r =½GL ðα þ βÞ r 200 μs ) α þ β Z 0:026
ð37Þ
After substituting ADPLL parameters into formula (36) we have: qffiffiffiffi qffiffiffiffi ð38Þ 2:64 β β r α r 8:82 β β By plugging phase noise performance constraints, phase noise of equations in Table 2 and close loop transfer functions of each noise source into formulas (33) and (34), we can derive: 1:7 U β þ 1:1 þ 87β ½0:12β ðβ þ 2αÞ þ β þ α pffiffiffiffi pffiffiffiffi r 3:16 105 0:34 β ½0:12ðα þ β Þ þ 2 cos ð0:34 β Þ 22
ð39Þ
3:25α2 þ14:12β þ0:24α þ 2:06β þ 0:07αβ r 1
ð40Þ
1=2
3=2
2
Based on formulas (37)–(40), we can plot the boundary condition lines in Fig. 7. The shadow area specifies the possible DLF
Table 2 Phase noise of each functional unit. REF
11:2
Sr ðf Þ ¼ 10 15 þ 10 f
9:4
f
ST ¼ 1:075 10
DCO
SDQ N ¼ 1:53 10 15 2
SDCO ðf Þ ¼ 100:33 =f þ 106 =f
Ref. [24]
f
9
PFD
DSM
7:0
þ 10 2 þ 10 3
Eq. (7) Eq. (3) 3
SDS ¼ π 2 ½2 sin ðπf =f sΔ Þ2 =3ðf sΔ Þ
Ref. [26] Eq. (4)
where T L is locking time constrain. Regarding the phase noise, it is usually evaluated at a selected frequency offset (i.e. 1 MHz) from the central frequency. Additionally, for an under damped ðζ o 1Þ PLL system, its closed loop transfer function has a peak value at the natural frequency, which will lead to an increased phase noise at this particular frequency point. Therefore, in the design analysis, we choose to characterize ADPLL output phase noise at frequency points f n and 1 MHz offset respectively for phase noise constraint characterizations. The output phase noise constraints are: phase noise at natural frequency Sout ðf n Þ and 1 MHz Sout ð1M Þ not exceeding Sf n and S1M , respectively. Sout ðf n Þ rSf n
ð33Þ
Fig. 6. ADPLL locking time with different DLF coefficients.
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coefficient values for α and β that can meet all the requirements including locking time, phase noise and system stability. Fig. 8 plots ADPLL output phase noise with different DLF coefficients. As illustrated, when α ¼ 2 1 and β ¼ 2 5 , the maximum in band phase noise is 89 dBc=Hz, the phase noise at 1 MHz frequency offset is 110 dBc=Hz. Accordingly, the locking time is calculated to be 9:8 μs. When α ¼ 2 2 and β ¼ 2 7 , the maximum in band phase noise is 82 dBc=Hz, the phase noise at 1 MHz frequency offset is 111 dBc=Hz and the locking time is 20:2 μs. Apparently, there is a trade off among ADPLL locking time, maximum in band phase noise and phase noise at specific frequency offset (i.e. frequency offset at 1 MHz). Lower phase noise requires smaller DLF coefficients, while faster locking speed needs larger DLF coefficients. In another word, to obtain lower phase noise, DLF coefficients should be selected from the lower left corner of the shadow area in Fig. 7. While to achieve a faster locking speed, DLF coefficients should be selected from the upper right corner of shadow area in Fig. 7. Therefore, it is important to set proper DLF coefficient values to achieve performance balance. DCO resolution is determined by last significant bit of DCO input control code. The limited frequency resolution leads to DCO quantization noise. We have to consider the DCO resolution when DCO quantization noise is comparable to DCO oscillator noise. We use NDCO ¼ 6, K DCO ¼ 100 KHz=LSB in above case study. DCO quantization noise of DCO is 151 dBc which is at least 12 dB smaller than DCO oscillator noise at frequency offset range from 1 KHz to 5 MHz. Hence, the quantization noise of DCO in this case study can be neglected.
6. Case study In order to verify the developed analytical model, we select ADPLLs in references [28,29] as study cases. We develop models based on ADPLL topology presented in these papers and perform noise simulations. By comparing simulation results and measurement data provided in the original manuscripts, we are able to evaluate the proposed phase noise model effectiveness.
6.1. Architecture-I ADPLL In [28], a 1.5 GHz ADPLL is developed. The loop bandwidth is 20 KHz. Other parameters are listed as follows: reference signal frequency f r is 45 MHz. Output frequency is 1.5 GHz. Divider ratio N is 33.3333. K DCO equals 577 Hz/LSB. TDC resolution equals 10 ps. The order number of ΔΣ modulators in DCO block is 1, respectively. The sampling frequency of those two ΔΣ modulators are f sΔ ¼ 0:75 GHz. The DLF coefficients α ¼ 22 and β ¼ 2 6 are computed from loop bandwidth and phase margin. A 45 MHz crystal oscillator [31] phase noise equals: Sr ðf Þ ¼ 10 16:1 þ 10 10:2 =f þ 10 7:6 =f þ 10 6:1 =f 2
3
The free running 1.5 GHz DCO oscillator phase noise in [28] is approximated as: SDCO ðf Þ ¼ 10 15:5 þ 10 8:2 =f þ 10 4:2 =f þ 100:9 =f 2
3
By using the analytical modeling method developed in proceeding sections, we are able to characterize the noise contributions of different noise sources as shown in Fig. 9. As can be seen clearly, the in-band phase noise is mainly contributed by noises in reference clock and PFD function block. In out-of-band frequency range, the total phase noise is mainly affected by the noises in PFD, DCO and ΔΣ modulator. The primary fractional spur occurs at offset frequency f spur ¼ F f rac f r ¼ 15 MHz. From Eq. (14), rollof f ðf spur Þ is calculated to be 48:5 dB. The primary fractional spur PSD equals: " # ð21 1Þ U577 Sspur ¼ 20 log 48:5 dB ¼ 142:8 dBc 2 15 MHz
Fig. 7. DLF coefficients determination.
For validation, we obtain ADPLL circuit hardware measurement results. The difference between the simulated and measured total phase noise at different frequency points are listed in Table 3. It shows that our model simulation achieves good agreement with hardware results.
Fig. 8. Output phase noise with different DLF coefficients.
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7
oscillators in references [31,32].
6.2. Architecture-II ADPLL
Sr ðf Þ ¼ 10 14:7 þ 10 10:3 =f þ 10 8:3 =f þ 10 4:8 =f 2
In [29], a 4.9–6.9 GHz fractional-N ADPLL for radio telecommunication is presented. The loop bandwidth is 200 KHz. Other important parameters are: reference clock frequency f r ¼ 48 MHz, output frequency is 5.376021831 GHz, FCW is 112.0004548125. K DCO ¼ 26 kHz, TDC-PD resolution τT ¼ 15 ps, TDC output bit-width is 9 and the 2nd order MASH ΔΣ modulator in DCO block with sampling frequency f sΔ ¼ f r is employed. There is an extra 9-bit fine tuning code in DCO block. The DLF coefficients are α ¼ 2 5 and β ¼ 2 10 . Phase noise PSD of the 48 MHz reference clock and LC-tank DCO at 5.3 GHz output are approximated as follows, which are in agreements with the similar
Table 3 Output phase noise differences between simulation and measurement at some typical frequencies. Phase noise (dBc/Hz) at frequency offset
SPUR
10 K Hz
Freq. (Hz) PSD
100 K Hz
1 M Hz
10 M Hz
Simu. 92.4 124.7 140.4 150.1 15M Meas 96.3 124.8 141.5 149.5 15M Error 3.9 dB 0.1 dB 1.1 dB 0.6 dB 0
142.8 dBc 142.5 dBc 0.3 dB
SDCO ðf Þ ¼ 10 13:8 þ 10 0:2 =f
3
2
From our model analysis, the contribution of each noise to the total output phase noise is plotted in Fig. 10. The in-band phase noise is mainly contributed by the reference clock noise and TDCPD noise. In high noise frequency range, the total noise is affected by the noises of TDC-PD, DCO and ΔΣ modulator. The primary fractional spur occurs at the offset frequency f spur ¼ F f rac f r ¼ 21:8 KHz. Since the fractional spur locates within loop bandwidth, the rollof f ðf spur Þ equals 0 dB. The primary fractional spur PSD equals Sspur ¼ 20 log
! ð22 1Þ U 26 kHz=29 þ 0 dB ¼ 49:1 dBc 2 21:8 kHz
The difference between the simulated and measured total phase noise at different frequency points are listed in Table 4. Also, the simulation results from proposed model show good agreement with hardware results. In the presented phase noise model, other noise sources such as power supply noise and thermal noise are not considered, which is the major cause of the deviation between the simulation results and the measurement results. Those noises heavily depend
Fig. 9. Simulated phase noise of each noise source and total phase noise at 1.5 GHz output frequency.
Fig. 10. Simulated phase noise of each noise source and total phase noise at 5.376021831 GHz output frequency.
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Table 4 Output phase noise differences between simulation and measurement at some typical frequencies. Phase Noise (dBc/Hz) at frequency offset
Simu. Meas Error
SPUR
10 K Hz
100 K Hz
1 M Hz
10 M Hz Freq. (Hz) PSD
95.2 96.9 1.7 dB
92.1 90.7 1.4 dB
116.7 116.4 0.3 dB
134 137 3dB
21.8K 20K 1.8K
49.1 dBc 45dBc 4.1 dB
on the operating conditions of the system that ADPLL is embedded in, such as the on-chip power grid signal integrity etc., whose noise characterizations are not available in the work presented in this paper. Actually, if these noise data are provided, their effects on ADPLL output phase noise can also be projected. 7. Conclusion This paper develops an analytic noise model for both architecture-I and architecture-II ADPLLs. By analyzing fractional spur, noise contribution and transfer function of each function block, the total phase noise and fractional spur can be projected. The total phase noise and primary fractional spur between simulation results and measurement data collected show reasonable agreements. Furthermore, we plot boundary condition lines according to phase noise, locking time and damping ratio constrains in order to determine proper DLF coefficients. This analysis method can effectively project phase noise and fractional spur and can be used as design guidance for ADPLL variables determination and optimization. References [1] J. Segundo, L. Quintanilla, J. Arias, L. Enriquez, J.M. Hernandez, J. Vicente, A PLLbased synthesizer for tunable digital clock generation in a continuous-time ΣΔ A/D converter, Integr. VLSI J. 42 (1) (2009) 24–33. [2] R.B. Staszewski, et al., All-digital PLL and transmitter for mobile phones, IEEE J. Solid-State Circuits 40 (12) (2005) 2469–2482. [3] M.E. Heidari Minjae Lee, A.A. Abidi, A. Low-Noise Wideband, Digital Phaselocked loop based on a coarseCFine time-to-digital converter with subpicosecond resolution, IEEE J. Solid-State Circuits 44 (10) (2009) 2809–2816. [4] M.E.S. Elrabaa, A portable high-frequency digitally controlled oscillator (DCO), Integr. VLSI J. (2013). [5] M.H. Perrott, M.D. Trott, C.G. Sodini, A modeling approach for fractional-N frequency synthesizers allowing straightforward noise analysis, IEEE J. SolidState Circuits 37 (2002) 1028–1038. [6] B. Jiang, T. Xia, G. Wang, PLL low pass filter design considering unified specification constraints, Analog Integr. Circuits Signal Process. (2014) 1–8. [7] F. Herzel, S.A. Osmany, J.C. Scheytt, Analytical phase-noise modeling and charge pump optimization for fractional-N PLLs, IEEE Trans. Circuits Syst. I: Regul. Pap. 57 (2010) 1914–1924 (Aug.). [8] A. Hajimiri, S. Limotyrakis, T.H. Lee, Jitter and phase noise in ring oscillators, IEEE J. Solid-State Circuits 34 (6) (1999) 790–804. [9] T. Xia, Analytical model for spread-spectrum clock generator circuit characterization, Int. J. Circuit Theory Appl. (2010). [10] Nicola Da Dalt, A. Design-Oriented, Study of the nonlinear dynamics of digital bang–bang PLLs, IEEE Trans. Circuits Syst.-I: Regul. Pap. 52 (1) (2005) 21–31 (Jan.). [11] R.B. Staszewski, D. Leipold, Chih-Ming Hung, P.T. Balsara, TDC-based frequency synthesizer for wireless applications, in: Proceedings of IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, August 2004, pp. 215–218. [12] R.B. Staszewski, P.T. Balsara, Phase-Domain All-Digital Phase-Locked Loop, in: Proceedings of IEEE Transactions on Circuits and Systems-II: Express Briefs, 52, 3, March 2005, pp. 159–163. [13] S. Mendel, C. Vogel, A z-domain model and analysis of phase-domain alldigital phase-locked loops, Norchip (2007) 1–6. [14] Ioannis L. Syllaios, Poras T. Balsara, R.B. Staszewski, Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications, in: Proceedings of IEEE Custom Intergrated Circuits Conference (CICC), 2007, pp. 861–864. [15] Ioannis L. Syllaios, Robert Bogdan Staszewski, Poras T. Balsara, Time-Domain Modeling of an RF All-Digital PLL, in: Proceedings of IEEE Transactions on Circuits and Systems-II: Express Briefs, 55, 6, June 2008, pp. 601–605.
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Bo Jiang was born in Hangzhou, P.R. China. He received the B.S. and M.S. degrees in Electrical Engineering from Xi’an University of Technology and Xi’an Jiaotong University, Xi’an, P.R. China, in 2003 and 2006, respectively. He is currently working toward the Ph.D. degree in Electrical Engineering at the University of Vermont. His research interests include low noise phase locked loop (PLL) and all digital PLL frequency synthesizer circuit design and modeling.
Tian Xia received the B.E. degree in Electrical Engineering from the Huazhong University of Science and Technology, Wuhan, China, in 1994, the M.S. degree from the Nanjing University of Posts and Telecom munications, Nanjing, China, in 2000, and the Ph.D. degree in Electrical and Computer Engineering from the University of Rhode Island, Kingston, U.S., in 2003. During the summers of 2002 and 2003, he did his internship in IBM T.J. Watson Research Center, Yorktown Heights, NY. He is now an Associate Professor with the School of Engineering at the University of Vermont. His current research interests are in mixedsignal and RF circuit design and test. He is the recipient of the Best Paper Award of IEEE North Atlantic Test Workshop (NATW) 2005, the Best Paper Award of IEEE System on Chip Conference (SOCC) 2012. Dr. Xia received IBM Faculty Awards in 2005, 2006 and 2008. He was the program chair of IEEE North Atlantic Test Workshop 2011, 2012, 2013, 2014; Guest editor of Journal of Electronic Test: Theory and Application (JETTA) 2013, and has been the Associate Editor of Journal of Circuits, Systems, and Computers (JCSC) since 2013.
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