Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS
Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha Chandrakasan Massachusetts Institute of Technology
presented at
ESSCIRC 2005
Outline
Introduction to Static Noise Margin (SNM)
Modeling SNM
Dependencies of SNM
Impact of Variation on SNM
Conclusions
Graphical Method for Finding SNM 0.3 BL
VTC for inverter 2 VTC−1 for inverter 1 VTC for inv 2 with VN=SNM VTC−1 for inv 1 with V =SNM N
BLB
WL M3
M6
M2
Q
M5 M1
M4
QB
VN
Inverter 1
QB (V)
VN
0.15
Inverter 2
0 0
SNM is length of side of the largest embedded square on the butterfly curve
0.15
0.3
Q (V) 0.3
ax
is
→
Difference in [u,v] VTC for inv 2 −1 VTC for inv 1
QB (V)
0.1 0
u
−0.1
is
ax →
E. Seevinck, F. List, J. Lohstroh, “Static-Noise Margin Analysis of MOS SRAM Cells” JSSC, Oct ‘87.
y
0.2
−0.2 −0.2
−0.1
0
0.1
Q (V)
0.2
0.3
SNM during Hold and Read BL
BLB
WL=0 M3
M6
M2
1
M1
M4
1
0
M6 M5
M1
M4
0.3
Hold
0.15
0.15
BLB prech to 1
M2
QB (V)
QB (V)
M3 M5
0.3
0 0
BL prech to 1 WL=1
0.3
0
Read
0.15
0 0
Q (V)
0.15
Q (V)
Read SNM is worst-case
0.3
Outline
Introduction to Static Noise Margin (SNM)
Modeling SNM
Dependencies of SNM
Impact of Variation on SNM
Conclusions
Modeling SNM Hold BLB
WL=0 M3
Q
Vth QB =
⎛ V − VT I D = I S exp ⎜⎜ GS ⎝ nVth
M6
M2
M5 M1
M4
In Sub-threshold:
QB
⎛ 1 − exp((−VDD + Q) / Vth ) ⎞ ⎞ n1n3 ⎛⎜ I S 3 ⎜⎜ ⎟⎟ ⎟ ln ln + ⎟ n1 + n3 ⎜⎝ I S 1 Q V 1 exp( / ) − − th ⎝ ⎠⎠ nV n n ⎛V V ⎞ + 1 DD + 1 3 ⎜⎜ T 1 − T 3 ⎟⎟ n1 + n3 n1 + n3 ⎝ n1 n3 ⎠
−V DD ⎛ ⎛ ⎞⎞ ⎜ ⎜ ⎟⎟ V th 2 QB = VDD + Vth ln ⎜ 0.5 * ⎜1 − G + (G − 1) + 4e G ⎟ ⎟, ⎜ ⎟⎟ ⎜ ⎝ ⎠⎠ ⎝ ⎛ n + n6 1 ⎛ VT 4 VT 6 ⎞ ⎞⎟ I V ⎟⎟ ⎜⎜ G = exp ⎜⎜ 4 Q − ln S 6 − DD − − ⎟ n n V I n V V n n th S th th 4 6 4 6 4 6 ⎠⎠ ⎝ ⎝
⎞⎛ ⎛ − VDS ⎟⎟⎜1 − exp ⎜⎜ ⎜ ⎠⎝ ⎝ Vth
Assumptions: •IM3=IM1 •IM6=IM4 sims eqns
QB
BL
VT6−1σ
Q
⎞⎞ ⎟⎟ ⎟ ⎟ ⎠⎠
Modeling SNM Read BL prech to 1 WL=1 M3
BLB prech to 1
M6
M2
M5
Q=low
QB =
•IM2=IM1 •IM6=IM4
M4
QB = high
⎛ 1 − exp((−VDD + Q ) / Vth ) ⎞ IS2 ⎟⎟ + n1Vth ln⎜⎜ 1 exp( / ) Q V I S1 − − th ⎠ ⎝ n + VT 1 + 1 (VDD − VT 2 − Q ) n2
sims eqns
QB
M1
n1Vth ln
Assumptions when Q is low:
VT1−1σ
Q
Outline
Introduction to Static Noise Margin (SNM)
Modeling SNM
Dependencies of SNM
Impact of Variation on SNM
Conclusions
SNM Dependence on VDD
1.2
1.2
Hold
Read
QB
0.8
QB
0.8
0.4
0.4
0.2
0.2
0 0
0.2 0.4
0.8 Q
1.2
0 0
0.2 0.4
0.8 Q
Read SNM less sensitive in above VT operation
1.2
SNM Dependence on VDD 0.5
SNM (V)
0.4
Hold Read V /2 DD
0.3 0.2 0.1 0 0
0.2
0.4
V
0.6 (V)
0.8
1
DD
VDD noise affects SNM by less than half
1.2
SNM Dependence on Temperature 1.2
0.5
100 °C 0 °C
QB (V)
SNM (V)
0.4 0.3 0.2 0.1 0 −40
0.3 0 0
0
40 T (°C)
VDD=0.3V 0.3
1.2 Q (V)
Temperature impact not large because it affects pFETs and nFETs similarly
80
VDD=1.2V
120
Transistor Sizing Impact on SNM BL
BLB
WL M3
M6
M2
e.g.
M5 M1
M4
QB =
QB
⎛ 1 − exp((−VDD + Q) / Vth ) ⎞ ⎞ n1n3 ⎛⎜ I S 3 ⎜⎜ ⎟⎟ ⎟ + ln ln ⎟ n1 + n3 ⎜⎝ I S 1 Q V − − 1 exp( / ) th ⎝ ⎠⎠ nV n n ⎛V V ⎞ + 1 DD + 1 3 ⎜⎜ T 1 − T 3 ⎟⎟ n1 + n3 n1 + n3 ⎝ n1 n3 ⎠
VDD=0.3V M1,4 M3,6 M2,4
0.1
SNM (V)
Q
Vth
0.08
Hold
0.06 0.04 0.02 0 0
Read 2
4 6 8 Normalized width
10
Sizing impact not so large because of logarithmic impact on VTCs
Cell Ratio and Sub-threshold SNM BL
BLB
WL M3 M2
M5 M1
M4
QB
0.5
0.4
SNM (V)
Q
Cell ratio = (W/L)1 / (W/L)2 or (W/L)4 / (W/L)5
M6
Hold Read
1.2V
0.3
0.2
0.3V
0.1
0 1
1.5
2
2.5
3 Cell Ratio
3.5
4
4.5
Cell ratio much less important for sub-threshold SNM
5
Outline
Introduction to Static Noise Margin (SNM)
Modeling SNM
Dependencies of SNM
Impact of Variation on SNM
Conclusions
Impact of Mismatch on SNM BL
BLB
WL M3
M6
M2
Q
M5 M1
M4
QB
0.3
Until now, we have assumed that the two sides of the bitcell are symmetric. With mismatch, that is not true.
Hold
QB (V)
SNM high SNM low 0.15
0 0
SNM is the minimum of SNM high and SNM low, which are different due to mismatch 0.15
Q (V)
0.3
Single FET VT mismatch
M3
Sensitivity of SNM to single FET mismatch is roughly linear.
M6
M2
Q
3
BLB
WL
M5 M1
M4
QB
Norm. Read SNM high
BL
2
M1
1
M5 M3
0
−1 −5
5 3
Norm. Read SNM high
Norm. Read SNM high
Above threshold SNM can use 1st order series model
Above−threshold
1 −1 −3 −5
∆V
T4
(σ)
5
5 3
M6
M2 ∆V (σ) T
Sub−threshold Cannot use 1st order series model for subthreshold SNM
1 −1 −3 −5
M4
∆V
T4
(σ)
5
5
Mismatch SNM Distributions Random mismatch in all 6 transistors Minimum WL
600
4 Minimum WL
600
Hold
400
Read 200
0 −0.1
Hold
400
Read 200
0 SNM high (V)0.2
0 −0.1
0 SNM high (V)0.2
Like above-threshold, SNM high and SNM low are normally distributed with threshold voltage mismatch
Modeling PDF for Mismatch SNM is min(SNM high, SNM low); Tail is most important for yield If SNMhigh, SNMlow are independent and identically distributed (iid), then the pdf for SNM is:
fSNM=2fSNMhigh(1-FSNMhigh) 0.2
SNM Hold
0.1
SNM Read
0
SNM high 0
0.1
0.2
SNM low
0.1
SNM low
0
0.2
SNM high 0
0.1
0.2
SNM high and SNM low are nearly identically distributed, but NOT independent
Simulations Compared to Model 3
Try the model anyway: fSNM=2fSNMhigh(1-FSNMhigh) Model matches well for the worst-case tail
10
2
10
1
10
0
10
1k model within 3% of 50k model
10k
−1
10 −0.1
0
SNM (V)
0.1
model sim Model based on short sims is accurate for much longer sims
100 1
Normal distribution
Model for N−pt M−C N=100,500,800,1k,50k SNM (V)
0.06
Global Process Corner Variation
2k
Hold Read
1k 0 0.02
SNM (V) Global variation causes variation in SNM
0.1
Global Variation and Local Mismatch When mismatch occurs in addition to global variation, the mismatch distribution shifts. 3
Occurrences
10
2
10
Model : no global variation Monte−Carlo : no global varn Model : 3σ global varn Monte−Carlo : 3σ global varn
1
10
0
10 −0.1 −0.05 0 0.05 Read SNM (V)
Model still works with global variation and mismatch
Conclusions
SNM limits sub-threshold memory yield
SNM most strongly depends on mismatch and global variation
Proper modeling for the tail of the SNM distribution allows fast estimation of SNM yield
presented at
ESSCIRC 2005
Outline
Introduction to Static Noise Margin (SNM)
Modeling SNM
Dependencies of SNM
Impact of Variation on SNM
Conclusions
Graphical Method for Finding SNM 0.3 BL
VTC for inverter 2 VTC−1 for inverter 1 VTC for inv 2 with VN=SNM VTC−1 for inv 1 with V =SNM N
BLB
WL M3
M6
M2
Q
M5 M1
M4
QB
VN
Inverter 1
QB (V)
VN
0.15
Inverter 2
0 0
SNM is length of side of the largest embedded square on the butterfly curve
0.15
0.3
Q (V) 0.3
ax
is
→
Difference in [u,v] VTC for inv 2 −1 VTC for inv 1
QB (V)
0.1 0
u
−0.1
is
ax →
E. Seevinck, F. List, J. Lohstroh, “Static-Noise Margin Analysis of MOS SRAM Cells” JSSC, Oct ‘87.
y
0.2
−0.2 −0.2
−0.1
0
0.1
Q (V)
0.2
0.3
SNM during Hold and Read BL
BLB
WL=0 M3
M6
M2
1
M1
M4
1
0
M6 M5
M1
M4
0.3
Hold
0.15
0.15
BLB prech to 1
M2
QB (V)
QB (V)
M3 M5
0.3
0 0
BL prech to 1 WL=1
0.3
0
Read
0.15
0 0
Q (V)
0.15
Q (V)
Read SNM is worst-case
0.3
Outline
Introduction to Static Noise Margin (SNM)
Modeling SNM
Dependencies of SNM
Impact of Variation on SNM
Conclusions
Modeling SNM Hold BLB
WL=0 M3
Q
Vth QB =
⎛ V − VT I D = I S exp ⎜⎜ GS ⎝ nVth
M6
M2
M5 M1
M4
In Sub-threshold:
QB
⎛ 1 − exp((−VDD + Q) / Vth ) ⎞ ⎞ n1n3 ⎛⎜ I S 3 ⎜⎜ ⎟⎟ ⎟ ln ln + ⎟ n1 + n3 ⎜⎝ I S 1 Q V 1 exp( / ) − − th ⎝ ⎠⎠ nV n n ⎛V V ⎞ + 1 DD + 1 3 ⎜⎜ T 1 − T 3 ⎟⎟ n1 + n3 n1 + n3 ⎝ n1 n3 ⎠
−V DD ⎛ ⎛ ⎞⎞ ⎜ ⎜ ⎟⎟ V th 2 QB = VDD + Vth ln ⎜ 0.5 * ⎜1 − G + (G − 1) + 4e G ⎟ ⎟, ⎜ ⎟⎟ ⎜ ⎝ ⎠⎠ ⎝ ⎛ n + n6 1 ⎛ VT 4 VT 6 ⎞ ⎞⎟ I V ⎟⎟ ⎜⎜ G = exp ⎜⎜ 4 Q − ln S 6 − DD − − ⎟ n n V I n V V n n th S th th 4 6 4 6 4 6 ⎠⎠ ⎝ ⎝
⎞⎛ ⎛ − VDS ⎟⎟⎜1 − exp ⎜⎜ ⎜ ⎠⎝ ⎝ Vth
Assumptions: •IM3=IM1 •IM6=IM4 sims eqns
QB
BL
VT6−1σ
Q
⎞⎞ ⎟⎟ ⎟ ⎟ ⎠⎠
Modeling SNM Read BL prech to 1 WL=1 M3
BLB prech to 1
M6
M2
M5
Q=low
QB =
•IM2=IM1 •IM6=IM4
M4
QB = high
⎛ 1 − exp((−VDD + Q ) / Vth ) ⎞ IS2 ⎟⎟ + n1Vth ln⎜⎜ 1 exp( / ) Q V I S1 − − th ⎠ ⎝ n + VT 1 + 1 (VDD − VT 2 − Q ) n2
sims eqns
QB
M1
n1Vth ln
Assumptions when Q is low:
VT1−1σ
Q
Outline
Introduction to Static Noise Margin (SNM)
Modeling SNM
Dependencies of SNM
Impact of Variation on SNM
Conclusions
SNM Dependence on VDD
1.2
1.2
Hold
Read
QB
0.8
QB
0.8
0.4
0.4
0.2
0.2
0 0
0.2 0.4
0.8 Q
1.2
0 0
0.2 0.4
0.8 Q
Read SNM less sensitive in above VT operation
1.2
SNM Dependence on VDD 0.5
SNM (V)
0.4
Hold Read V /2 DD
0.3 0.2 0.1 0 0
0.2
0.4
V
0.6 (V)
0.8
1
DD
VDD noise affects SNM by less than half
1.2
SNM Dependence on Temperature 1.2
0.5
100 °C 0 °C
QB (V)
SNM (V)
0.4 0.3 0.2 0.1 0 −40
0.3 0 0
0
40 T (°C)
VDD=0.3V 0.3
1.2 Q (V)
Temperature impact not large because it affects pFETs and nFETs similarly
80
VDD=1.2V
120
Transistor Sizing Impact on SNM BL
BLB
WL M3
M6
M2
e.g.
M5 M1
M4
QB =
QB
⎛ 1 − exp((−VDD + Q) / Vth ) ⎞ ⎞ n1n3 ⎛⎜ I S 3 ⎜⎜ ⎟⎟ ⎟ + ln ln ⎟ n1 + n3 ⎜⎝ I S 1 Q V − − 1 exp( / ) th ⎝ ⎠⎠ nV n n ⎛V V ⎞ + 1 DD + 1 3 ⎜⎜ T 1 − T 3 ⎟⎟ n1 + n3 n1 + n3 ⎝ n1 n3 ⎠
VDD=0.3V M1,4 M3,6 M2,4
0.1
SNM (V)
Q
Vth
0.08
Hold
0.06 0.04 0.02 0 0
Read 2
4 6 8 Normalized width
10
Sizing impact not so large because of logarithmic impact on VTCs
Cell Ratio and Sub-threshold SNM BL
BLB
WL M3 M2
M5 M1
M4
QB
0.5
0.4
SNM (V)
Q
Cell ratio = (W/L)1 / (W/L)2 or (W/L)4 / (W/L)5
M6
Hold Read
1.2V
0.3
0.2
0.3V
0.1
0 1
1.5
2
2.5
3 Cell Ratio
3.5
4
4.5
Cell ratio much less important for sub-threshold SNM
5
Outline
Introduction to Static Noise Margin (SNM)
Modeling SNM
Dependencies of SNM
Impact of Variation on SNM
Conclusions
Impact of Mismatch on SNM BL
BLB
WL M3
M6
M2
Q
M5 M1
M4
QB
0.3
Until now, we have assumed that the two sides of the bitcell are symmetric. With mismatch, that is not true.
Hold
QB (V)
SNM high SNM low 0.15
0 0
SNM is the minimum of SNM high and SNM low, which are different due to mismatch 0.15
Q (V)
0.3
Single FET VT mismatch
M3
Sensitivity of SNM to single FET mismatch is roughly linear.
M6
M2
Q
3
BLB
WL
M5 M1
M4
QB
Norm. Read SNM high
BL
2
M1
1
M5 M3
0
−1 −5
5 3
Norm. Read SNM high
Norm. Read SNM high
Above threshold SNM can use 1st order series model
Above−threshold
1 −1 −3 −5
∆V
T4
(σ)
5
5 3
M6
M2 ∆V (σ) T
Sub−threshold Cannot use 1st order series model for subthreshold SNM
1 −1 −3 −5
M4
∆V
T4
(σ)
5
5
Mismatch SNM Distributions Random mismatch in all 6 transistors Minimum WL
600
4 Minimum WL
600
Hold
400
Read 200
0 −0.1
Hold
400
Read 200
0 SNM high (V)0.2
0 −0.1
0 SNM high (V)0.2
Like above-threshold, SNM high and SNM low are normally distributed with threshold voltage mismatch
Modeling PDF for Mismatch SNM is min(SNM high, SNM low); Tail is most important for yield If SNMhigh, SNMlow are independent and identically distributed (iid), then the pdf for SNM is:
fSNM=2fSNMhigh(1-FSNMhigh) 0.2
SNM Hold
0.1
SNM Read
0
SNM high 0
0.1
0.2
SNM low
0.1
SNM low
0
0.2
SNM high 0
0.1
0.2
SNM high and SNM low are nearly identically distributed, but NOT independent
Simulations Compared to Model 3
Try the model anyway: fSNM=2fSNMhigh(1-FSNMhigh) Model matches well for the worst-case tail
10
2
10
1
10
0
10
1k model within 3% of 50k model
10k
−1
10 −0.1
0
SNM (V)
0.1
model sim Model based on short sims is accurate for much longer sims
100 1
Normal distribution
Model for N−pt M−C N=100,500,800,1k,50k SNM (V)
0.06
Global Process Corner Variation
2k
Hold Read
1k 0 0.02
SNM (V) Global variation causes variation in SNM
0.1
Global Variation and Local Mismatch When mismatch occurs in addition to global variation, the mismatch distribution shifts. 3
Occurrences
10
2
10
Model : no global variation Monte−Carlo : no global varn Model : 3σ global varn Monte−Carlo : 3σ global varn
1
10
0
10 −0.1 −0.05 0 0.05 Read SNM (V)
Model still works with global variation and mismatch
Conclusions
SNM limits sub-threshold memory yield
SNM most strongly depends on mismatch and global variation
Proper modeling for the tail of the SNM distribution allows fast estimation of SNM yield
