Chapter 6 figures
I0
D
A0
C R
I1
D
A1
C R
I2
D
A2
C R
I3
D
A3
C R
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Clock Clear Fig. 6-1 4-Bit Register
Load
D
I0
C
D
I1
A1
C
D
I2
A2
C
D I3
C
Clock © 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
A0
Fig. 6-2 4-Bit Register with Parallel Load
A3
Serial input
SI
D
D
C
D
C
C
CLK Fig. 6-3 4-Bit Shift Register
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
SO
D
C
Serial output
SI
SO
SI
Shift register A
SO Shift register B
CLK
Clock Shift control
CLK
(a) Block diagram
Clock
Shift control
CLK
T1
T2
T3
T4
(b) Timing diagram © 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Fig. 6-4 Serial Transfer from Register A to register B
Shift control CLK
SI Shift register A
SO x y
Serial input
SI
S FA
z Shift register B
SO
Q D
C Clear
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Fig. 6-5 Serial Adder
C
Shift control CLK
Serial input
SI Shift register A
SI Shift register B
SO ⫽ x
S
J
SO ⫽ y
C K
Clear Fig. 6-6 Second form of Serial Adder
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Parallel outputs A3
Clear
C
D
A2
C
D
A1
C
D
A0
C
D
CLK
S1 S0
4⫻1 MUX 3 2 1 0
4⫻1 MUX 3 2 1 0
4⫻1 MUX 3 2 1 0
4⫻1 MUX 3 2 1 0
Serial input for shift-right I3
I2
I1 Parallel inputs
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Fig. 6-7 4-Bit Universal Shift Register
I0
Serial input for shift-left
A0
T
C R
Count
D
Count
A1
T
D
C R
D
C R
Logic-1 Reset
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
C R
Reset
(a) With T flip-flops
A2
CR
A3
T
A1
CR
A2
T
CR
D
C R
A0
(b) With D flip-flops
Fig. 6-8 4-Bit Binary Ripple Counter
A3
0000
0001
0010
0011
0100
1001
1000
0111
0110
0101
Fig. 6-9 State Diagram of a Decimal BCD-Counter
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Q1
J Count
C K
Q2
J C K
Q4
J C K
Q8
J C K
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Logic-1 Fig. 6-10 BCD Ripple Counter
Q8 Q4 Q2 Q1
Q8 Q4 Q2 Q1
Q 8 Q4 Q 2 Q 1
BCD Counter
BCD Counter
BCD Counter
10 2 digit
101 digit
100 digit
Fig. 6-11 Block Diagram of a Three-Decade Decimal BCD Counter
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Count pulses
J
A0
C Count enable
K
J
A1
C K
J
A2
C K
J
A3
C K
To next stage CLK © 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Fig. 6-12 4-Bit Synchronous Binary Counter
Up
Down
T C
A0
T
A1
C
T C
A2
T
A3
C © 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
CLK Fig. 6-13 4-Bit Up-Down Binary Counter
Count Load I0
J C K
A0
I1
J C K
A1
I2
J C K
A2
I3
J C K
A3
Clear CLK Carry-output © 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Fig. 6-14 4-Bit Binary Counter with Parallel Load
A3 A2 A1 A0
A3 A2 A1 A0
Count ⫽ 1
Load Counter of Fig.6-14
Clear ⫽ 1
Count ⫽ 1
Clear Counter of Fig.6-14
CLK Inputs ⫽ 0
CLK
Inputs have no effect
(a) Using the load input
(b) Using the clear input
Fig. 6-15 Two ways to Achieve a BCD Counter Using a Counter with Parallel Load
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Load ⫽ 0
A
J
B
C
K
J
C
C
K
J
C
K Clock
(a) Logic diagram
000
111
001
110
010
101 100
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Logic-1
011
(b) State diagram Fig. 6-16 Counter with Unused States
T0 T1 T2 T3
2⫻4 decoder Shift right
T0 T1 T2 T3
Count enable
(a) Ring-counter (initial value ⫽ 1000)
2-bit counter (b) Counter and decoder
CLK
T0
T1
T2 T3
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
(c) Sequence of four timing signals Fig. 6-17 Generation of Timing Signals
A
D
B
D
C
C
D
C
C
A⬘
B⬘
E
D C C⬘
CLK (a) Four-stage switch-tail ring counter
Flip-flop outputs
Sequence number
A
B
C
E
AND gate required for output
1 2 3 4 5 6 7 8
0 1 1 1 1 0 0 0
0 0 1 1 1 1 0 0
0 0 0 1 1 1 1 0
0 0 0 0 1 1 1 1
A⬘E⬘ AB⬘ BC⬘ CE⬘ AE A⬘B B⬘C C⬘E
(b) Count sequence and required decoding © 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Fig. 6-18 Construction of a Johnson Counter
E⬘
0ns
20ns
40ns
60ns
80ns
100ns 120ns 140ns 160ns
testcounter.Count testcounter.Reset testcounter.A0 testcounter.A1 testcounter.A2 testcounter.A3 (a) From 0 to 170 ns 72ns
74ns
76ns
78ns
80ns
82ns
84ns
testcounter.Count testcounter.Reset testcounter.A0 testcounter.A1 testcounter.A2 testcounter.A3 (b) From 70 to 92 ns © 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Fig. 6-19 Simulation Output of HDL Example 6-4
86ns
88ns
90ns
9
Load (L) J CLK
Count (C)
K
Data (I)
Fig. P6-21
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
D
A0
C R
I1
D
A1
C R
I2
D
A2
C R
I3
D
A3
C R
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Clock Clear Fig. 6-1 4-Bit Register
Load
D
I0
C
D
I1
A1
C
D
I2
A2
C
D I3
C
Clock © 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
A0
Fig. 6-2 4-Bit Register with Parallel Load
A3
Serial input
SI
D
D
C
D
C
C
CLK Fig. 6-3 4-Bit Shift Register
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
SO
D
C
Serial output
SI
SO
SI
Shift register A
SO Shift register B
CLK
Clock Shift control
CLK
(a) Block diagram
Clock
Shift control
CLK
T1
T2
T3
T4
(b) Timing diagram © 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Fig. 6-4 Serial Transfer from Register A to register B
Shift control CLK
SI Shift register A
SO x y
Serial input
SI
S FA
z Shift register B
SO
Q D
C Clear
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Fig. 6-5 Serial Adder
C
Shift control CLK
Serial input
SI Shift register A
SI Shift register B
SO ⫽ x
S
J
SO ⫽ y
C K
Clear Fig. 6-6 Second form of Serial Adder
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Parallel outputs A3
Clear
C
D
A2
C
D
A1
C
D
A0
C
D
CLK
S1 S0
4⫻1 MUX 3 2 1 0
4⫻1 MUX 3 2 1 0
4⫻1 MUX 3 2 1 0
4⫻1 MUX 3 2 1 0
Serial input for shift-right I3
I2
I1 Parallel inputs
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Fig. 6-7 4-Bit Universal Shift Register
I0
Serial input for shift-left
A0
T
C R
Count
D
Count
A1
T
D
C R
D
C R
Logic-1 Reset
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
C R
Reset
(a) With T flip-flops
A2
CR
A3
T
A1
CR
A2
T
CR
D
C R
A0
(b) With D flip-flops
Fig. 6-8 4-Bit Binary Ripple Counter
A3
0000
0001
0010
0011
0100
1001
1000
0111
0110
0101
Fig. 6-9 State Diagram of a Decimal BCD-Counter
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Q1
J Count
C K
Q2
J C K
Q4
J C K
Q8
J C K
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Logic-1 Fig. 6-10 BCD Ripple Counter
Q8 Q4 Q2 Q1
Q8 Q4 Q2 Q1
Q 8 Q4 Q 2 Q 1
BCD Counter
BCD Counter
BCD Counter
10 2 digit
101 digit
100 digit
Fig. 6-11 Block Diagram of a Three-Decade Decimal BCD Counter
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Count pulses
J
A0
C Count enable
K
J
A1
C K
J
A2
C K
J
A3
C K
To next stage CLK © 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Fig. 6-12 4-Bit Synchronous Binary Counter
Up
Down
T C
A0
T
A1
C
T C
A2
T
A3
C © 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
CLK Fig. 6-13 4-Bit Up-Down Binary Counter
Count Load I0
J C K
A0
I1
J C K
A1
I2
J C K
A2
I3
J C K
A3
Clear CLK Carry-output © 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Fig. 6-14 4-Bit Binary Counter with Parallel Load
A3 A2 A1 A0
A3 A2 A1 A0
Count ⫽ 1
Load Counter of Fig.6-14
Clear ⫽ 1
Count ⫽ 1
Clear Counter of Fig.6-14
CLK Inputs ⫽ 0
CLK
Inputs have no effect
(a) Using the load input
(b) Using the clear input
Fig. 6-15 Two ways to Achieve a BCD Counter Using a Counter with Parallel Load
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Load ⫽ 0
A
J
B
C
K
J
C
C
K
J
C
K Clock
(a) Logic diagram
000
111
001
110
010
101 100
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Logic-1
011
(b) State diagram Fig. 6-16 Counter with Unused States
T0 T1 T2 T3
2⫻4 decoder Shift right
T0 T1 T2 T3
Count enable
(a) Ring-counter (initial value ⫽ 1000)
2-bit counter (b) Counter and decoder
CLK
T0
T1
T2 T3
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
(c) Sequence of four timing signals Fig. 6-17 Generation of Timing Signals
A
D
B
D
C
C
D
C
C
A⬘
B⬘
E
D C C⬘
CLK (a) Four-stage switch-tail ring counter
Flip-flop outputs
Sequence number
A
B
C
E
AND gate required for output
1 2 3 4 5 6 7 8
0 1 1 1 1 0 0 0
0 0 1 1 1 1 0 0
0 0 0 1 1 1 1 0
0 0 0 0 1 1 1 1
A⬘E⬘ AB⬘ BC⬘ CE⬘ AE A⬘B B⬘C C⬘E
(b) Count sequence and required decoding © 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Fig. 6-18 Construction of a Johnson Counter
E⬘
0ns
20ns
40ns
60ns
80ns
100ns 120ns 140ns 160ns
testcounter.Count testcounter.Reset testcounter.A0 testcounter.A1 testcounter.A2 testcounter.A3 (a) From 0 to 170 ns 72ns
74ns
76ns
78ns
80ns
82ns
84ns
testcounter.Count testcounter.Reset testcounter.A0 testcounter.A1 testcounter.A2 testcounter.A3 (b) From 70 to 92 ns © 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
Fig. 6-19 Simulation Output of HDL Example 6-4
86ns
88ns
90ns
9
Load (L) J CLK
Count (C)
K
Data (I)
Fig. P6-21
© 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
