CSCI 220: Computer Architecture I Instructor: Pranava K. Jha ...
CSCI 220: Computer Architecture I Instructor: Pranava K. Jha Multiplexers Q. Develop a Boolean expression for the function F in terms of the input variables v, w, x, y and z in the following circuit. (E is the “enable” input.)
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Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
All multiplexers are enabled, hence each will respond to the SELECT inputs and data inputs. Let g be the output of the “top left” multiplexer and let h be the output of the “bottom left” multiplexer, and note that g
= 0(w’x’) + 1(w’x) + 1(wx’) + 0(wx) = w’x + wx’, and
h
= v’(w’x’) + v(w’x) + 0(wx’) + 1(wx) = v’w’x’ + vw’x + wx = v’w’x’ + (vw’ + w)x = v’w’x’ + (v + w)x, using absorption theorem, i.e., a+ a’b = a + b = v’w’x’ + vx + wx.
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Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Accordingly, F = g(y’z’) + 0(y’z) + h(yz’) + 1(yz) = (w’x + wx’)y’z’ + (v’w’x’ + vx + wx) yz’ + yz = (w’x + wx’)y’z’ + [(v’w’x’ + vx + wx)z’ + z] y = (w’x + wx’)y’z’ + [(v’w’x’ + vx + wx) + z] y, using absorption theorem = v’w’x’y + vxy + wxy + w’xy’z’ + wx’y’z’ + yz.
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Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Q. The circuit below employs three 4-to-1 multiplexers, where E denotes the Enable input. Develop a Boolean expression for the function F in terms of the input variables v, w, x, y and z. 4-to-1 MUX 1 0 1 0
I0 I1 I2 I3
1
E
f
S1
S0 4-to-1 MUX
w
x
I0 I1 I2 I3
1
E
1
E
1
4-to-1 MUX v 1 v’ 0
0
I0 I1 I2 I3
f
S1
S0
y
z
f
S1
S0
w
x
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F
Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
4-to-1 MUX 1 0 1 0
I0 I1 I2 I3
1
E
f
S1
w’x’ + wx’ = x’
S0 4-to-1 MUX
w
x
4-to-1 MUX v 1 v’ 0
I0 I1 I2 I3
1
E
f
S1
S0
w
x
0
I0 I1 I2 I3
1
E
1
vw’x’ + w’x + v’wx’ = vw’ + w’x + v’wx’
F = x’y’z’ + y’z + (vw’ + w’x + v’wx’)yz’
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f
S1
S0
y
z
F
Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Q. Realize the Boolean function f(w, x, y, z) = Σm(4, 5, 7, 8, 10, 12, 15) using an 8-to-1 multiplexer and an inverter. Let inputs w, x and y appear on the SELECT lines. The canonical truth table and the abridged truth table appear below. Truth table w 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
z 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Abridged truth table f 0 0 0 0 1 1 0 1 1 0 1 0 1 0 0 1
w 0 0 0 0 1 1 1 1
x 0 0 1 1 0 0 1 1
y 0 1 0 1 0 1 0 1
f 0 0 1 z z’ z’ z’ z
Implementation is immediate. 8-to-1 MUX w x y z
S2 S1 S0
•
•
0 0 1 • •
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I0 I1 I2 I3 I4 I5 I6 I7
Y
f
Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Q. Consider the following Boolean function: f(A, B, C, D) = Σm (0, 2, 3, 6, 9, 10, 13, 14). Present an abridged truth table where inputs are deemed to be A, C and D. Truth table
Abridged truth table
A
B
C
D
f
0
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
0
1
1
1
A
C
D
f
0
1
0
0
0
0
0
0
B’
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
0
0
1
1
B’
1
0
0
0
0
1
0
0
0
1
0
0
1
1
1
0
1
1
1
0
1
0
1
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
0
0
0
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
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Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Q. Realize the following Boolean function using 4-to-1 multiplexer and external gates: f(w, x, y, z) = Σm(4, 5, 7, 8, 10, 12, 15). Let w and x appear on the SELECT lines. The truth table and the abridged truth table are immediate.
w 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Truth table y z 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1
Abridged truth table f 0 0 0 0 1 1 0 1 1 0 1 0 1 0 0 1
w 0 0 1 1
x 0 1 0 1
f 0 y’ + z z’ y’z’ + yz
Implementation follows. 4-to-1 MUX w x y z
S1 S0 •
• 0
I0 I1
•
I2 I3
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Y
f
Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Q. 3. [10 points] Present a truth table for the function f(w, x, y, z) = Σ(1, 4, 6, 7, 8, 9, 12), and then derive a condensed truth table where primary variables are y and z, and whose output is in terms of w, x, logical 0 and logical 1. Condensed truth table
Truth table w
x
y
z
f
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
y
z
f
0
1
1
0
1
0
0
w+x
0
1
1
1
1
0
1
x’
1
0
0
0
1
1
0
w’x
1
0
0
1
1
1
1
w’x
1
0
1
0
0
1
0
1
1
0
1
1
0
0
1
1
1
0
1
0
1
1
1
0
0
1
1
1
1
0
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Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Q. Present the truth table of the function F relative to the input variables A, B, C and D in the following circuit.
The following table is immediate. A 0 0 1 1
B 0 1 0 1
F D (C + D)’ CD 1
Detailed truth table follows. A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 10 of 16
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
F 0 1 0 1 1 0 0 0 0 0 0 1 1 1 1 1
Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Q. IC−74153 is a four-input, two-bit multiplexer. Its block diagram and function table appear below. Block diagram
Function table
A
1G’ 0 0 0 0 0 0 0 0 1 1 1 1 1
B 1G’
1G
1Y
1C0 1C1 1C2 1C3 2G’
2G 2C0
Inputs 2G’ B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 ∅
2Y
2C1 2C2 2C3
74x153
A 0 1 0 1 0 1 0 1 0 1 0 1 ∅
Outputs 1Y 2Y 1C0 2C0 1C1 2C1 1C2 2C2 1C3 2C3 1C0 0 1C1 0 1C2 0 1C3 0 0 2C0 0 2C1 0 2C2 0 2C3 0 0
Show how to implement the Boolean function f(w, x, y) = Σm(1, 4, 6, 7) using IC−74153. You may use an external NOT gate and an external OR gate. The area of operation of the function table relevant to the present implementation is highlighted below.
1G’ 0 0 0 0 0 0 0 0 1 1 1 1 1
Inputs 2G’ B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 ∅
A 0 1 0 1 0 1 0 1 0 1 0 1 ∅
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Outputs 1Y 2Y 1C0 2C0 1C1 2C1 1C2 2C2 1C3 2C3 1C0 0 1C1 0 1C2 0 1C3 0 0 2C0 0 2C1 0 2C2 0 2C3 0 0
Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Implementation follows.
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Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Q. Show how to realize an 8-to-1 multiplexer using 4-to-1 multiplexers and 2-to-1 multiplexers. Recall the block diagrams of 2-to-1 MUX, 4-to-1 MUX and 8-to-1 MUX.
I0
1
I1
2
2-to-1 MUX 4
f = S’I0 + SI1
7
g = S1’ S0’J0 + S1’ S0J 1 + S1 S0’J2 + S1 S0 J3
3
S
J0
1
J1
2
J2
3
J3
4
K0
1
K1
2
K2
3
K3
4
K4
5
K5
6
K6
7
K7
8
4-to-1 MUX
5
6
S1
S0
8-to-1 MUX
12
9
10
11
T2
T1
T0
h = T2’ T1’ T0’ K0 + T2’ T1’ T0 K 1 + T2’ T1 T0’ K2 + T2’ T1 T0 K3 + T2 T1’ T0’ K4 + T2 T1’ T0 K 5 + T2 T1 T0’ K6 + T2 T1 T0 K7
Note: Pin numbers have been assigned for ease of implementation.
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Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
It is clear that h = T2’ (T1’ T0’ K0 + T1’ T0 K 1 + T1 T0’ K2 + T1 T0 K3) + T2 (T1’ T0’ K4 + T1’ T0 K 5 + T1 T0’ K6 + T1 T0 K7). A desired implementation is now immediate.
1
4-to-1 MUX
2
K0 K1
7
3 4
5
T1’ T0’ K0 + T1’ T0 K 1 + T1 T0’ K2 + T1 T0 K3
6
K2 K3
1
K4
2
2-to-1 MUX 4
h
3
K5 K6 K7
1
4-to-1 MUX
2
7
3 4
5
• T2
T1
T1’ T0’ K4 + T1’ T0 K 5 + T1 T0’ K6 + T1 T0 K7
6
• T0
Remark: The following tree structure is an abstraction of the preceding implementation. 4-to-1 MUX 2-to-1 MUX 4-to-1 MUX
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Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
There exists another way of realizing an 8-to-1 MUX. To that end, note that h = T2’ T1’ (T0’ K0 + T0 K 1) + T2’ T1 (T0’ K2 + T0 K3) + T2 T1’ (T0’ K4 + T0 K 5) + T2T1 (T0’ K6 + T0 K7).
1 2
K0
1
K1
2
K2 K3
2-to-1 MUX 4 3
T0’ K0 + T0 K 1
2-to-1 MUX 4 3
T0’ K2 + T0 K 3
•
4-to-1 MUX
2
7
3
K4 K5
1
K6 K7
1
2
4
2-to-1 MUX 4 3
5
T0’ K4+ T0 K 5
• 1 2
2-to-1 MUX 4 3
T0’ K6 + T0 K 7
• T2
T1
T0
The tree structure follows. 2-to-1 MUX 2-to-1 MUX 4-to-1 MUX 2-to-1 MUX 2-to-1 MUX
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6
h
Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
An 8-to-1 MUX may as well be implemented by employing 2-to-1 MUXs uniformly. Here is he underlying tree structure.
2-to-1 MUX 2-to-1 MUX 2-to-1 MUX 2-to-1 MUX 2-to-1 MUX 2-to-1 MUX 2-to-1 MUX
The foregoing discussion on tree structures underlying the construction of a large multiplexer using smaller ones admits an elegant generalization. Let n, i and j be positive integers such that n = i + j, so 2n = 2i ⋅ 2 j . A 2n -to-1 MUX is realizable by means of 2i -to-1 MUX ( 2 j nos.) and 2 j -to-1 MUX (1 no.). The schematic follows.
0
2i -to-1 MUX
1
2i -to-1 MUX
# 2 j -1
2 j -to-1 MUX
# 2i -to-1 MUX
Note that if i ≥ 2, then a 2i -to-1 MUX itself is obtainable by means of smaller multiplexers using the same scheme. The tree corresponding to the implementation of a 2n -to-1 multiplexer using 2-to-1 multiplexers is a complete binary tree having 2n – 1 nodes.
——————o——————
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Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
All multiplexers are enabled, hence each will respond to the SELECT inputs and data inputs. Let g be the output of the “top left” multiplexer and let h be the output of the “bottom left” multiplexer, and note that g
= 0(w’x’) + 1(w’x) + 1(wx’) + 0(wx) = w’x + wx’, and
h
= v’(w’x’) + v(w’x) + 0(wx’) + 1(wx) = v’w’x’ + vw’x + wx = v’w’x’ + (vw’ + w)x = v’w’x’ + (v + w)x, using absorption theorem, i.e., a+ a’b = a + b = v’w’x’ + vx + wx.
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Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Accordingly, F = g(y’z’) + 0(y’z) + h(yz’) + 1(yz) = (w’x + wx’)y’z’ + (v’w’x’ + vx + wx) yz’ + yz = (w’x + wx’)y’z’ + [(v’w’x’ + vx + wx)z’ + z] y = (w’x + wx’)y’z’ + [(v’w’x’ + vx + wx) + z] y, using absorption theorem = v’w’x’y + vxy + wxy + w’xy’z’ + wx’y’z’ + yz.
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Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Q. The circuit below employs three 4-to-1 multiplexers, where E denotes the Enable input. Develop a Boolean expression for the function F in terms of the input variables v, w, x, y and z. 4-to-1 MUX 1 0 1 0
I0 I1 I2 I3
1
E
f
S1
S0 4-to-1 MUX
w
x
I0 I1 I2 I3
1
E
1
E
1
4-to-1 MUX v 1 v’ 0
0
I0 I1 I2 I3
f
S1
S0
y
z
f
S1
S0
w
x
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F
Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
4-to-1 MUX 1 0 1 0
I0 I1 I2 I3
1
E
f
S1
w’x’ + wx’ = x’
S0 4-to-1 MUX
w
x
4-to-1 MUX v 1 v’ 0
I0 I1 I2 I3
1
E
f
S1
S0
w
x
0
I0 I1 I2 I3
1
E
1
vw’x’ + w’x + v’wx’ = vw’ + w’x + v’wx’
F = x’y’z’ + y’z + (vw’ + w’x + v’wx’)yz’
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f
S1
S0
y
z
F
Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Q. Realize the Boolean function f(w, x, y, z) = Σm(4, 5, 7, 8, 10, 12, 15) using an 8-to-1 multiplexer and an inverter. Let inputs w, x and y appear on the SELECT lines. The canonical truth table and the abridged truth table appear below. Truth table w 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
z 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Abridged truth table f 0 0 0 0 1 1 0 1 1 0 1 0 1 0 0 1
w 0 0 0 0 1 1 1 1
x 0 0 1 1 0 0 1 1
y 0 1 0 1 0 1 0 1
f 0 0 1 z z’ z’ z’ z
Implementation is immediate. 8-to-1 MUX w x y z
S2 S1 S0
•
•
0 0 1 • •
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I0 I1 I2 I3 I4 I5 I6 I7
Y
f
Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Q. Consider the following Boolean function: f(A, B, C, D) = Σm (0, 2, 3, 6, 9, 10, 13, 14). Present an abridged truth table where inputs are deemed to be A, C and D. Truth table
Abridged truth table
A
B
C
D
f
0
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
0
1
1
1
A
C
D
f
0
1
0
0
0
0
0
0
B’
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
0
0
1
1
B’
1
0
0
0
0
1
0
0
0
1
0
0
1
1
1
0
1
1
1
0
1
0
1
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
0
0
0
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
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Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Q. Realize the following Boolean function using 4-to-1 multiplexer and external gates: f(w, x, y, z) = Σm(4, 5, 7, 8, 10, 12, 15). Let w and x appear on the SELECT lines. The truth table and the abridged truth table are immediate.
w 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Truth table y z 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1
Abridged truth table f 0 0 0 0 1 1 0 1 1 0 1 0 1 0 0 1
w 0 0 1 1
x 0 1 0 1
f 0 y’ + z z’ y’z’ + yz
Implementation follows. 4-to-1 MUX w x y z
S1 S0 •
• 0
I0 I1
•
I2 I3
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Y
f
Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Q. 3. [10 points] Present a truth table for the function f(w, x, y, z) = Σ(1, 4, 6, 7, 8, 9, 12), and then derive a condensed truth table where primary variables are y and z, and whose output is in terms of w, x, logical 0 and logical 1. Condensed truth table
Truth table w
x
y
z
f
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
y
z
f
0
1
1
0
1
0
0
w+x
0
1
1
1
1
0
1
x’
1
0
0
0
1
1
0
w’x
1
0
0
1
1
1
1
w’x
1
0
1
0
0
1
0
1
1
0
1
1
0
0
1
1
1
0
1
0
1
1
1
0
0
1
1
1
1
0
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Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Q. Present the truth table of the function F relative to the input variables A, B, C and D in the following circuit.
The following table is immediate. A 0 0 1 1
B 0 1 0 1
F D (C + D)’ CD 1
Detailed truth table follows. A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 10 of 16
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
F 0 1 0 1 1 0 0 0 0 0 0 1 1 1 1 1
Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Q. IC−74153 is a four-input, two-bit multiplexer. Its block diagram and function table appear below. Block diagram
Function table
A
1G’ 0 0 0 0 0 0 0 0 1 1 1 1 1
B 1G’
1G
1Y
1C0 1C1 1C2 1C3 2G’
2G 2C0
Inputs 2G’ B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 ∅
2Y
2C1 2C2 2C3
74x153
A 0 1 0 1 0 1 0 1 0 1 0 1 ∅
Outputs 1Y 2Y 1C0 2C0 1C1 2C1 1C2 2C2 1C3 2C3 1C0 0 1C1 0 1C2 0 1C3 0 0 2C0 0 2C1 0 2C2 0 2C3 0 0
Show how to implement the Boolean function f(w, x, y) = Σm(1, 4, 6, 7) using IC−74153. You may use an external NOT gate and an external OR gate. The area of operation of the function table relevant to the present implementation is highlighted below.
1G’ 0 0 0 0 0 0 0 0 1 1 1 1 1
Inputs 2G’ B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 ∅
A 0 1 0 1 0 1 0 1 0 1 0 1 ∅
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Outputs 1Y 2Y 1C0 2C0 1C1 2C1 1C2 2C2 1C3 2C3 1C0 0 1C1 0 1C2 0 1C3 0 0 2C0 0 2C1 0 2C2 0 2C3 0 0
Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Implementation follows.
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Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
Q. Show how to realize an 8-to-1 multiplexer using 4-to-1 multiplexers and 2-to-1 multiplexers. Recall the block diagrams of 2-to-1 MUX, 4-to-1 MUX and 8-to-1 MUX.
I0
1
I1
2
2-to-1 MUX 4
f = S’I0 + SI1
7
g = S1’ S0’J0 + S1’ S0J 1 + S1 S0’J2 + S1 S0 J3
3
S
J0
1
J1
2
J2
3
J3
4
K0
1
K1
2
K2
3
K3
4
K4
5
K5
6
K6
7
K7
8
4-to-1 MUX
5
6
S1
S0
8-to-1 MUX
12
9
10
11
T2
T1
T0
h = T2’ T1’ T0’ K0 + T2’ T1’ T0 K 1 + T2’ T1 T0’ K2 + T2’ T1 T0 K3 + T2 T1’ T0’ K4 + T2 T1’ T0 K 5 + T2 T1 T0’ K6 + T2 T1 T0 K7
Note: Pin numbers have been assigned for ease of implementation.
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Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
It is clear that h = T2’ (T1’ T0’ K0 + T1’ T0 K 1 + T1 T0’ K2 + T1 T0 K3) + T2 (T1’ T0’ K4 + T1’ T0 K 5 + T1 T0’ K6 + T1 T0 K7). A desired implementation is now immediate.
1
4-to-1 MUX
2
K0 K1
7
3 4
5
T1’ T0’ K0 + T1’ T0 K 1 + T1 T0’ K2 + T1 T0 K3
6
K2 K3
1
K4
2
2-to-1 MUX 4
h
3
K5 K6 K7
1
4-to-1 MUX
2
7
3 4
5
• T2
T1
T1’ T0’ K4 + T1’ T0 K 5 + T1 T0’ K6 + T1 T0 K7
6
• T0
Remark: The following tree structure is an abstraction of the preceding implementation. 4-to-1 MUX 2-to-1 MUX 4-to-1 MUX
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Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
There exists another way of realizing an 8-to-1 MUX. To that end, note that h = T2’ T1’ (T0’ K0 + T0 K 1) + T2’ T1 (T0’ K2 + T0 K3) + T2 T1’ (T0’ K4 + T0 K 5) + T2T1 (T0’ K6 + T0 K7).
1 2
K0
1
K1
2
K2 K3
2-to-1 MUX 4 3
T0’ K0 + T0 K 1
2-to-1 MUX 4 3
T0’ K2 + T0 K 3
•
4-to-1 MUX
2
7
3
K4 K5
1
K6 K7
1
2
4
2-to-1 MUX 4 3
5
T0’ K4+ T0 K 5
• 1 2
2-to-1 MUX 4 3
T0’ K6 + T0 K 7
• T2
T1
T0
The tree structure follows. 2-to-1 MUX 2-to-1 MUX 4-to-1 MUX 2-to-1 MUX 2-to-1 MUX
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6
h
Computer Architecture-I: Multiplexers (Instructor: Pranava K. Jha)
An 8-to-1 MUX may as well be implemented by employing 2-to-1 MUXs uniformly. Here is he underlying tree structure.
2-to-1 MUX 2-to-1 MUX 2-to-1 MUX 2-to-1 MUX 2-to-1 MUX 2-to-1 MUX 2-to-1 MUX
The foregoing discussion on tree structures underlying the construction of a large multiplexer using smaller ones admits an elegant generalization. Let n, i and j be positive integers such that n = i + j, so 2n = 2i ⋅ 2 j . A 2n -to-1 MUX is realizable by means of 2i -to-1 MUX ( 2 j nos.) and 2 j -to-1 MUX (1 no.). The schematic follows.
0
2i -to-1 MUX
1
2i -to-1 MUX
# 2 j -1
2 j -to-1 MUX
# 2i -to-1 MUX
Note that if i ≥ 2, then a 2i -to-1 MUX itself is obtainable by means of smaller multiplexers using the same scheme. The tree corresponding to the implementation of a 2n -to-1 multiplexer using 2-to-1 multiplexers is a complete binary tree having 2n – 1 nodes.
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