Fixed- and Variable-Length Ring Oscillators for Variability ...
IEEE 2009 Custom Intergrated Circuits Conference (CICC)
Fixed- and Variable-Length Ring Oscillators for Variability Characterization in 45nm CMOS Ji-Hoon Park, Liang-Teck Pang1, Kenneth Duong2, Borivoje Nikolić Electrical Engineering and Computer Sciences, University of California, Berkeley 1 now with IBM T.J. Watson Research Center, 2now with Sun Microsystems, Inc. Abstract- Fixed- and variable-length ring oscillators (RO’s) are designed for characterization of circuit-topology induced variations and spatial correlations. A 930μm × 775μm test array is implemented in a low-power 45nm CMOS process. Measurements from the fixed-length RO’s quantify an increase in variability with transistor stack height in logic gates and added variability associated to the top transistor in the stack. In addition, Variable-length RO’s (VRO’s) are designed to measure spatial correlation with a single-gate resolution.
I. INTRODUCTION With continued technology scaling, the increasing process variation remains a major roadblock in implementing highperformance digital circuits. Various ways of dealing with this problem have been suggested in different levels of abstraction from the architectural [1], the algorithmic [2], down to the circuit [3,4,5] level. On the other hand, the variability has been attributed to intrinsic device and interconnect performance, and layout variations. It has also been attributed in the past to circuit styles [6], but has not been studied in detail. In this work, we systematically characterize the impact of circuit topology on gate delay variability by measuring ring oscillator frequencies. Circuit topology delay dependence has a large impact on critical path monitoring used in adaptive throughput digital systems. Also, spatial correlation of variability greatly affects the use of statistical timing analysis. Although various measurement of the spatial correlation have been reported [7,8], the resolution of the measurements has been either too coarse or too fine to be useful in designing circuits. In this work, a VRO is designed to measure the correlation with a gate-level resolution.
switching order. The gates in the figure are grouped by the number of stacked PMOS and NMOS. Moreover, the top switching configuration is shown in the first column of the table. The number within a small box in the figure designates the index of the inverter. In addition, there are configurations for investigating the effect of pass transistors, layout symmetries, and layout rotation (Fig.3). Each RO is composed of thirteen stages of inverting gates, accompanied with control logic to select and enable a single RO (Fig.5). The stage number of thirteen was chosen to keep the delay contribution of the enabling NAND gate less than 10% of the total delay. The output of the oscillator is multiplexed out to a frequency divider and the divided frequency is measured off-chip [7].
Vertical VRO Rotated VRO RO ARRAY
Horizontal VRO
Fig.1: Chip microphotograph.
Unit inverter Two NMOS stacked
II. TEST STRUCTURE A 930μm × 775μm test array was built in a low-power 45nm CMOS process, consisting of 184 tiles of ROs and VROs. The VROs have three blocks of different implementations to measure the spatial correlation in different directions and gate orientations: 176 tiles of horizontal VROs, 210 tiles of vertical VROs, and 180 tiles of 90o (gate) rotated horizontal VROs (Fig.1). Dummy cells are added along the perimeter of each block to eliminate edge effects from the measurements. A. RO structures A tile of ROs is an aggregation of twenty ROs with inverting gates of different configurations. Fig.2 shows the gates devised to evaluate the effects of transistor stacking and
978-1-4244-4072-6/09/$25.00 ©2009 IEEE
Three NMOS stacked
Two PMOS stacked Two PMOS/ NMOS stacked Fig.2: Test inverters for the effects of transistor stacking and switching order.
T-14-1
519
Differential pass logic 1
Pass transistors
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
Fig.8: Horizontal VRO tile layout.
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
III. MEASUREMENT RESULTS
43 44 45 46 47 48 49 50 51 52 53 54
Symmetric inverters
55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 : measured
Rotated layout
Fig.3: Test inverters for different logic. Fig.4: Dies measured within a wafer.
The oscillating frequency of each RO was measured for more than one hundred cycles and an average value was taken as the frequency of the RO. The mean (µ) and the standard deviation (σ) of the frequencies are calculated over 184 ROs for an identical topology over the wafer. A. RO Frequency Variation Fig.9 shows the normalized σ of the measured frequencies plotted vs. the normalized mean frequency for the different inverter configurations in two dies of corner cases. The plot shows a strong correlation between the mean frequency and the variability of the circuit elements. Also, fig.10 is a plot of the normalized σ of three top switching configurations across all seventeen dies measured. 2
Fig.5: Ring oscillator diagram.
7
A04 (slowest die) B76 (fastest die)
Frequencies of the ring oscillators from seventeen dies, from two positions in the reticle (A and B), scattered across a wafer were measured (Fig.4).
1.5 Normalized σ
B. VRO structure The VRO is devised to measure the spatial correlation with a gate-level resolution. A VRO tile has 26 selectable ring oscillator loops, each of which has different number of stages (Fig.6,8). The length of adjacent loops differs by four unit cells. The unit cell is made to have symmetric input loading (Fig.7) in order to maintain the same delay from either input signals. The horizontal VRO has the NAND gates placed horizontally adjacent to each other whereas the vertical VRO has the same gates placed vertically next to each other. The rotated VRO is a 90o rotated version of the horizontal VRO. In this case, the gates are rotated by 90o.
19
5
1
14 8
15 16
6 8
0.5 0.7
3
4
4 6
2
1 2 18 14
13 18 15 12
3
13 12
9
9
10
16 10
0.8
0.9
1 1.1 1.2 Normalized Mean Freq
1.3
1.4
1.5
Fig.9: Measured σ vs. mean oscillating frequency. A number next to each point indicates the inverter index from Figs.2 and 3.
1.8
Normalized σ
1.6
1.4
1.2
Fig.7: VRO unit cell.
1
5
2
Fig.6: VRO diagram.
7 19
A42 A76 A24 B28 B57 B73 B04 A04 B64 A21 A28 B76 B42 B21 B24 A57 A64
7 77
7 7 77 77 7
7 7 7
7 7 7
1 13 13 1313 13 13
1
13 13 13 13 1313 1313 13 13 13
0.8 1
1.1
1
1 1
1
1
1.2 1.3 Normalized Mean Freq
1
1 1
1 1
1 7
1 1
11
1
1.4
1.5
Fig.10: Measured σ vs. mean oscillating frequency over the wafer.
T-14-2
520
1.15
1.2
13
1.1
Normalized σ / μ
Normalized σ / μ
1
1.05 15 16
9
1
2 3 10 4
0.95 6
0.8
1
1.1
8 9
1.05 1
5
0.95 11
0.85 0.9
1 1.1 1.2 Normailzed Mean Freq
1.3
1.4
N ormalized Ids
Vgs=0.9V Vgs=0.8V
50
Vgs=0.7V Vgs=0.6V Vgs=0.5V
0
0
0.2
0.4
0.6
0.8
1 1.2 Normailzed Mean Freq
1.4
Fig.13: σ/μ plot for different styles.
Bottom Switching Top Switching
100
18
0.8 0.8
1
1.2
Vds Fig.12: Id/Vds trajectories for top and bottom switching of two stacked NMOS’s.
1.05 Normalized σ / μ
B. Transistor Stacking and Switching Order Effects Fig. 11 is a plot of the measured σ/μ of the test structures described in Fig. 2 averaged over the wafer. From the plot, it can be observed that the taller the NMOS stack, the larger the variation. Also, the top switching configurations enclosed in boxes clearly show larger variability, which contributes to about 10% difference in σ/μ for the NMOS case and 3% difference for the PMOS. The PMOS top switching effect is not as pronounced as the NMOS one because of the larger speed gain associated with top switching in PMOS, which is due to the relatively larger internal capacitance of the PMOS stack structure. The increased variability of the top switching configuration can be qualitatively explained by the Id/Vds trajectory of the stacked configuration plotted in Fig.12. The trajectory of Id/Vds of a device during the switching is superimposed upon the Id/Vds characteristic curves of the device in the figure. It can observed that the top switching device clearly remains in the velocity-saturated (low-Vgs, high-Vds) region for a longer portion of its switching time. Because drive current, in this region of operation, has a stronger dependence on Vt, the performance of the top switching stack is more susceptible to process-induced variation in L and Vt.
-50 -0.2
7
5
Fig.11: σ/μ plot of structures from Fig.2.
150
12
0.9 7
0.9 0.7
13
1.15
14
1
3
20 7 19
0.95 0.8
1 1.2 1.4 Normailzed Mean Freq Fig.14: σ/μ plot for layout rotation.
C. Effects of Logic Styles and Layout Rotation Fig.13 is a σ/μ plot for the test structures listed in Fig.3 that represent different logic styles. The differential pass logic has the least variability among all the structures examined, because it has the largest number of devices and the largest output capacitance, which both reduce sensitivity to variability. The relatively low variations of the symmetric inverters can also be explained in a similar way. In addition, as shown in Fig.14, only a minor difference in variability due to the direction of the layout (poly) is observed; inverters with horizontally drawn poly gates show slightly less variability (only 5% different in σ/μ) than normal poly gates largely because of lithography. D. Spatial Correlation Fig.15 shows the measured frequency distribution of VROs from a die. Different oscillating frequencies of individual loops within a VRO tile are clearly discernable. By denoting the oscillating frequency of the ith loop of the jth VRO cell as fi , j , the delay of a unit cell between the ith loop and the (i+1)th loop can be simply expressed as, ti , j = fi +1, j −1 − fi , j −1 .
T-14-3
521
50
longest loop shortest loop
40 Occurrence
Fig. 17 shows the spatial correlation calculated from the measurements and these equations. Except for the negative correlation with the nearest neighbor, attributed to the periodicity in wiring, the spatial correlation is weak for all three configurations of the VROs.
30
IV. CONCLUSION
20
10
0 0.2
0.4
0.6
0.8 1 1.2 1.4 1.6 1.8 Normalized Frequency Fig.15: Oscillating frequency distribution of a horizontal VRO tile.
Fig.16 is a plot of this unit delay measured from a VRO tile. From this data, the covariance of the unit cell delays separated by τ unit cells can be calculated as, C j (τ ) = Ei [(ti +τ , j − E j [ti +τ , j ]) ⋅ (ti , j − E j [ti , j ])] , where E j [⋅] is an expectation operator over j. The spatial
Norm. Unit Delay
correlation can be calculated by the following equation, E [C (τ )] R (τ ) = j j . E j [C j (0)]
1.5
Fixed- and variable-length ring oscillators are designed to evaluate the variability of different circuit topologies and spatial correlation of the variability, respectively, in a lowpower 45nm CMOS process. From the measurement results, it has been observed that the top switching configuration increases the random variation by 10% in the NMOS stack and 3% in the PMOS, compared to the switching of the bottom transistor. This finding has an impact on the design and design margins for circuits used for critical path monitoring in adaptive systems. While it has been measured that NMOS stacking increases the variability, the variation difference from the direction of the poly gate is observed as less than 5%. Also, from the VROs, weak spatial correlation in a gate-level resolution is measured. ACKNOWLEDGMENTS The authors wish to acknowledge the support of the Samsung Scholarship and the Semiconductor Research Corporation program, wafer fabrication donation of STMicroelectronics, and the National Science Foundation Infrastructure Grant No. 0403427. The authors also would like to thank the contributions of students, faculty and member companies of the Berkeley Wireless Research Center. REFERENCES
1
[1] D. Blaauw et al., “Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance,” ISSCC Dig. Tech. Papers, Feb. 2008. [2] R. Hedge, N.R. Shanbhag, “Soft Digital Signal Processing,” IEEE Trans. on VLSI, vol.9, Dec. 2001. [3] X. Liang, D. Brooks, Gu-Yeon Wei, “A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency,” ISSCC Dig. Tech. Papers, Feb. 2008. [4] J.W. Tschanz et al., “Adaptive Body Bias for Reducing Impacts of Die-toDie and Within-Die Parameter Variations on Microprocessor Frequency and Leakage,” IEEE J. Solid-State Circuits, vol. 37, Nov. 2002. [5] T.D.Burd et al, “A Dynamic Voltage Scaled Microprocessor System,” ISSCC Dig. Tech. Papers, Feb. 2000. [6] K.Bernstein et al, “High-Performance CMOS variability in the 65-nm regime and beyond,” IBM J. Research and Development, 2006. [7] L.T. Pang, B. Nikolić, “Impact of layout on 90nm process parameter fluctuations,” VLSI Circ. Dig., 2006. [8] D.Levacq, M. Takamiya, T. Sakurai, “A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000x1 Transistor Arrays in 90nm CMOS,” Proc. IEEE CICC, 2007.
0.5 50 100 150 Cell Index (j)
10
5
15
25
20
Loop Index (i)
Fig.16: Unit delay of a horizontal VRO tile. 1 Horizontal VRO Rotated VRO Vertical VRO
R (τ)
0.5
0
-0.5
0
1
2
3
4
5
6
7
8
9
10
τ in unit cell Fig.17: Spatial correlation of three types of the VRO structures.
T-14-4
522
Fixed- and Variable-Length Ring Oscillators for Variability Characterization in 45nm CMOS Ji-Hoon Park, Liang-Teck Pang1, Kenneth Duong2, Borivoje Nikolić Electrical Engineering and Computer Sciences, University of California, Berkeley 1 now with IBM T.J. Watson Research Center, 2now with Sun Microsystems, Inc. Abstract- Fixed- and variable-length ring oscillators (RO’s) are designed for characterization of circuit-topology induced variations and spatial correlations. A 930μm × 775μm test array is implemented in a low-power 45nm CMOS process. Measurements from the fixed-length RO’s quantify an increase in variability with transistor stack height in logic gates and added variability associated to the top transistor in the stack. In addition, Variable-length RO’s (VRO’s) are designed to measure spatial correlation with a single-gate resolution.
I. INTRODUCTION With continued technology scaling, the increasing process variation remains a major roadblock in implementing highperformance digital circuits. Various ways of dealing with this problem have been suggested in different levels of abstraction from the architectural [1], the algorithmic [2], down to the circuit [3,4,5] level. On the other hand, the variability has been attributed to intrinsic device and interconnect performance, and layout variations. It has also been attributed in the past to circuit styles [6], but has not been studied in detail. In this work, we systematically characterize the impact of circuit topology on gate delay variability by measuring ring oscillator frequencies. Circuit topology delay dependence has a large impact on critical path monitoring used in adaptive throughput digital systems. Also, spatial correlation of variability greatly affects the use of statistical timing analysis. Although various measurement of the spatial correlation have been reported [7,8], the resolution of the measurements has been either too coarse or too fine to be useful in designing circuits. In this work, a VRO is designed to measure the correlation with a gate-level resolution.
switching order. The gates in the figure are grouped by the number of stacked PMOS and NMOS. Moreover, the top switching configuration is shown in the first column of the table. The number within a small box in the figure designates the index of the inverter. In addition, there are configurations for investigating the effect of pass transistors, layout symmetries, and layout rotation (Fig.3). Each RO is composed of thirteen stages of inverting gates, accompanied with control logic to select and enable a single RO (Fig.5). The stage number of thirteen was chosen to keep the delay contribution of the enabling NAND gate less than 10% of the total delay. The output of the oscillator is multiplexed out to a frequency divider and the divided frequency is measured off-chip [7].
Vertical VRO Rotated VRO RO ARRAY
Horizontal VRO
Fig.1: Chip microphotograph.
Unit inverter Two NMOS stacked
II. TEST STRUCTURE A 930μm × 775μm test array was built in a low-power 45nm CMOS process, consisting of 184 tiles of ROs and VROs. The VROs have three blocks of different implementations to measure the spatial correlation in different directions and gate orientations: 176 tiles of horizontal VROs, 210 tiles of vertical VROs, and 180 tiles of 90o (gate) rotated horizontal VROs (Fig.1). Dummy cells are added along the perimeter of each block to eliminate edge effects from the measurements. A. RO structures A tile of ROs is an aggregation of twenty ROs with inverting gates of different configurations. Fig.2 shows the gates devised to evaluate the effects of transistor stacking and
978-1-4244-4072-6/09/$25.00 ©2009 IEEE
Three NMOS stacked
Two PMOS stacked Two PMOS/ NMOS stacked Fig.2: Test inverters for the effects of transistor stacking and switching order.
T-14-1
519
Differential pass logic 1
Pass transistors
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
Fig.8: Horizontal VRO tile layout.
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
III. MEASUREMENT RESULTS
43 44 45 46 47 48 49 50 51 52 53 54
Symmetric inverters
55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 : measured
Rotated layout
Fig.3: Test inverters for different logic. Fig.4: Dies measured within a wafer.
The oscillating frequency of each RO was measured for more than one hundred cycles and an average value was taken as the frequency of the RO. The mean (µ) and the standard deviation (σ) of the frequencies are calculated over 184 ROs for an identical topology over the wafer. A. RO Frequency Variation Fig.9 shows the normalized σ of the measured frequencies plotted vs. the normalized mean frequency for the different inverter configurations in two dies of corner cases. The plot shows a strong correlation between the mean frequency and the variability of the circuit elements. Also, fig.10 is a plot of the normalized σ of three top switching configurations across all seventeen dies measured. 2
Fig.5: Ring oscillator diagram.
7
A04 (slowest die) B76 (fastest die)
Frequencies of the ring oscillators from seventeen dies, from two positions in the reticle (A and B), scattered across a wafer were measured (Fig.4).
1.5 Normalized σ
B. VRO structure The VRO is devised to measure the spatial correlation with a gate-level resolution. A VRO tile has 26 selectable ring oscillator loops, each of which has different number of stages (Fig.6,8). The length of adjacent loops differs by four unit cells. The unit cell is made to have symmetric input loading (Fig.7) in order to maintain the same delay from either input signals. The horizontal VRO has the NAND gates placed horizontally adjacent to each other whereas the vertical VRO has the same gates placed vertically next to each other. The rotated VRO is a 90o rotated version of the horizontal VRO. In this case, the gates are rotated by 90o.
19
5
1
14 8
15 16
6 8
0.5 0.7
3
4
4 6
2
1 2 18 14
13 18 15 12
3
13 12
9
9
10
16 10
0.8
0.9
1 1.1 1.2 Normalized Mean Freq
1.3
1.4
1.5
Fig.9: Measured σ vs. mean oscillating frequency. A number next to each point indicates the inverter index from Figs.2 and 3.
1.8
Normalized σ
1.6
1.4
1.2
Fig.7: VRO unit cell.
1
5
2
Fig.6: VRO diagram.
7 19
A42 A76 A24 B28 B57 B73 B04 A04 B64 A21 A28 B76 B42 B21 B24 A57 A64
7 77
7 7 77 77 7
7 7 7
7 7 7
1 13 13 1313 13 13
1
13 13 13 13 1313 1313 13 13 13
0.8 1
1.1
1
1 1
1
1
1.2 1.3 Normalized Mean Freq
1
1 1
1 1
1 7
1 1
11
1
1.4
1.5
Fig.10: Measured σ vs. mean oscillating frequency over the wafer.
T-14-2
520
1.15
1.2
13
1.1
Normalized σ / μ
Normalized σ / μ
1
1.05 15 16
9
1
2 3 10 4
0.95 6
0.8
1
1.1
8 9
1.05 1
5
0.95 11
0.85 0.9
1 1.1 1.2 Normailzed Mean Freq
1.3
1.4
N ormalized Ids
Vgs=0.9V Vgs=0.8V
50
Vgs=0.7V Vgs=0.6V Vgs=0.5V
0
0
0.2
0.4
0.6
0.8
1 1.2 Normailzed Mean Freq
1.4
Fig.13: σ/μ plot for different styles.
Bottom Switching Top Switching
100
18
0.8 0.8
1
1.2
Vds Fig.12: Id/Vds trajectories for top and bottom switching of two stacked NMOS’s.
1.05 Normalized σ / μ
B. Transistor Stacking and Switching Order Effects Fig. 11 is a plot of the measured σ/μ of the test structures described in Fig. 2 averaged over the wafer. From the plot, it can be observed that the taller the NMOS stack, the larger the variation. Also, the top switching configurations enclosed in boxes clearly show larger variability, which contributes to about 10% difference in σ/μ for the NMOS case and 3% difference for the PMOS. The PMOS top switching effect is not as pronounced as the NMOS one because of the larger speed gain associated with top switching in PMOS, which is due to the relatively larger internal capacitance of the PMOS stack structure. The increased variability of the top switching configuration can be qualitatively explained by the Id/Vds trajectory of the stacked configuration plotted in Fig.12. The trajectory of Id/Vds of a device during the switching is superimposed upon the Id/Vds characteristic curves of the device in the figure. It can observed that the top switching device clearly remains in the velocity-saturated (low-Vgs, high-Vds) region for a longer portion of its switching time. Because drive current, in this region of operation, has a stronger dependence on Vt, the performance of the top switching stack is more susceptible to process-induced variation in L and Vt.
-50 -0.2
7
5
Fig.11: σ/μ plot of structures from Fig.2.
150
12
0.9 7
0.9 0.7
13
1.15
14
1
3
20 7 19
0.95 0.8
1 1.2 1.4 Normailzed Mean Freq Fig.14: σ/μ plot for layout rotation.
C. Effects of Logic Styles and Layout Rotation Fig.13 is a σ/μ plot for the test structures listed in Fig.3 that represent different logic styles. The differential pass logic has the least variability among all the structures examined, because it has the largest number of devices and the largest output capacitance, which both reduce sensitivity to variability. The relatively low variations of the symmetric inverters can also be explained in a similar way. In addition, as shown in Fig.14, only a minor difference in variability due to the direction of the layout (poly) is observed; inverters with horizontally drawn poly gates show slightly less variability (only 5% different in σ/μ) than normal poly gates largely because of lithography. D. Spatial Correlation Fig.15 shows the measured frequency distribution of VROs from a die. Different oscillating frequencies of individual loops within a VRO tile are clearly discernable. By denoting the oscillating frequency of the ith loop of the jth VRO cell as fi , j , the delay of a unit cell between the ith loop and the (i+1)th loop can be simply expressed as, ti , j = fi +1, j −1 − fi , j −1 .
T-14-3
521
50
longest loop shortest loop
40 Occurrence
Fig. 17 shows the spatial correlation calculated from the measurements and these equations. Except for the negative correlation with the nearest neighbor, attributed to the periodicity in wiring, the spatial correlation is weak for all three configurations of the VROs.
30
IV. CONCLUSION
20
10
0 0.2
0.4
0.6
0.8 1 1.2 1.4 1.6 1.8 Normalized Frequency Fig.15: Oscillating frequency distribution of a horizontal VRO tile.
Fig.16 is a plot of this unit delay measured from a VRO tile. From this data, the covariance of the unit cell delays separated by τ unit cells can be calculated as, C j (τ ) = Ei [(ti +τ , j − E j [ti +τ , j ]) ⋅ (ti , j − E j [ti , j ])] , where E j [⋅] is an expectation operator over j. The spatial
Norm. Unit Delay
correlation can be calculated by the following equation, E [C (τ )] R (τ ) = j j . E j [C j (0)]
1.5
Fixed- and variable-length ring oscillators are designed to evaluate the variability of different circuit topologies and spatial correlation of the variability, respectively, in a lowpower 45nm CMOS process. From the measurement results, it has been observed that the top switching configuration increases the random variation by 10% in the NMOS stack and 3% in the PMOS, compared to the switching of the bottom transistor. This finding has an impact on the design and design margins for circuits used for critical path monitoring in adaptive systems. While it has been measured that NMOS stacking increases the variability, the variation difference from the direction of the poly gate is observed as less than 5%. Also, from the VROs, weak spatial correlation in a gate-level resolution is measured. ACKNOWLEDGMENTS The authors wish to acknowledge the support of the Samsung Scholarship and the Semiconductor Research Corporation program, wafer fabrication donation of STMicroelectronics, and the National Science Foundation Infrastructure Grant No. 0403427. The authors also would like to thank the contributions of students, faculty and member companies of the Berkeley Wireless Research Center. REFERENCES
1
[1] D. Blaauw et al., “Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance,” ISSCC Dig. Tech. Papers, Feb. 2008. [2] R. Hedge, N.R. Shanbhag, “Soft Digital Signal Processing,” IEEE Trans. on VLSI, vol.9, Dec. 2001. [3] X. Liang, D. Brooks, Gu-Yeon Wei, “A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency,” ISSCC Dig. Tech. Papers, Feb. 2008. [4] J.W. Tschanz et al., “Adaptive Body Bias for Reducing Impacts of Die-toDie and Within-Die Parameter Variations on Microprocessor Frequency and Leakage,” IEEE J. Solid-State Circuits, vol. 37, Nov. 2002. [5] T.D.Burd et al, “A Dynamic Voltage Scaled Microprocessor System,” ISSCC Dig. Tech. Papers, Feb. 2000. [6] K.Bernstein et al, “High-Performance CMOS variability in the 65-nm regime and beyond,” IBM J. Research and Development, 2006. [7] L.T. Pang, B. Nikolić, “Impact of layout on 90nm process parameter fluctuations,” VLSI Circ. Dig., 2006. [8] D.Levacq, M. Takamiya, T. Sakurai, “A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000x1 Transistor Arrays in 90nm CMOS,” Proc. IEEE CICC, 2007.
0.5 50 100 150 Cell Index (j)
10
5
15
25
20
Loop Index (i)
Fig.16: Unit delay of a horizontal VRO tile. 1 Horizontal VRO Rotated VRO Vertical VRO
R (τ)
0.5
0
-0.5
0
1
2
3
4
5
6
7
8
9
10
τ in unit cell Fig.17: Spatial correlation of three types of the VRO structures.
T-14-4
522
