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Microelectronics Journal 39 (2008) 1663–1670 www.elsevier.com/locate/mejo
Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation Rodrigo Trevisoli Doriaa,, Antonio Cerdeirab, Jean-Pierre Raskinc, Denis Flandred, Marcelo Antonio Pavanelloa,e a
Departamento de Engenharia Ele´trica, Centro Universita´rio da FEI, Av. Humberto de Alencar Castelo Branco, 3972, CEP 09850-901, Sa˜o Bernardo do Campo, Brazil b Seccı´on de Electro´nica del Estado So´lido (SEES), CINVESTAV, Mexico c Laboratoire d’Hyperfre´quences, Universite´ Catholique de Louvain, Belgium d Laboratoire de Microe´lectronique, Universite´ Catholique de Louvain, Belgium e Laborato´rio de Sistemas Integra´veis, Escola Polite´cnica da Universidade de Sa˜o Paulo, Sa˜o Paulo, Brazil Received 6 December 2007; accepted 7 February 2008 Available online 2 April 2008
Abstract In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-around (GAA) devices operating in saturation region for analog applications. The study has been performed through device characterization and two-dimensional process and device simulations. The overall study has been done on the total and third order HDs. When applied in the saturation regime as an amplifier, the GC outperforms conventional GAA transistors presenting simultaneously higher transconductance, lower drain output conductance and more than 15 dB improved linearity. The influence of channel length reduction on the HD is also analyzed. Although slight linearity degradation is observed in both the conventional and the GC devices when reducing the channel length, the HD presented by the GC transistor is significantly lower than the one showed by conventional device for any studied channel length. This allows AC input signal amplitude up to 20 times higher than the conventional GAA for a same specified distortion level. r 2008 Elsevier Ltd. All rights reserved. Keywords: Silicon-on-insulator; Channel engineering; Graded-channel; Double gate; Gate-all-around; Asymmetric MOSFET; Harmonic distortion; Nonlinearity
1. Introduction The very high performance of SOI MOS transistors in analog applications such as operational amplifiers [1] and continuous-time filters [2] has long been demonstrated. These applications require devices with a satisfactory linear response, since the non-linear characteristic of the MOSFETs is frequently considered as a circuit bottleneck contributing for the poor quality of the output signal. Thus, the choice of the device is essential. Double gate (DG) SOI MOSFETs appear as a good alternative for such low-power low-voltage applications, since the presence of Corresponding author. Tel.: +55 11 4353 2900x2067; fax: +55 11 4109 5994. E-mail addresses: [email protected], [email protected] (R.T. Doria).
0026-2692/$ - see front matter r 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2008.02.006
two gates improves the gate control on the channel charges leading to nearly ideal body factor [3]. In our study, we have worked with DG gate-all-around (GAA) MOS transistors that feature a channel region surrounded by gate material and gate oxide. Since the channel widths (a few mm) of the GAA under analysis in this work are much bigger than the channel thickness (80 nm), the contribution of the current flow due to the vertical channels is negligible and thus GAA devices behave as symmetric DG transistors. According to Ref. [4], GAA devices have proven to be advantageous with respect to conventional single gate (SG) devices for several reasons, such as volume inversion, improved transconductance, nearly ideal sub-threshold slope and higher gain. It is known that in the GAA devices the transconductance can be over twice larger than in the SG transistors thanks to the
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lower mobility degradation provided by the volume inversion [3]. However, for the current study the volume inversion effect can only be observed in the vicinity of the threshold voltage. In order to obtain higher volume inversion contribution, thinner silicon layer devices should be used [5,6]. A new MOSFET architecture called graded-channel (GC) has been proposed in Ref. [7] with the purpose of reducing inherent bipolar effects exhibited in fully depleted uniformly doped SOI MOSFETs. The GC device is obtained thanks to a special arrangement in one of the masks of the conventional CMOS process, such that the threshold voltage implantation is not performed in the channel region near the drain. Consequently, this region (with length LLD) remains lightly doped with the initial wafer concentration and can be considered as an extension of the drain, whereas the rest of the channel controls the overall threshold voltage. For this reason, the effective channel length (Leff) can be approximated to the difference between the total channel length (L) and the length of the lightly doped region (Leff ¼ LLLD) in saturation. The GC device architecture has been successfully applied in DG configuration demonstrating extraordinary improvements in relation to the conventional ones (i.e. with uniformly doped channel), when operating as amplifiers [4,8,9]. This occurs because when the device is in saturation regime, the majority of the potential applied to the drain is absorbed in the interior of LLD region. Thus, the variation of the drain voltage that reaches the implanted channel region (which predominantly governs the drain current) is greatly reduced, appreciably improving the drain output conductance, and thereby leading to an extraordinary intrinsic voltage gain [9]. On the other hand, results of interest have also been reported for GC devices operating as tunable resistors in Ref. [10] demonstrating the potential of this channel engineering to be applied in low distortion MOSFET-C continuous-time filters. Other similar asymmetric MOSFETs have been studied in Refs. [11,12] also showing excellent analog performances. This paper proposes an evaluation of the performance of DG GC transistors made using the GAA device architecture (GC GAA), shown in Fig. 1, from the distortion perspective. The harmonic distortion (HD) corresponds to the non-linearities inherently exhibited in the output L LLD PolySi Gate Source N+
P+
P-
Gate Oxide Drain N+
PolySi Gate Buried Oxide Fig. 1. Cross-section of a graded-channel GAA SOI MOSFET.
current of transistors, resulting in the presence of signals whose frequencies differ from the input signal. Consequently, total HD (THD) and third order HD (HD3) have been taken as figures of merit. Second order HD (HD2) will not be discussed since this figure of merit is quite similar to THD in the analyzed regime of operation [13]. The distortion has been determined through the integral function method (IFM) once this technique permits the distortion extraction from DC measurements without the need of an AC characterization, contrary to Fourier based methods [14], for instance. The linearity properties of GC GAA will be investigated in relation to conventional GAA transistors in saturation regime. In this analysis the SOI MOSFET operates as a single transistor amplifier and the HD is determined for several LLD/L ratios. Channel length reduction influence on linearity will also be taken under consideration. For high analog performance in baseband applications, long channel MOSFETs are selected [15]. In order to perform the proposed analyses, this paper is organized as follows. Section 2 describes the fabrication characteristics of the measured transistors and the simulations. In Section 3 the analog performance is explored in the saturation regime. Section 4 discusses the origin of the non-linearities obtained. Finally, Section 5 points out the conclusions of this work. 2. Devices and simulations characteristics The measured GC GAA transistors have been fabricated according to the process described in Ref. [16]. The referred process has been optimized for analog baseband and instrumentation circuits. It uses UNIBOND wafers with an initial boron concentration of 1015 cm3 with 390 nm thick buried oxide. Devices with three parallel fingers, each one with L ¼ W ¼ 3 mm (where W is the channel width), have been made with several LLD/L ratios. The final thicknesses of the gate oxide and silicon film are 30 and 80 nm, respectively. The final doping level in the threshold voltage (VTH) adjust implanted region is in the order of 1017 cm3. Coupled process and device bi-dimensional numerical simulations have been performed through the Athena [17] and the Atlas [18] tools, respectively, for devices with dimensions similar to those experimentally measured. The simulations have taken into account models for bandgap narrowing, impact ionization, doping-dependent carrier lifetime and mobility degradation with vertical and lateral electric fields. Except for the maximum values of electrons and holes low field mobility of the Klaassen model, which have been set to 510 and 170 cm2/V s, respectively, default simulator coefficients were used. Uniformly doped GAA transistors that received the VTH implantation in the entire channel, hereafter called conventional GAA, were also simulated to allow for a performance comparison. The HD was determined through the application of the IFM to the transfer characteristics of the drain current as a function of gate voltage (IDSVGS) curves at fixed drain
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bias (VDS). For this analysis, the IFM calculation considered an equivalent input sinusoidal signal of amplitude Va added to the bias voltage (VGT ¼ VGSVTH, where VTH is the threshold voltage), i.e. emulating VGS ¼ VGT+Va sin(x) with x between 0 and 2p. 3. HD evaluation for devices operating in saturation region Aiming at the determination of the HD, the transfer characteristics IDS versus VGT at VDS ¼ 1.5 V were obtained for measured and simulated devices and are exhibited in Fig. 2. From the presented curves we can see the excellent agreement between both simulated and measured curves independently of GC GAA LLD/L ratio. The transconductance (gm), low-frequency open-loop voltage gain (AV) and the early voltage (VEA) were also extracted from the devices characteristics. When devices operate in saturation as for amplifiers, AV depends on the bias conditions and influences the HD performance. Considering that, AV has been simulated for devices of 1 and 3 mm gate lengths with several LLD/L ratios, as shown in Fig. 3. As expected, any GC studied device presents much larger AV than the conventional transistors with similar physical gate length (L) as also demonstrated in Refs. [4,9]. Among the GC GAA transistors, as the effective channel length is diminished through the increase of LLD/L, the gain suffers a degradation, as the drain conductance rises for smaller effective channel lengths [19]. The gain also degrades as L is downscaled independently of the channel architecture, as demonstrated in Fig. 3. The HD was firstly determined at fixed amplitude Va of 50 mV and varying the gate bias. The results of the obtained THD and HD3 for gm/IDS ¼ 3.5 V1 in strong inversion are shown in Table 1 for measured and simulated devices of various LLD/L ratios. As stated in Ref. [20] the
Fig. 3. Curves of AV versus gm/IDS for simulated conventional and GC GAA MOSFETs with gate lengths of (A) 1 mm and (B) 3 mm (VDS ¼ 1.5 V).
Table 1 Extracted and simulated values for AV, THD, HD3, THD/AV and HD3/ AV at VGT ¼ 500 mV, gm/IDS ¼ 3.5 V1, VDS ¼ 1.5 V and Va ¼ 50 mV (L ¼ 3 mm) THD Device L ¼ 3 mm AV (dB) (dB) LLD/L LLD/L 0.2 0.4 0.2 Experiment Simulation
Fig. 2. Curves of IDS versus VGT for measured and simulated GC GAA devices with total gate lengths (L) of 3 mm and various low-doped drain extension (LLD) over L ratios (VDS ¼ 1.5 V).
0.4
HD3 (dB) LLD/L
THD/AV (dB) LLD/L
0.2 0.4 0.2
0.4
HD3/AV (dB) LLD/L 0.2
0.4
76 62 34 35 73 71 105 95 144 130 72 62 35 37 77 76 106 97 149 136
differences on AV demonstrated in Fig. 3 can influence the HD characteristics, such that THD and HD3 were divided by the gain in the saturation region analysis generating the new figures of merit THD/AV and HD3/AV to allow for a fair comparison. The measured values for AV, THD/AV and HD3/AV are also given in Table 1, for devices with
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total gate length of 3 mm and various LLD/L ratios. As shown in Table 1 and in Fig. 2, the good agreement obtained between simulated and measured results for both IDS versus VGT characteristics and HD values validate the performed simulations. Thus, calibrated process-device simulation data will be used to determine the channel length influence on linearity properties of GC GAA devices, which allows not only for extending the set of LLD/L ratios under study, but also for comparing the results with uniformly doped, conventional GAA transistors. For the evaluation of the linearity, transistors of 1 and 3 mm channel lengths had their HD determined as a function of gm/IDS. According to the results obtained for THD in Fig. 4(A), as the LLD/L ratio increases the linearity improves and for the device with LLD/L ¼ 0.6, an advantage of 4 dB is obtained. The negative peaks observed
for all devices THD at gm/IDSffi1.25 V1 have been verified to correspond to the inflexion in the drain current where the devices start to operate in the triode regime; so this region of the curves is not relevant to the amplifier applications. On the other hand, the HD3 analysis shows a degradation of the linearity when increasing LLD/L as shown in Fig. 4(B). This degradation can be superior to 10 dB for devices with higher LLD/L, depending on the gm/IDS observed. However, as HD3 is not dominant for the analysis of one transistor amplifier in saturation, because THDffiHD2 is greater than HD3 by least in 20 dB, the rise in this distortion does not present significant influence in THD. Even in a differential operational amplifier in which HD3 would become dominant, the degradation observed on HD3 when increasing LLD/L shall be analyzed more carefully since the different AV among the devices influence the linearity. Thus, the HD3/AV figure for the linearity shall be verified. Devices of L ¼ 1 mm presented similar results showing reduction on THD and degradation on HD3 as LLD/L rises. When compared to 3 mm-long transistors, the smaller devices exhibit similar THD and a slight degradation on HD3. 4. Discussion The results obtained for HD2 (ffiTHD) and HD3 can be explained through the expressions (1) and (2) extracted from Ref. [21], which are valid for low signal amplitude Va. According to these equations, the HD is a function of the transconductance and its derivatives.
Fig. 4. Simulated curves of (A) THD and (B) HD3 as a function of gm/IDS for the GAA and GC GAA devices (VDS ¼ 1.5 V and Va ¼ 50 mV).
1 ðdgm =dV GT Þ HD2 ¼ Va , 2 2gm
(1)
1 ðd2 gm =dV 2GT Þ HD3 ¼ Va2 . 4 6gm
(2)
This way, considering the input signal amplitude Va constant, HD2 is dependent on the first derivative of gm and HD3 on the second. By calculating the HD it is possible to observe that the shape of the final HD2 curves is mainly governed by the derivative of gm as exhibited in Fig. 5(A) for devices of L ¼ 3 mm, and the linear increase of the transconductance with LLD as in Fig. 5(B). Since HD2 dominates the distortion in the saturation analysis, the improvement observed on THD due to the GC architecture in Fig. 4(A) is derived from the higher increase in gm obtained for gm/IDS between 2 and 5 V1 (VGT between 0.3 and 0.7 V) thanks to the smaller effective channel length, which is clearly shown in the derivative of gm. As mentioned, the shape of the final HD2 curves is indeed essentially given by dgm/dVGT divided by 2gm. As the levels of both dgm/dVGT and gm curves tends to increase as LLD/L, the higher linearity exhibited by the GC devices is determined through the greater increase observed for the transconductance in relation to the one obtained by
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the necessary overdrive voltage to reach the linear region slightly reduces when increasing LLD/L, which moves the negative peaks to larger gm/IDS. As previously mentioned, GC devices with different LLD/L ratios present distinct open-loop gain. Since AV can influence the HD, to fairly compare the results of HD3 and THD obtained for devices with different LLD/L ratios operating as single-transistor amplifiers in the unity-gain configuration; these figures of merit were divided by AV yielding the new figures of merit THD/AV and HD3/AV. Thus, the curves of THD/AV and HD3/AV are plotted in Fig. 6 as a function of the transconductance-to-drain ratio, which then yields the current required to obtain a given linearity level for a determined gain-bandwidth product (i.e. GBW ¼ gm/CL ¼ (gm/IDS)*(IDS/CL), where CL is the load) [23]. Although linearity degradation is observed when reducing the devices channel length, both 1 and 3 mm long GC devices present great improvement on THD/AV. When compared to the conventional, the shorter GC device of
Fig. 5. Simulated curves of (A) qgm/qVGT versus gm/IDS and (B) gm versus gm/IDS for devices of 3 mm channel length at VDS ¼ 1.5 V.
the gm derivative. Similarly, as presented in Eq. (2), the shape of HD3 is mainly determined by d2gm/dV2GT divided by 6gm, including the negative peaks presented in Fig. 4(B) which occur at dgm/dVGT ¼ 0. In this case, d2gm/dV2GT also rises as LLD/L. However, the division of the second derivative of gm by 6gm does not present enough influence on HD3 to improve the linearity. Except in the peak region, which is shifted to the right (this is an advantage if the sweet spot, i.e. optimal range, is obtained for more practical gm/IDS around 10 V1). HD3 worsens as LLD/L is increased. The negative peaks exhibited in the HD3 curves for the 3 mm-long devices are coincident with either maximum or minimum points in the dgm/dVGT curves [13]. These negative peaks move to larger gm/IDS as the LLD/L ratio increases owing to the fact that in saturation the lightly doped region of the devices is pinched off, and for that reason absorbs part of the applied VDS [22]. Consequently,
Fig. 6. Simulated THD/AV versus gm/IDS curves for channel lengths of (A) 1 mm and (B) 3 mm (VDS ¼ 1.5 V and Va ¼ 50 mV).
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LLD/L ¼ 0.4 shows an improvement of 20 dB, while the longer one for LLD/L ¼ 0.2 presents a THD/AV 33 dB better than the conventional device of same physical dimensions at gm/IDS ¼ 3.5 V1, i.e. in strong inversion. The excellent values obtained for THD/AV at gm/IDS ratios between 3 and 5 V1, mainly for the longer device, are derived from the better THD presented by these devices in Fig. 4(A) associated to the greater gain provided by the GC structure in this bias region. Although HD3 is not the predominant distortion in the current analysis, the curves of HD3/AV as a function of gm/ IDS shown in Fig. 7 state that all GC transistors under study show better performance than the conventional ones. The 1 mm-long device with LLD/L ¼ 0.4 presents an improvement of 15 dB at gm/IDS between 3 and 10 V1 and the 3 mm-long transistor with LLD/L ¼ 0.2 shows 25 dB improvement at gm/IDS ratios in the left side of the observed negative peaks. For the 1 mm-long devices, the
negative peaks occur at gm/IDS ratios greater than 10 V1 and, for that reason, are not exhibited in the figure. Nevertheless, the present work results diverge from the ones reported in Ref. [24] for DG FinFETs. The referred study presents an improvement in THD/AV as gm/IDS is increased for devices of any L. So that, the study carried out on the mentioned reference shows better linearity properties for higher gm/IDS ratios and worse HD at lower gm/IDS for any analyzed device. Apparently, the differences obtained for THD/AV in both studies are related to the higher doping concentration (6 1017 cm3) of the FinFET devices and to the mobility variation. Fig. 8 shows the curves of THD/AV and HD3/AV as a function of the devices channel length at gm/IDS ¼ 3 V1. Similar behavior is obtained for any gm/IDS from 2 to 10 V1. For majority of the analyzed devices, the obtained curves present a small degradation when reducing the channel length. The only exceptions are the shorter devices with LLD/L ¼ 0.1 and 0.2, which exhibit a larger degradation since their lightly doped regions do not reach the wafer doping level due to the lateral diffusion of VTH implanted impurities. In order to evaluate the analog performance of GC GAA SOI nMOSFETs as a function of the sinusoidal input amplitude Va, we considered a fixed bias of gm/IDS ¼ 5 V1 which represents a fixed bias voltage VGT around 0.35 V. Through the curves of THD/AV versus Va, the determination of the maximum input signal amplitude Va for a given distortion level is allowed. Thus, the designer is able to choose the device that best fits the desired operation conditions searching for the optimal relation between HD and device channel length for the required Va. The maximum Va amplitudes to obtain targeted THD/AV between 70 and 80 dB is presented in Table 2. The exhibited evaluation has been obtained for sinusoidal input amplitudes varying between 0.01 and 1.0 V and, as expected, has shown remarkable improvements when the GC architecture is applied. The italic values in the table
Fig. 7. Simulated HD3/AV versus gm/IDS curves for channel lengths of (A) 1 mm and (B) 3 mm (VDS ¼ 1.5 V and Va ¼ 50 mV).
Fig. 8. Simulated THD/AV and HD3/AV as a function of channel length for gm/IDS ¼ 3 V1.
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Table 2 Maximum amplitude Va of the sinusoidal input to attain the target distortion THD/AV Target THD/AV (dB)
Max Va (V) conv. GAA
Max Va (V), GC GAA—LLD/L 0.1
0.2
0.3
0.4
0.5
0.6
L 1 mm
80 75 70
o0.010 o0.010 0.014
o0.010 0.010 0.019
0.015 0.026 0.045
0.033 0.058 0.103
0.048 0.085 0.150
0.044 0.077 0.137
0.030 0.052 0.093
L 2 mm
80 75 70
o0.010 0.016 0.026
0.030 0.055 0.094
0.141 0.254 0.474
0.159 0.287 0.546
0.125 0.223 0.404
0.094 0.166 0.291
0.064 0.113 0.196
L 3 mm
80 75 70
0.016 0.025 0.039
0.166 0.300 0.573
0.378 0.761 41.000
0.305 0.592 41.000
0.255 0.473 41.000
0.148 0.263 0.471
0.125 0.216 0.367
Italic values represent the cases in which the maximum Va allowed in the GC device is greater than one order of magnitude in relation to the conventional one.
highlights the devices for which the permitted input amplitude Va at the specified distortion level in the asymmetric device is greater by one order of magnitude compared to the conventional one (uniformly doped channel). For devices with L ¼ 3 mm and LLD/L between 0.2 and 0.4, the targeted THD/AV of 70 dB is attained for any input amplitude under study, while for the shorter conventional devices THD/AV is always superior than 75 dB. Considering that the high voltage gain of GC transistors is higher than 20 dB, results shown in Table 2 indicates that targeted distortion level can be achieved in all the practical dynamic range of transistor operation. 5. Conclusions This work analyzes the interest of DG GC devices for analog applications in saturation regime for devices operating as amplifiers. THD, HD3, THD/AV and HD3/AV were taken as the figures of merit. According to the results, the use of GC architecture improves remarkably the linearity on the output signal. Depending on the length of lightly doped channel region (LLD/L), 3 mm-long GC devices presented a reduction on THD/AV that reaches 30 dB. Although the linearity degradation observed when reducing the channel length, any GC device shows better results for HD3 and THD by up to 10 dB. Moreover, this work demonstrates that the GC configuration relaxes the constraint on the input signal amplitude for a requested distortion level. DG GC devices with LLD/L from 0.2 to 0.4 allow AC input signal amplitude up to 20 times higher than the conventional GAA for a same specified distortion level. Acknowledgments Rodrigo T. Doria and Marcelo A. Pavanello acknowledge the Brazilian research-funding agencies CAPES, CNPq and FAPESP for the financial support. Denis Flandre is Honorary Senior Research Associate of the
FRS-FNRS, Belgium. The authors thank the UCL micronano-infrastructure technical staff for device fabrication.
References [1] D. Flandre, J.P. Colinge, J. Chen, D. De Ceuster, J.P. Eggermont, L. Ferreira, B. Gentinne, P.G.A. Jespers, A. Viviani, R. Gillon, J.P. Raskin, A. Vander Vorst, D. Vanhoenacker-Janvier, F. Silveira, Fully-depleted SOI CMOS technology for low-voltage low-power mixed digital/analog/microwave circuits, Analog Integrated Circuits Signal Process. 21 (1999) 213–228. [2] D. Flandre, L.F. Ferreira, P.G.A. Jespers, J.P. Colinge, Modeling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits, Solid-State Electron. 39 (4) (1996) 455–460. [3] J.P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Kluwer Academic Publishers, Dordrecht, 1991. [4] A. Kranti, T.M. Chung, D. Flandre, J.P. Raskin, Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications, Solid-State Electron. 48 (6) (2004) 947–959. [5] T. Rudenko, N. Collaert, S. De Gendt, V. Kilchytska, M. Jurczak, D. Flandre, Effective mobility in FinFET Structures with HfO2 and SiON gate dielectrics and TaN gate electrode, Microelectron. Eng. 80 (2005) 386–389. [6] J.P. Raskin, T.M. Chung, V. Kilchytska, D. Lederer, D. Flandre, Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization, IEEE Trans. Electron Devices 53 (5) (2006) 1088–1095. [7] M.A. Pavanello, J.A. Martino, D. Flandre, Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects, Solid-State Electron. 44 (6) (2000) 917–922. [8] R.T. Doria, M.A. Pavanello, A. Cerdeira, J.P. Raskin, D. Flandre, Channel length reduction influence on harmonic distortion of gradedchannel gate-all-around devices, in: 21st Symposium on Microelectronics Technology and Devices, 2006, pp. 247–256. [9] M.A. Pavanello, J.A. Martino, J.-P. Raskin, D. Flandre, High performance analog operation of double-gate transistors with graded-channel architecture at low temperatures, Solid-State Electron. 49 (10) (2005) 1569–1575. [10] A. Cerdeira, M.A. Alema´n, M.A. Pavanello, J.A. Martino, L. Vancaillie, D. Flandre, Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor, IEEE Trans. Electron Devices 52 (5) (2005) 967–972.
ARTICLE IN PRESS 1670
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[11] M.A. Pavanello, J.A. Martino, D. Flandre, Analog circuit design using graded-channel SOI nMOSFETs, Solid-State Electron. 46 (8) (2002) 1215–1225. [12] S.P. Gimenez, M.A. Pavanello, J.A. Martino, D. Flandre, Gain improvement in operational transconductance amplifiers using gradedchannel SOI nMOSFETs, Microelectron. J. 37 (1) (2006) 31–37. [13] A. Cerdeira, M. Estrada, R. Quintero, D. Flandre, A. Ortiz-Conde, F.J. Garcı´ a Sa´nchez, New method for determination of harmonic distortion in SOI FD transistors, Solid-State Electron. 46 (1) (2002) 103–108. [14] A. Cerdeira, M.A. Alema´n, M. Estrada, D. Flandre, Integral function method for determination of nonlinear harmonic distortion, Solid-State Electron. 48 (12) (2004) 2225–2234. [15] V. Kilchytska, A. Neve, L. Vancaillie, D. Levacq, S. Adriaensen, H. van Meer, K. De Meyer, C. Raynaud, M. Dehan, J.P. Raskin, D. Flandre, Influence of device engineering on the analog and RF performances of SOI MOSFETs, IEEE Trans. Electron Devices 50 (3) (2003) 577–588. [16] A. Vandooren, J.P. Colinge, D. Flandre, Gate-all-around OTA’s for red-hard and high-temperature analog applications, IEEE Trans. Nucl. Sci. 46 (4) (1999) 1242–1249.
[17] Athena Users’ Manual, Edition 10, 2004. [18] Atlas Users Manual, 2004. [19] M.A. Pavanello, J.A. Martino, D. Flandre, Analog performance and applications of graded-channel fully depleted SOI MOSFETs, SolidState Electron. 44 (7) (2000) 1219–1222. [20] S. Sakurai, M. Ismail, Low-voltage CMOS Operational Amplifiers Theory, Design and Implementation, Kluwer Academic Publishers, Dordrecht, 1994. [21] P. Wanbacq, W. Sansen, Distortion Analysis of Integrated Circuits, Kluwer Academic Publishers, Dordrecht, 1998. [22] M. de Souza, M.A. Pavanello, B. In˜iguez, D. Flandre, A chargebased continuous model for submicron graded-channel nMOSFET for analog circuit simulation, Solid-State Electron. 49 (10) (2005) 1683–1692. [23] M.A. Pavanello, A. Cerdeira, J.A. Martino, J.P. Raskin, D. Flandre, Impact of asymmetric channel configuration on the linearity of double-gate SOI MOSFETs, in: Proceedings of the 6th ICCDCS, 2006, pp. 187–191. [24] A. Cerdeira, M. Alema´n, V. Kilchitska, N. Collaert, K. De Meyer, D. Flandre, Nonlinearity analysis of FinFETs, in: Proceedings of the 6th ICCDCS, 2006, pp. 9–12.
Microelectronics Journal 39 (2008) 1663–1670 www.elsevier.com/locate/mejo
Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation Rodrigo Trevisoli Doriaa,, Antonio Cerdeirab, Jean-Pierre Raskinc, Denis Flandred, Marcelo Antonio Pavanelloa,e a
Departamento de Engenharia Ele´trica, Centro Universita´rio da FEI, Av. Humberto de Alencar Castelo Branco, 3972, CEP 09850-901, Sa˜o Bernardo do Campo, Brazil b Seccı´on de Electro´nica del Estado So´lido (SEES), CINVESTAV, Mexico c Laboratoire d’Hyperfre´quences, Universite´ Catholique de Louvain, Belgium d Laboratoire de Microe´lectronique, Universite´ Catholique de Louvain, Belgium e Laborato´rio de Sistemas Integra´veis, Escola Polite´cnica da Universidade de Sa˜o Paulo, Sa˜o Paulo, Brazil Received 6 December 2007; accepted 7 February 2008 Available online 2 April 2008
Abstract In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-around (GAA) devices operating in saturation region for analog applications. The study has been performed through device characterization and two-dimensional process and device simulations. The overall study has been done on the total and third order HDs. When applied in the saturation regime as an amplifier, the GC outperforms conventional GAA transistors presenting simultaneously higher transconductance, lower drain output conductance and more than 15 dB improved linearity. The influence of channel length reduction on the HD is also analyzed. Although slight linearity degradation is observed in both the conventional and the GC devices when reducing the channel length, the HD presented by the GC transistor is significantly lower than the one showed by conventional device for any studied channel length. This allows AC input signal amplitude up to 20 times higher than the conventional GAA for a same specified distortion level. r 2008 Elsevier Ltd. All rights reserved. Keywords: Silicon-on-insulator; Channel engineering; Graded-channel; Double gate; Gate-all-around; Asymmetric MOSFET; Harmonic distortion; Nonlinearity
1. Introduction The very high performance of SOI MOS transistors in analog applications such as operational amplifiers [1] and continuous-time filters [2] has long been demonstrated. These applications require devices with a satisfactory linear response, since the non-linear characteristic of the MOSFETs is frequently considered as a circuit bottleneck contributing for the poor quality of the output signal. Thus, the choice of the device is essential. Double gate (DG) SOI MOSFETs appear as a good alternative for such low-power low-voltage applications, since the presence of Corresponding author. Tel.: +55 11 4353 2900x2067; fax: +55 11 4109 5994. E-mail addresses: [email protected], [email protected] (R.T. Doria).
0026-2692/$ - see front matter r 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2008.02.006
two gates improves the gate control on the channel charges leading to nearly ideal body factor [3]. In our study, we have worked with DG gate-all-around (GAA) MOS transistors that feature a channel region surrounded by gate material and gate oxide. Since the channel widths (a few mm) of the GAA under analysis in this work are much bigger than the channel thickness (80 nm), the contribution of the current flow due to the vertical channels is negligible and thus GAA devices behave as symmetric DG transistors. According to Ref. [4], GAA devices have proven to be advantageous with respect to conventional single gate (SG) devices for several reasons, such as volume inversion, improved transconductance, nearly ideal sub-threshold slope and higher gain. It is known that in the GAA devices the transconductance can be over twice larger than in the SG transistors thanks to the
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lower mobility degradation provided by the volume inversion [3]. However, for the current study the volume inversion effect can only be observed in the vicinity of the threshold voltage. In order to obtain higher volume inversion contribution, thinner silicon layer devices should be used [5,6]. A new MOSFET architecture called graded-channel (GC) has been proposed in Ref. [7] with the purpose of reducing inherent bipolar effects exhibited in fully depleted uniformly doped SOI MOSFETs. The GC device is obtained thanks to a special arrangement in one of the masks of the conventional CMOS process, such that the threshold voltage implantation is not performed in the channel region near the drain. Consequently, this region (with length LLD) remains lightly doped with the initial wafer concentration and can be considered as an extension of the drain, whereas the rest of the channel controls the overall threshold voltage. For this reason, the effective channel length (Leff) can be approximated to the difference between the total channel length (L) and the length of the lightly doped region (Leff ¼ LLLD) in saturation. The GC device architecture has been successfully applied in DG configuration demonstrating extraordinary improvements in relation to the conventional ones (i.e. with uniformly doped channel), when operating as amplifiers [4,8,9]. This occurs because when the device is in saturation regime, the majority of the potential applied to the drain is absorbed in the interior of LLD region. Thus, the variation of the drain voltage that reaches the implanted channel region (which predominantly governs the drain current) is greatly reduced, appreciably improving the drain output conductance, and thereby leading to an extraordinary intrinsic voltage gain [9]. On the other hand, results of interest have also been reported for GC devices operating as tunable resistors in Ref. [10] demonstrating the potential of this channel engineering to be applied in low distortion MOSFET-C continuous-time filters. Other similar asymmetric MOSFETs have been studied in Refs. [11,12] also showing excellent analog performances. This paper proposes an evaluation of the performance of DG GC transistors made using the GAA device architecture (GC GAA), shown in Fig. 1, from the distortion perspective. The harmonic distortion (HD) corresponds to the non-linearities inherently exhibited in the output L LLD PolySi Gate Source N+
P+
P-
Gate Oxide Drain N+
PolySi Gate Buried Oxide Fig. 1. Cross-section of a graded-channel GAA SOI MOSFET.
current of transistors, resulting in the presence of signals whose frequencies differ from the input signal. Consequently, total HD (THD) and third order HD (HD3) have been taken as figures of merit. Second order HD (HD2) will not be discussed since this figure of merit is quite similar to THD in the analyzed regime of operation [13]. The distortion has been determined through the integral function method (IFM) once this technique permits the distortion extraction from DC measurements without the need of an AC characterization, contrary to Fourier based methods [14], for instance. The linearity properties of GC GAA will be investigated in relation to conventional GAA transistors in saturation regime. In this analysis the SOI MOSFET operates as a single transistor amplifier and the HD is determined for several LLD/L ratios. Channel length reduction influence on linearity will also be taken under consideration. For high analog performance in baseband applications, long channel MOSFETs are selected [15]. In order to perform the proposed analyses, this paper is organized as follows. Section 2 describes the fabrication characteristics of the measured transistors and the simulations. In Section 3 the analog performance is explored in the saturation regime. Section 4 discusses the origin of the non-linearities obtained. Finally, Section 5 points out the conclusions of this work. 2. Devices and simulations characteristics The measured GC GAA transistors have been fabricated according to the process described in Ref. [16]. The referred process has been optimized for analog baseband and instrumentation circuits. It uses UNIBOND wafers with an initial boron concentration of 1015 cm3 with 390 nm thick buried oxide. Devices with three parallel fingers, each one with L ¼ W ¼ 3 mm (where W is the channel width), have been made with several LLD/L ratios. The final thicknesses of the gate oxide and silicon film are 30 and 80 nm, respectively. The final doping level in the threshold voltage (VTH) adjust implanted region is in the order of 1017 cm3. Coupled process and device bi-dimensional numerical simulations have been performed through the Athena [17] and the Atlas [18] tools, respectively, for devices with dimensions similar to those experimentally measured. The simulations have taken into account models for bandgap narrowing, impact ionization, doping-dependent carrier lifetime and mobility degradation with vertical and lateral electric fields. Except for the maximum values of electrons and holes low field mobility of the Klaassen model, which have been set to 510 and 170 cm2/V s, respectively, default simulator coefficients were used. Uniformly doped GAA transistors that received the VTH implantation in the entire channel, hereafter called conventional GAA, were also simulated to allow for a performance comparison. The HD was determined through the application of the IFM to the transfer characteristics of the drain current as a function of gate voltage (IDSVGS) curves at fixed drain
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bias (VDS). For this analysis, the IFM calculation considered an equivalent input sinusoidal signal of amplitude Va added to the bias voltage (VGT ¼ VGSVTH, where VTH is the threshold voltage), i.e. emulating VGS ¼ VGT+Va sin(x) with x between 0 and 2p. 3. HD evaluation for devices operating in saturation region Aiming at the determination of the HD, the transfer characteristics IDS versus VGT at VDS ¼ 1.5 V were obtained for measured and simulated devices and are exhibited in Fig. 2. From the presented curves we can see the excellent agreement between both simulated and measured curves independently of GC GAA LLD/L ratio. The transconductance (gm), low-frequency open-loop voltage gain (AV) and the early voltage (VEA) were also extracted from the devices characteristics. When devices operate in saturation as for amplifiers, AV depends on the bias conditions and influences the HD performance. Considering that, AV has been simulated for devices of 1 and 3 mm gate lengths with several LLD/L ratios, as shown in Fig. 3. As expected, any GC studied device presents much larger AV than the conventional transistors with similar physical gate length (L) as also demonstrated in Refs. [4,9]. Among the GC GAA transistors, as the effective channel length is diminished through the increase of LLD/L, the gain suffers a degradation, as the drain conductance rises for smaller effective channel lengths [19]. The gain also degrades as L is downscaled independently of the channel architecture, as demonstrated in Fig. 3. The HD was firstly determined at fixed amplitude Va of 50 mV and varying the gate bias. The results of the obtained THD and HD3 for gm/IDS ¼ 3.5 V1 in strong inversion are shown in Table 1 for measured and simulated devices of various LLD/L ratios. As stated in Ref. [20] the
Fig. 3. Curves of AV versus gm/IDS for simulated conventional and GC GAA MOSFETs with gate lengths of (A) 1 mm and (B) 3 mm (VDS ¼ 1.5 V).
Table 1 Extracted and simulated values for AV, THD, HD3, THD/AV and HD3/ AV at VGT ¼ 500 mV, gm/IDS ¼ 3.5 V1, VDS ¼ 1.5 V and Va ¼ 50 mV (L ¼ 3 mm) THD Device L ¼ 3 mm AV (dB) (dB) LLD/L LLD/L 0.2 0.4 0.2 Experiment Simulation
Fig. 2. Curves of IDS versus VGT for measured and simulated GC GAA devices with total gate lengths (L) of 3 mm and various low-doped drain extension (LLD) over L ratios (VDS ¼ 1.5 V).
0.4
HD3 (dB) LLD/L
THD/AV (dB) LLD/L
0.2 0.4 0.2
0.4
HD3/AV (dB) LLD/L 0.2
0.4
76 62 34 35 73 71 105 95 144 130 72 62 35 37 77 76 106 97 149 136
differences on AV demonstrated in Fig. 3 can influence the HD characteristics, such that THD and HD3 were divided by the gain in the saturation region analysis generating the new figures of merit THD/AV and HD3/AV to allow for a fair comparison. The measured values for AV, THD/AV and HD3/AV are also given in Table 1, for devices with
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total gate length of 3 mm and various LLD/L ratios. As shown in Table 1 and in Fig. 2, the good agreement obtained between simulated and measured results for both IDS versus VGT characteristics and HD values validate the performed simulations. Thus, calibrated process-device simulation data will be used to determine the channel length influence on linearity properties of GC GAA devices, which allows not only for extending the set of LLD/L ratios under study, but also for comparing the results with uniformly doped, conventional GAA transistors. For the evaluation of the linearity, transistors of 1 and 3 mm channel lengths had their HD determined as a function of gm/IDS. According to the results obtained for THD in Fig. 4(A), as the LLD/L ratio increases the linearity improves and for the device with LLD/L ¼ 0.6, an advantage of 4 dB is obtained. The negative peaks observed
for all devices THD at gm/IDSffi1.25 V1 have been verified to correspond to the inflexion in the drain current where the devices start to operate in the triode regime; so this region of the curves is not relevant to the amplifier applications. On the other hand, the HD3 analysis shows a degradation of the linearity when increasing LLD/L as shown in Fig. 4(B). This degradation can be superior to 10 dB for devices with higher LLD/L, depending on the gm/IDS observed. However, as HD3 is not dominant for the analysis of one transistor amplifier in saturation, because THDffiHD2 is greater than HD3 by least in 20 dB, the rise in this distortion does not present significant influence in THD. Even in a differential operational amplifier in which HD3 would become dominant, the degradation observed on HD3 when increasing LLD/L shall be analyzed more carefully since the different AV among the devices influence the linearity. Thus, the HD3/AV figure for the linearity shall be verified. Devices of L ¼ 1 mm presented similar results showing reduction on THD and degradation on HD3 as LLD/L rises. When compared to 3 mm-long transistors, the smaller devices exhibit similar THD and a slight degradation on HD3. 4. Discussion The results obtained for HD2 (ffiTHD) and HD3 can be explained through the expressions (1) and (2) extracted from Ref. [21], which are valid for low signal amplitude Va. According to these equations, the HD is a function of the transconductance and its derivatives.
Fig. 4. Simulated curves of (A) THD and (B) HD3 as a function of gm/IDS for the GAA and GC GAA devices (VDS ¼ 1.5 V and Va ¼ 50 mV).
1 ðdgm =dV GT Þ HD2 ¼ Va , 2 2gm
(1)
1 ðd2 gm =dV 2GT Þ HD3 ¼ Va2 . 4 6gm
(2)
This way, considering the input signal amplitude Va constant, HD2 is dependent on the first derivative of gm and HD3 on the second. By calculating the HD it is possible to observe that the shape of the final HD2 curves is mainly governed by the derivative of gm as exhibited in Fig. 5(A) for devices of L ¼ 3 mm, and the linear increase of the transconductance with LLD as in Fig. 5(B). Since HD2 dominates the distortion in the saturation analysis, the improvement observed on THD due to the GC architecture in Fig. 4(A) is derived from the higher increase in gm obtained for gm/IDS between 2 and 5 V1 (VGT between 0.3 and 0.7 V) thanks to the smaller effective channel length, which is clearly shown in the derivative of gm. As mentioned, the shape of the final HD2 curves is indeed essentially given by dgm/dVGT divided by 2gm. As the levels of both dgm/dVGT and gm curves tends to increase as LLD/L, the higher linearity exhibited by the GC devices is determined through the greater increase observed for the transconductance in relation to the one obtained by
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the necessary overdrive voltage to reach the linear region slightly reduces when increasing LLD/L, which moves the negative peaks to larger gm/IDS. As previously mentioned, GC devices with different LLD/L ratios present distinct open-loop gain. Since AV can influence the HD, to fairly compare the results of HD3 and THD obtained for devices with different LLD/L ratios operating as single-transistor amplifiers in the unity-gain configuration; these figures of merit were divided by AV yielding the new figures of merit THD/AV and HD3/AV. Thus, the curves of THD/AV and HD3/AV are plotted in Fig. 6 as a function of the transconductance-to-drain ratio, which then yields the current required to obtain a given linearity level for a determined gain-bandwidth product (i.e. GBW ¼ gm/CL ¼ (gm/IDS)*(IDS/CL), where CL is the load) [23]. Although linearity degradation is observed when reducing the devices channel length, both 1 and 3 mm long GC devices present great improvement on THD/AV. When compared to the conventional, the shorter GC device of
Fig. 5. Simulated curves of (A) qgm/qVGT versus gm/IDS and (B) gm versus gm/IDS for devices of 3 mm channel length at VDS ¼ 1.5 V.
the gm derivative. Similarly, as presented in Eq. (2), the shape of HD3 is mainly determined by d2gm/dV2GT divided by 6gm, including the negative peaks presented in Fig. 4(B) which occur at dgm/dVGT ¼ 0. In this case, d2gm/dV2GT also rises as LLD/L. However, the division of the second derivative of gm by 6gm does not present enough influence on HD3 to improve the linearity. Except in the peak region, which is shifted to the right (this is an advantage if the sweet spot, i.e. optimal range, is obtained for more practical gm/IDS around 10 V1). HD3 worsens as LLD/L is increased. The negative peaks exhibited in the HD3 curves for the 3 mm-long devices are coincident with either maximum or minimum points in the dgm/dVGT curves [13]. These negative peaks move to larger gm/IDS as the LLD/L ratio increases owing to the fact that in saturation the lightly doped region of the devices is pinched off, and for that reason absorbs part of the applied VDS [22]. Consequently,
Fig. 6. Simulated THD/AV versus gm/IDS curves for channel lengths of (A) 1 mm and (B) 3 mm (VDS ¼ 1.5 V and Va ¼ 50 mV).
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LLD/L ¼ 0.4 shows an improvement of 20 dB, while the longer one for LLD/L ¼ 0.2 presents a THD/AV 33 dB better than the conventional device of same physical dimensions at gm/IDS ¼ 3.5 V1, i.e. in strong inversion. The excellent values obtained for THD/AV at gm/IDS ratios between 3 and 5 V1, mainly for the longer device, are derived from the better THD presented by these devices in Fig. 4(A) associated to the greater gain provided by the GC structure in this bias region. Although HD3 is not the predominant distortion in the current analysis, the curves of HD3/AV as a function of gm/ IDS shown in Fig. 7 state that all GC transistors under study show better performance than the conventional ones. The 1 mm-long device with LLD/L ¼ 0.4 presents an improvement of 15 dB at gm/IDS between 3 and 10 V1 and the 3 mm-long transistor with LLD/L ¼ 0.2 shows 25 dB improvement at gm/IDS ratios in the left side of the observed negative peaks. For the 1 mm-long devices, the
negative peaks occur at gm/IDS ratios greater than 10 V1 and, for that reason, are not exhibited in the figure. Nevertheless, the present work results diverge from the ones reported in Ref. [24] for DG FinFETs. The referred study presents an improvement in THD/AV as gm/IDS is increased for devices of any L. So that, the study carried out on the mentioned reference shows better linearity properties for higher gm/IDS ratios and worse HD at lower gm/IDS for any analyzed device. Apparently, the differences obtained for THD/AV in both studies are related to the higher doping concentration (6 1017 cm3) of the FinFET devices and to the mobility variation. Fig. 8 shows the curves of THD/AV and HD3/AV as a function of the devices channel length at gm/IDS ¼ 3 V1. Similar behavior is obtained for any gm/IDS from 2 to 10 V1. For majority of the analyzed devices, the obtained curves present a small degradation when reducing the channel length. The only exceptions are the shorter devices with LLD/L ¼ 0.1 and 0.2, which exhibit a larger degradation since their lightly doped regions do not reach the wafer doping level due to the lateral diffusion of VTH implanted impurities. In order to evaluate the analog performance of GC GAA SOI nMOSFETs as a function of the sinusoidal input amplitude Va, we considered a fixed bias of gm/IDS ¼ 5 V1 which represents a fixed bias voltage VGT around 0.35 V. Through the curves of THD/AV versus Va, the determination of the maximum input signal amplitude Va for a given distortion level is allowed. Thus, the designer is able to choose the device that best fits the desired operation conditions searching for the optimal relation between HD and device channel length for the required Va. The maximum Va amplitudes to obtain targeted THD/AV between 70 and 80 dB is presented in Table 2. The exhibited evaluation has been obtained for sinusoidal input amplitudes varying between 0.01 and 1.0 V and, as expected, has shown remarkable improvements when the GC architecture is applied. The italic values in the table
Fig. 7. Simulated HD3/AV versus gm/IDS curves for channel lengths of (A) 1 mm and (B) 3 mm (VDS ¼ 1.5 V and Va ¼ 50 mV).
Fig. 8. Simulated THD/AV and HD3/AV as a function of channel length for gm/IDS ¼ 3 V1.
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Table 2 Maximum amplitude Va of the sinusoidal input to attain the target distortion THD/AV Target THD/AV (dB)
Max Va (V) conv. GAA
Max Va (V), GC GAA—LLD/L 0.1
0.2
0.3
0.4
0.5
0.6
L 1 mm
80 75 70
o0.010 o0.010 0.014
o0.010 0.010 0.019
0.015 0.026 0.045
0.033 0.058 0.103
0.048 0.085 0.150
0.044 0.077 0.137
0.030 0.052 0.093
L 2 mm
80 75 70
o0.010 0.016 0.026
0.030 0.055 0.094
0.141 0.254 0.474
0.159 0.287 0.546
0.125 0.223 0.404
0.094 0.166 0.291
0.064 0.113 0.196
L 3 mm
80 75 70
0.016 0.025 0.039
0.166 0.300 0.573
0.378 0.761 41.000
0.305 0.592 41.000
0.255 0.473 41.000
0.148 0.263 0.471
0.125 0.216 0.367
Italic values represent the cases in which the maximum Va allowed in the GC device is greater than one order of magnitude in relation to the conventional one.
highlights the devices for which the permitted input amplitude Va at the specified distortion level in the asymmetric device is greater by one order of magnitude compared to the conventional one (uniformly doped channel). For devices with L ¼ 3 mm and LLD/L between 0.2 and 0.4, the targeted THD/AV of 70 dB is attained for any input amplitude under study, while for the shorter conventional devices THD/AV is always superior than 75 dB. Considering that the high voltage gain of GC transistors is higher than 20 dB, results shown in Table 2 indicates that targeted distortion level can be achieved in all the practical dynamic range of transistor operation. 5. Conclusions This work analyzes the interest of DG GC devices for analog applications in saturation regime for devices operating as amplifiers. THD, HD3, THD/AV and HD3/AV were taken as the figures of merit. According to the results, the use of GC architecture improves remarkably the linearity on the output signal. Depending on the length of lightly doped channel region (LLD/L), 3 mm-long GC devices presented a reduction on THD/AV that reaches 30 dB. Although the linearity degradation observed when reducing the channel length, any GC device shows better results for HD3 and THD by up to 10 dB. Moreover, this work demonstrates that the GC configuration relaxes the constraint on the input signal amplitude for a requested distortion level. DG GC devices with LLD/L from 0.2 to 0.4 allow AC input signal amplitude up to 20 times higher than the conventional GAA for a same specified distortion level. Acknowledgments Rodrigo T. Doria and Marcelo A. Pavanello acknowledge the Brazilian research-funding agencies CAPES, CNPq and FAPESP for the financial support. Denis Flandre is Honorary Senior Research Associate of the
FRS-FNRS, Belgium. The authors thank the UCL micronano-infrastructure technical staff for device fabrication.
References [1] D. Flandre, J.P. Colinge, J. Chen, D. De Ceuster, J.P. Eggermont, L. Ferreira, B. Gentinne, P.G.A. Jespers, A. Viviani, R. Gillon, J.P. Raskin, A. Vander Vorst, D. Vanhoenacker-Janvier, F. Silveira, Fully-depleted SOI CMOS technology for low-voltage low-power mixed digital/analog/microwave circuits, Analog Integrated Circuits Signal Process. 21 (1999) 213–228. [2] D. Flandre, L.F. Ferreira, P.G.A. Jespers, J.P. Colinge, Modeling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits, Solid-State Electron. 39 (4) (1996) 455–460. [3] J.P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Kluwer Academic Publishers, Dordrecht, 1991. [4] A. Kranti, T.M. Chung, D. Flandre, J.P. Raskin, Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications, Solid-State Electron. 48 (6) (2004) 947–959. [5] T. Rudenko, N. Collaert, S. De Gendt, V. Kilchytska, M. Jurczak, D. Flandre, Effective mobility in FinFET Structures with HfO2 and SiON gate dielectrics and TaN gate electrode, Microelectron. Eng. 80 (2005) 386–389. [6] J.P. Raskin, T.M. Chung, V. Kilchytska, D. Lederer, D. Flandre, Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization, IEEE Trans. Electron Devices 53 (5) (2006) 1088–1095. [7] M.A. Pavanello, J.A. Martino, D. Flandre, Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects, Solid-State Electron. 44 (6) (2000) 917–922. [8] R.T. Doria, M.A. Pavanello, A. Cerdeira, J.P. Raskin, D. Flandre, Channel length reduction influence on harmonic distortion of gradedchannel gate-all-around devices, in: 21st Symposium on Microelectronics Technology and Devices, 2006, pp. 247–256. [9] M.A. Pavanello, J.A. Martino, J.-P. Raskin, D. Flandre, High performance analog operation of double-gate transistors with graded-channel architecture at low temperatures, Solid-State Electron. 49 (10) (2005) 1569–1575. [10] A. Cerdeira, M.A. Alema´n, M.A. Pavanello, J.A. Martino, L. Vancaillie, D. Flandre, Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor, IEEE Trans. Electron Devices 52 (5) (2005) 967–972.
ARTICLE IN PRESS 1670
R.T. Doria et al. / Microelectronics Journal 39 (2008) 1663–1670
[11] M.A. Pavanello, J.A. Martino, D. Flandre, Analog circuit design using graded-channel SOI nMOSFETs, Solid-State Electron. 46 (8) (2002) 1215–1225. [12] S.P. Gimenez, M.A. Pavanello, J.A. Martino, D. Flandre, Gain improvement in operational transconductance amplifiers using gradedchannel SOI nMOSFETs, Microelectron. J. 37 (1) (2006) 31–37. [13] A. Cerdeira, M. Estrada, R. Quintero, D. Flandre, A. Ortiz-Conde, F.J. Garcı´ a Sa´nchez, New method for determination of harmonic distortion in SOI FD transistors, Solid-State Electron. 46 (1) (2002) 103–108. [14] A. Cerdeira, M.A. Alema´n, M. Estrada, D. Flandre, Integral function method for determination of nonlinear harmonic distortion, Solid-State Electron. 48 (12) (2004) 2225–2234. [15] V. Kilchytska, A. Neve, L. Vancaillie, D. Levacq, S. Adriaensen, H. van Meer, K. De Meyer, C. Raynaud, M. Dehan, J.P. Raskin, D. Flandre, Influence of device engineering on the analog and RF performances of SOI MOSFETs, IEEE Trans. Electron Devices 50 (3) (2003) 577–588. [16] A. Vandooren, J.P. Colinge, D. Flandre, Gate-all-around OTA’s for red-hard and high-temperature analog applications, IEEE Trans. Nucl. Sci. 46 (4) (1999) 1242–1249.
[17] Athena Users’ Manual, Edition 10, 2004. [18] Atlas Users Manual, 2004. [19] M.A. Pavanello, J.A. Martino, D. Flandre, Analog performance and applications of graded-channel fully depleted SOI MOSFETs, SolidState Electron. 44 (7) (2000) 1219–1222. [20] S. Sakurai, M. Ismail, Low-voltage CMOS Operational Amplifiers Theory, Design and Implementation, Kluwer Academic Publishers, Dordrecht, 1994. [21] P. Wanbacq, W. Sansen, Distortion Analysis of Integrated Circuits, Kluwer Academic Publishers, Dordrecht, 1998. [22] M. de Souza, M.A. Pavanello, B. In˜iguez, D. Flandre, A chargebased continuous model for submicron graded-channel nMOSFET for analog circuit simulation, Solid-State Electron. 49 (10) (2005) 1683–1692. [23] M.A. Pavanello, A. Cerdeira, J.A. Martino, J.P. Raskin, D. Flandre, Impact of asymmetric channel configuration on the linearity of double-gate SOI MOSFETs, in: Proceedings of the 6th ICCDCS, 2006, pp. 187–191. [24] A. Cerdeira, M. Alema´n, V. Kilchitska, N. Collaert, K. De Meyer, D. Flandre, Nonlinearity analysis of FinFETs, in: Proceedings of the 6th ICCDCS, 2006, pp. 9–12.
