Hydroponic Garden Automation using Various Interfacing Devices
Hydroponic Garden Automation using Various Interfacing Devices May 3, 2013 Alexander Barrow Computer Engineer Sophomore Demonstrating
Kelvin Jerry Computer Engineer Sophomore Demonstrating Team Leader
Anthony Bird Computer Engineer Junior Demonstrating
Table of Contents A. Assignment ........................................................................................................................................... 3 B. Equipment Used.................................................................................................................................... 4 C. Methodology......................................................................................................................................... 5 F. Testing Methodology ............................................................................................................................ 9 G. References ............................................................................................................................................ 9 H. Appendices ......................................................................................................................................... 10 Spec. Sheets ........................................................................................................................................ 10 State Tables ......................................................................................................................................... 17 Xilinx Diagram ..................................................................................................................................... 20 Xilinx Constraint File............................................................................................................................ 21 PLC Flowchart...................................................................................................................................... 22
2
A. Assignment
3
B. Equipment Used
Figure 3: PLC
Figure 1: Pad-234 analog digital trainer
Figure 4: 2-input OR, D-Flip Flop, AND, XOR, NAND, 3-input AND, 3-input OR (from left to right).
Figure 2a: FPGA
Figure 5: 12-Volt Fan
Figure 2b: Bucket used with attached level sensors and motors.
4
C. Methodology Define Problem The purpose of the lab was to design and build a hydroponic test-bed set-up to help understand the functioning and control of hydroponic gardens. Large buckets, levels sensors, a water pump, an air pump, a water flow sensor, and 120volt light were used to simulate a hydroponic test-bed. The system had to fill a bucket until it hit one of the three sensors that were three inches apart. When the water hit a sensor the system stopped filling and aerated for 5 seconds. When water hit the last sensor the system aerated then triggered a light. This system was simulated using the PLC, Circuit Trainer, FPGA, and 8051 simulator. The PLC program was created in junction with the controls class. The PLC program was then simulated in two ways. One circuit created an automated program that simulated the lab setup, while the other used several switches.
Draw State Diagram
Figure 6: State Diagram of 3-bit counter resets to zero.
The three bit counter pictured above was used in the non-automated circuit for aeration. This counter resets to zero after reaching seven.
Figure 7: State Diagram of 3-bit counter stays at 7.
The counter above was used in the automated program to represent the time it took to fill a bucket. This counter counted up to and stayed at seven.
Preliminary Lab It was specified that the float sensors should be spaced three inches apart on the bucket; one at three inches from the bottom, one at six inches from the bottom, and one at nine inches from the bottom. The pump also had to be placed at the bottom of the bucket. We marked the bucket at the appropriate places for all four devices, and then using a drill, we bored the holes in the bucket and placed the devices with the wires in the proper place to be connected later on. Hoses were then used to connect the pump to two separate valves. One valve was for filling the bucket, while the other was for draining it. The aeration pump was set up inside the bucket and a light bulb was set up.
Figure 8: State Diagram of 2-bit sequential number detector.
The circuit that detects a sequence e of four 1βs above was used in the automated circuit to simulate aeration time. This counter resets to zero after reaching a sequence of four ones.
Encode Variables Variables used in this lab were already in binary, so there was no need to encode them.
Minimize Machine The machine was not adjusted because it was in its simplest form.
After the initial setup, the various devices were wired to a nanoline PLC. The float sensors were wired into the inputs of the PLC, while the aeration device, the pump, and the light bulb were all wired to outputs. The pump, the aeration device, and the light bulb were wired to different power sources as the PLC could not support that power output, they were merely hooked to relays on the nanoline to
trigger the output. The system was then ready to be programmed.
5
Make State Table A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
DA 0 0 0 1 1 1 1 0
DB 0 1 1 0 0 1 1 0
Dc 1 0 1 0 1 0 1 0
Figure 9: State Diagram of 3-bit counter resets to zero.
The state table for the resetting three bit counter shows the transition of binary numbers. The starting state is on the left, while the ending state is on the right. The least significant bit is represented by C and the most significant bit is represented by A. This was used when creating the non-autonomous circuit to measure aeration time. A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
DA 0 0 0 1 1 1 1 1
DB 0 1 1 0 0 1 1 1
Dc 1 0 1 0 1 0 1 1
Figure 10: State Diagram of 3-bit counter does not reset.
The state table for the three bit counter that doesnβt reset shows the transition of binary numbers. Clock inputs and transition states are not shown. The starting state is on the left, while the ending state in on the right. This was used when creating the automated circuit measure flow time. A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
X 0 1 0 1 0 1 0 1
A 0 0 0 1 0 1 0 1
B 0 1 0 0 0 1 0 1
Y 0 0 0 0 0 0 0 0
The state table for the circuit used to detect a sequence of four 1βs. This was used in the automated circuit to measure aeration time.
Simplify Flip-Flop DA = AB + ABC + ABC 1 1 1 1 π·π΅ = πΆπ΅ + πΆπ΅ = π΅ β πΆ 1 1 1 1 π·πΆ = π΅ πΆ + π΅πΆ = (π΅ + π΅)πΆ = πΆ 1 1 1 1 Figure 12: Simplification maps of 3-bit counter that resets.
π·π΄ = π΄ + π΅πΆ 1 1 1 1 1 π·π΅ = π΅πΆ + π΅πΆ + π΄π΅ = (π΅ β πΆ) + π΄π΅ 1 1 1 1 1 π·πΆ = π΅ πΆ + π΅πΆ + π΄π΅ = (π΅ + π΅)πΆ + π΄π΅ = πΆ + π΄π΅ 1 1 1 1 1 Figure 13: Simplification maps of 3-bit counter that doesnβt reset.
π·π΄ = π΅π + AX 1 1 1 π·π΅ = π΅π + π΄π 1 1 1 π = π΅π΄π 1 Figure 14: Simplification maps of sequential circuit.
The simplification maps in figure 12 were used in the non-automated circuit. The simplification maps in figures 13 and 14 were used in the automated circuit.
Figure 11: State Diagram of Circuit used to detect a sequence of four 1βs.
6
Draw Logic Circuit
Figure 17: Rail Logic used when creating the non-automated circuit.
Figure 15: Rail Logic used when creating the non-automated circuit.
Figure 18: Finished circuit created using logic diagram from figure 17.
The three bit counter, and sequential circuit is shown in figure 17 along with a chain of D-Flip flops. A larger version of the diagram can be viewed in the appendices.
Convert to NANDS Converting to NANDs was not necessary in this lab. Figure 16: Finished circuit created using logic diagram from figure 15.
The diagram shown above in figure 15 was created using Logisim. The program allowed us to test our circuit before its implementation. Other chips were used in conjunction with the counter in the non-automated system to simulate the automated hydroponic garden. A larger version of the diagram can be viewed in the appendices.
Analyze Unused States No unused states exist for this circuit. All bit combinations produced used states.
Re-Draw State Diagram The state diagram was unchanged. The final diagrams can be seen in figures 17 and 15.
Review Assumptions Assumptions were not made. Using the previous information we created the circuits on the PAD-234 Circuit Trainer, FPGA, and 8051 simulator.
PLC Program The programming of the PLC was undertaken by the Control Systems class, with us in EGR 333 overseeing it, as well as giving advice and final approval. The program written for the PLC by the controls group turn out as such: The system starts and the water pumps into the bucket, the pump being output 00. When the water level tripped the float sensor three inches from the bottom, input 00, the water pump would be stopped and the aeration process would be started, output 01. The program would then go 7
through a five second wait and then turn off the aeration and restart the water flow. When the water tripped float sensor two at six inches, input 01, the same process would occur. Then, when the water tripped the third sensor at nine inches, input 02, the pump would stop, the aeration would occur for five seconds. Then the aeration would stop, the light bulb, output 02, would be turned on, then the water would drain, the drain pump being output 03. There was also a programmed fail-safe that would shut down the entire system if there ever occurred a time where a float sensor did not trip when it was supposed to.
Non-Automated Circuit The non-automated circuit was designed using switches as βflow sensorsβ and a 3-bit counter for the aeration period. An LED was used to indicate water flow. When a switch was flipped to high, it indicated that the water had reached that sensor, the LED representing flow was turned off, and the aeration counter was started. At the end of the aeration period, the flow light turned back on and input from the next switch would be taken. After the third aeration period, the flow light would remain off to indication a full bucket.
Automated Circuit The automated circuit was designed using a three bit counter and a 2-bit sequential circuit. The three bit counter represents the time it takes to fill a bucket, which is three seconds. After the circuit reaches 7 a sensor is hit and the sequential circuit is triggered. A chain of D-flip flops represents the three level sensors in the bucket. They are connected in a way that allows a state to be saved each time itβs triggered. The 2-bit sequential circuit represents the time it takes to aerate the water. After the circuit for aeration counts a series of four 1βs each D-flip flop in the circuits used for counting are reset. After a signal in the chain of D-flip flops reaches the third flip flop a fan is triggered to represent the completion of a full cycle or the light bulb coming on in our hydroponic garden.
8051 Program One of the requirements of the lab was to simulate the hydroponic garden using the 8051 microcontroller simulator. Using code generously provided by James Kelly we were able to understand how our setup could be simulated on the 8051 microcontroller. D. Options When creating the PLC program we were able to decide how we programmed the automated system. Using the Flowchart program many different variations of the same system could be created. Using breadboards we were able to create two different approaches to the given problem. One circuit was created to simulate an automated hydroponic garden, while the other used switches to trigger events. E. Problems Encountered During the lab, there was a problem encountered when using one of the counters on the PLC using one of the counters, and for our fail-safe, we had to resort using a counter that counted by seconds, instead of counts that we set ourselves. Another problem encountered was one while working on the circuit simulation in Logisim. When setting up a system to act as the water flowing, and then switching over to the aeration, using clocks and D-flip-flops, the system would not work properly after the first βaeration.β It was later discovered that we had to use a negative clock edge instead of a positive one to have the system work properly. On the breadboard, the circuit required two Dflip-flop chips instead of one, because there were two clear separate clears required for the system to function properly and it would not work if all of the flip-flops used were wired to the same clear. When creating the automated circuit we ran into several problems. The clears on the D-flip flop didnβt act as expected. The D-flip-flip that used a clock for both the input and clock didnβt work properly. This was solved by connecting the input high so the flip flop was able to properly store bits. Creating the circuits on the
8
pad trainer became somewhat difficult when connecting so many chips.
F. Testing Methodology The PLC and FPGA programs were simulated in Logisim before being implemented. Programs for the FPGA were simulated using the Xilinx software. Visual inspection and software assistance allowed us to catch and address potential problems. When creating the circuit on the PAD Trainer each chip was checked for errors before being used. Visual inspection of the output LEDs allowed us to determine whether each circuit was working properly. The connections from the relay to the fan were inspected. After losing several chips we paid more attention to the connections between the chips, board, and power source.
G. References [1] A. Kenneth, β8051 Microcontroller: Architecture, Programming and Applicationsβ, New York, 1996
9
H. Appendices Spec. Sheets
10
11
12
13
14
15
16
State Tables Three Bit Counter Resets Table A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
DA 0 0 0 1 1 1 1 0
DB 0 1 1 0 0 1 1 0
Dc 1 0 1 0 1 0 1 0
Simplification Maps π·π΄ = π΄π΅ + π΄π΅πΆ + π΄π΅πΆ 1 1 1 1 π·π΅ = πΆπ΅ + πΆπ΅ = π΅ β πΆ 1 1 1 1 π·πΆ = π΅ πΆ + π΅πΆ = (π΅ + π΅)πΆ = πΆ 1 1 1 1 Rail Logic used in non-automated
17
Three Bit Counter Doesnβt Reset Table A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
DA 0 0 0 1 1 1 1 1
DB 0 1 1 0 0 1 1 1
Dc 1 0 1 0 1 0 1 1
Simplification Maps π·π΄ = π΄ + π΅πΆ 1 1 1 1 1 π·π΅ = π΅πΆ + π΅πΆ + π΄π΅ = (π΅ β πΆ) + π΄π΅ 1 1 1 1 1 π·πΆ = π΅ πΆ + π΅πΆ + π΄π΅ = (π΅ + π΅)πΆ + π΄π΅ = πΆ + π΄π΅ 1 1 1 1 1 Two Bit Sequential Circuit A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
X 0 1 0 1 0 1 0 1
DB 0 0 0 1 1 1 1 0
Dc 0 1 1 0 0 1 1 0
Simplification Maps π·π΄ = π΅π + AX 1 1 1 π·π΅ = π΅π + π΄π 1 1 1 π = π΅π΄π 1 18
Rail Logic Rail Logic used in non-automated
19
Xilinx Diagram
20
Xilinx Constraint File
21
PLC Flowchart
22
23
24
Kelvin Jerry Computer Engineer Sophomore Demonstrating Team Leader
Anthony Bird Computer Engineer Junior Demonstrating
Table of Contents A. Assignment ........................................................................................................................................... 3 B. Equipment Used.................................................................................................................................... 4 C. Methodology......................................................................................................................................... 5 F. Testing Methodology ............................................................................................................................ 9 G. References ............................................................................................................................................ 9 H. Appendices ......................................................................................................................................... 10 Spec. Sheets ........................................................................................................................................ 10 State Tables ......................................................................................................................................... 17 Xilinx Diagram ..................................................................................................................................... 20 Xilinx Constraint File............................................................................................................................ 21 PLC Flowchart...................................................................................................................................... 22
2
A. Assignment
3
B. Equipment Used
Figure 3: PLC
Figure 1: Pad-234 analog digital trainer
Figure 4: 2-input OR, D-Flip Flop, AND, XOR, NAND, 3-input AND, 3-input OR (from left to right).
Figure 2a: FPGA
Figure 5: 12-Volt Fan
Figure 2b: Bucket used with attached level sensors and motors.
4
C. Methodology Define Problem The purpose of the lab was to design and build a hydroponic test-bed set-up to help understand the functioning and control of hydroponic gardens. Large buckets, levels sensors, a water pump, an air pump, a water flow sensor, and 120volt light were used to simulate a hydroponic test-bed. The system had to fill a bucket until it hit one of the three sensors that were three inches apart. When the water hit a sensor the system stopped filling and aerated for 5 seconds. When water hit the last sensor the system aerated then triggered a light. This system was simulated using the PLC, Circuit Trainer, FPGA, and 8051 simulator. The PLC program was created in junction with the controls class. The PLC program was then simulated in two ways. One circuit created an automated program that simulated the lab setup, while the other used several switches.
Draw State Diagram
Figure 6: State Diagram of 3-bit counter resets to zero.
The three bit counter pictured above was used in the non-automated circuit for aeration. This counter resets to zero after reaching seven.
Figure 7: State Diagram of 3-bit counter stays at 7.
The counter above was used in the automated program to represent the time it took to fill a bucket. This counter counted up to and stayed at seven.
Preliminary Lab It was specified that the float sensors should be spaced three inches apart on the bucket; one at three inches from the bottom, one at six inches from the bottom, and one at nine inches from the bottom. The pump also had to be placed at the bottom of the bucket. We marked the bucket at the appropriate places for all four devices, and then using a drill, we bored the holes in the bucket and placed the devices with the wires in the proper place to be connected later on. Hoses were then used to connect the pump to two separate valves. One valve was for filling the bucket, while the other was for draining it. The aeration pump was set up inside the bucket and a light bulb was set up.
Figure 8: State Diagram of 2-bit sequential number detector.
The circuit that detects a sequence e of four 1βs above was used in the automated circuit to simulate aeration time. This counter resets to zero after reaching a sequence of four ones.
Encode Variables Variables used in this lab were already in binary, so there was no need to encode them.
Minimize Machine The machine was not adjusted because it was in its simplest form.
After the initial setup, the various devices were wired to a nanoline PLC. The float sensors were wired into the inputs of the PLC, while the aeration device, the pump, and the light bulb were all wired to outputs. The pump, the aeration device, and the light bulb were wired to different power sources as the PLC could not support that power output, they were merely hooked to relays on the nanoline to
trigger the output. The system was then ready to be programmed.
5
Make State Table A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
DA 0 0 0 1 1 1 1 0
DB 0 1 1 0 0 1 1 0
Dc 1 0 1 0 1 0 1 0
Figure 9: State Diagram of 3-bit counter resets to zero.
The state table for the resetting three bit counter shows the transition of binary numbers. The starting state is on the left, while the ending state is on the right. The least significant bit is represented by C and the most significant bit is represented by A. This was used when creating the non-autonomous circuit to measure aeration time. A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
DA 0 0 0 1 1 1 1 1
DB 0 1 1 0 0 1 1 1
Dc 1 0 1 0 1 0 1 1
Figure 10: State Diagram of 3-bit counter does not reset.
The state table for the three bit counter that doesnβt reset shows the transition of binary numbers. Clock inputs and transition states are not shown. The starting state is on the left, while the ending state in on the right. This was used when creating the automated circuit measure flow time. A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
X 0 1 0 1 0 1 0 1
A 0 0 0 1 0 1 0 1
B 0 1 0 0 0 1 0 1
Y 0 0 0 0 0 0 0 0
The state table for the circuit used to detect a sequence of four 1βs. This was used in the automated circuit to measure aeration time.
Simplify Flip-Flop DA = AB + ABC + ABC 1 1 1 1 π·π΅ = πΆπ΅ + πΆπ΅ = π΅ β πΆ 1 1 1 1 π·πΆ = π΅ πΆ + π΅πΆ = (π΅ + π΅)πΆ = πΆ 1 1 1 1 Figure 12: Simplification maps of 3-bit counter that resets.
π·π΄ = π΄ + π΅πΆ 1 1 1 1 1 π·π΅ = π΅πΆ + π΅πΆ + π΄π΅ = (π΅ β πΆ) + π΄π΅ 1 1 1 1 1 π·πΆ = π΅ πΆ + π΅πΆ + π΄π΅ = (π΅ + π΅)πΆ + π΄π΅ = πΆ + π΄π΅ 1 1 1 1 1 Figure 13: Simplification maps of 3-bit counter that doesnβt reset.
π·π΄ = π΅π + AX 1 1 1 π·π΅ = π΅π + π΄π 1 1 1 π = π΅π΄π 1 Figure 14: Simplification maps of sequential circuit.
The simplification maps in figure 12 were used in the non-automated circuit. The simplification maps in figures 13 and 14 were used in the automated circuit.
Figure 11: State Diagram of Circuit used to detect a sequence of four 1βs.
6
Draw Logic Circuit
Figure 17: Rail Logic used when creating the non-automated circuit.
Figure 15: Rail Logic used when creating the non-automated circuit.
Figure 18: Finished circuit created using logic diagram from figure 17.
The three bit counter, and sequential circuit is shown in figure 17 along with a chain of D-Flip flops. A larger version of the diagram can be viewed in the appendices.
Convert to NANDS Converting to NANDs was not necessary in this lab. Figure 16: Finished circuit created using logic diagram from figure 15.
The diagram shown above in figure 15 was created using Logisim. The program allowed us to test our circuit before its implementation. Other chips were used in conjunction with the counter in the non-automated system to simulate the automated hydroponic garden. A larger version of the diagram can be viewed in the appendices.
Analyze Unused States No unused states exist for this circuit. All bit combinations produced used states.
Re-Draw State Diagram The state diagram was unchanged. The final diagrams can be seen in figures 17 and 15.
Review Assumptions Assumptions were not made. Using the previous information we created the circuits on the PAD-234 Circuit Trainer, FPGA, and 8051 simulator.
PLC Program The programming of the PLC was undertaken by the Control Systems class, with us in EGR 333 overseeing it, as well as giving advice and final approval. The program written for the PLC by the controls group turn out as such: The system starts and the water pumps into the bucket, the pump being output 00. When the water level tripped the float sensor three inches from the bottom, input 00, the water pump would be stopped and the aeration process would be started, output 01. The program would then go 7
through a five second wait and then turn off the aeration and restart the water flow. When the water tripped float sensor two at six inches, input 01, the same process would occur. Then, when the water tripped the third sensor at nine inches, input 02, the pump would stop, the aeration would occur for five seconds. Then the aeration would stop, the light bulb, output 02, would be turned on, then the water would drain, the drain pump being output 03. There was also a programmed fail-safe that would shut down the entire system if there ever occurred a time where a float sensor did not trip when it was supposed to.
Non-Automated Circuit The non-automated circuit was designed using switches as βflow sensorsβ and a 3-bit counter for the aeration period. An LED was used to indicate water flow. When a switch was flipped to high, it indicated that the water had reached that sensor, the LED representing flow was turned off, and the aeration counter was started. At the end of the aeration period, the flow light turned back on and input from the next switch would be taken. After the third aeration period, the flow light would remain off to indication a full bucket.
Automated Circuit The automated circuit was designed using a three bit counter and a 2-bit sequential circuit. The three bit counter represents the time it takes to fill a bucket, which is three seconds. After the circuit reaches 7 a sensor is hit and the sequential circuit is triggered. A chain of D-flip flops represents the three level sensors in the bucket. They are connected in a way that allows a state to be saved each time itβs triggered. The 2-bit sequential circuit represents the time it takes to aerate the water. After the circuit for aeration counts a series of four 1βs each D-flip flop in the circuits used for counting are reset. After a signal in the chain of D-flip flops reaches the third flip flop a fan is triggered to represent the completion of a full cycle or the light bulb coming on in our hydroponic garden.
8051 Program One of the requirements of the lab was to simulate the hydroponic garden using the 8051 microcontroller simulator. Using code generously provided by James Kelly we were able to understand how our setup could be simulated on the 8051 microcontroller. D. Options When creating the PLC program we were able to decide how we programmed the automated system. Using the Flowchart program many different variations of the same system could be created. Using breadboards we were able to create two different approaches to the given problem. One circuit was created to simulate an automated hydroponic garden, while the other used switches to trigger events. E. Problems Encountered During the lab, there was a problem encountered when using one of the counters on the PLC using one of the counters, and for our fail-safe, we had to resort using a counter that counted by seconds, instead of counts that we set ourselves. Another problem encountered was one while working on the circuit simulation in Logisim. When setting up a system to act as the water flowing, and then switching over to the aeration, using clocks and D-flip-flops, the system would not work properly after the first βaeration.β It was later discovered that we had to use a negative clock edge instead of a positive one to have the system work properly. On the breadboard, the circuit required two Dflip-flop chips instead of one, because there were two clear separate clears required for the system to function properly and it would not work if all of the flip-flops used were wired to the same clear. When creating the automated circuit we ran into several problems. The clears on the D-flip flop didnβt act as expected. The D-flip-flip that used a clock for both the input and clock didnβt work properly. This was solved by connecting the input high so the flip flop was able to properly store bits. Creating the circuits on the
8
pad trainer became somewhat difficult when connecting so many chips.
F. Testing Methodology The PLC and FPGA programs were simulated in Logisim before being implemented. Programs for the FPGA were simulated using the Xilinx software. Visual inspection and software assistance allowed us to catch and address potential problems. When creating the circuit on the PAD Trainer each chip was checked for errors before being used. Visual inspection of the output LEDs allowed us to determine whether each circuit was working properly. The connections from the relay to the fan were inspected. After losing several chips we paid more attention to the connections between the chips, board, and power source.
G. References [1] A. Kenneth, β8051 Microcontroller: Architecture, Programming and Applicationsβ, New York, 1996
9
H. Appendices Spec. Sheets
10
11
12
13
14
15
16
State Tables Three Bit Counter Resets Table A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
DA 0 0 0 1 1 1 1 0
DB 0 1 1 0 0 1 1 0
Dc 1 0 1 0 1 0 1 0
Simplification Maps π·π΄ = π΄π΅ + π΄π΅πΆ + π΄π΅πΆ 1 1 1 1 π·π΅ = πΆπ΅ + πΆπ΅ = π΅ β πΆ 1 1 1 1 π·πΆ = π΅ πΆ + π΅πΆ = (π΅ + π΅)πΆ = πΆ 1 1 1 1 Rail Logic used in non-automated
17
Three Bit Counter Doesnβt Reset Table A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
DA 0 0 0 1 1 1 1 1
DB 0 1 1 0 0 1 1 1
Dc 1 0 1 0 1 0 1 1
Simplification Maps π·π΄ = π΄ + π΅πΆ 1 1 1 1 1 π·π΅ = π΅πΆ + π΅πΆ + π΄π΅ = (π΅ β πΆ) + π΄π΅ 1 1 1 1 1 π·πΆ = π΅ πΆ + π΅πΆ + π΄π΅ = (π΅ + π΅)πΆ + π΄π΅ = πΆ + π΄π΅ 1 1 1 1 1 Two Bit Sequential Circuit A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
X 0 1 0 1 0 1 0 1
DB 0 0 0 1 1 1 1 0
Dc 0 1 1 0 0 1 1 0
Simplification Maps π·π΄ = π΅π + AX 1 1 1 π·π΅ = π΅π + π΄π 1 1 1 π = π΅π΄π 1 18
Rail Logic Rail Logic used in non-automated
19
Xilinx Diagram
20
Xilinx Constraint File
21
PLC Flowchart
22
23
24
