Influence of the architecture on ADC error modeling - Semantic Scholar
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Influence of the Architecture on ADC Error Modeling Pasquale Arpaia, Member, IEEE, Pasquale Daponte, Member, IEEE, and Linus Michaeli Abstract—The influence of the architecture on analog-to-digital converter modeling is investigated for the three most widespread architectures: integrating, successive approximations, and flash. The effects of main error sources are analyzed in terms of integral and differential nonlinearity with the aim of setting up a unified error model. Such a model is useful both to economically generate a look-up table for error correction and to quickly produce diagnosis models for fault detection and isolation. Numerical simulations aimed to show the model effectiveness and experimental tests carried out to validate the model are discussed.
Fig. 1. General error model of ADC.
Index Terms— Analog–digital conversion, error analysis, integrated circuit testing, measurement, measurement errors, modeling.
I. INTRODUCTION
A
NALOG-TO-DIGITAL converters (ADC’s) are the basic components of digital measurement systems and can have a significant impact on dynamic range, distortions and error in general. As in other fields, in ADC error investigation the use of models is becoming more widespread [1], [2]. Models of actual ADC’s allow error characteristics to be analyzed and, hence, correction to be carried out more easily. Furthermore, in diagnostic processes, fault models are used in order to detect and isolate possible fault conditions [2]. Several error models have been proposed to describe ADC behavior [3]–[5]. From a behavioral model such as proposed by Irons [6], some proposals [7]–[16] were set up to compute corrections and linearize ADC transfer characteristic. While proposals based on device-level models are intrinsically devoted to a specific architecture, macromodels and behavioral models are useful for a more general modeling due to their higher level abstraction [17]. As an example, among various proposals dedicated to a specific architecture, the behavioral model proposed by Ruan [18], based on an analogical and a discrete state block, seems to be general and device-independent. However, such a model was described and identified referring only to a successive approximation converter. A critical review of the most recent developments in ADC error modeling [2], [19]–[22] shows that majority of proposed models are either strictly related to the conversion principle or take into account only a particular ADC typology, or a specific error [23]–[26]. Manuscript received September 15, 1996; revised June 24, 1999. P. Arpaia is with the Dipartimento di Ingegneria Elettrica, Universit`a di Napoli Federico II, 80125 Napoli, Italy (e-mail: [email protected]). P. Daponte is with the Facolt`a di Ingegneria, Universit`a del Sannio, 82100 Benevento, Italy (e-mail: [email protected]). L. Michaeli is with the Department of Electronics and Multimedial Telecommunications, Technical University of Kosice, 04120 Kosice, Slovak Republic (e-mail: [email protected]). Publisher Item Identifier S 0018-9456(99)08379-5.
Fig. 2. Dynamic error model.
In the following, a unified behavioral error model is proposed for the most widespread ADC architectures: integrating, successive approximation and flash. The model is derived by analyzing in detail the influence of the architecture on error modeling. Some criteria for the model identification are also given. Finally, the model validation is discussed by reporting results of numerical simulations and experimental tests on actual ADC’s. II. ERROR FEATURES FOR MAIN ADC ARCHITECTURES In an actual ADC of bit, the absolute error in terms of integral nonlinearity (INL) is usually expressed as the ( th transition level) difference between the input level to which corresponds the th output code bin and the related of an ideal ADC with the same bit number value (1) The differential nonlinearity (DNL) can be determined as (2) is the average of the actual code bin widths [28]. where From (1) a general error model (Fig. 1), based on an ideal ADC having a digital to analog (DAC) converter and an INL digital voltage source in a feedback loop, is derived. A model pointing out dynamic errors can be obtained by describing the error dependence on the input signal frequency (Fig. 2)
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(a)
(a)
(b) Fig. 4. (a) Block diagram and (b) error model of a dual slope integrating ADC.
A. The Integrating ADC (b)
(c) Fig. 3. Example of analysis in the output code bin domain of (a) ADC error characteristic, (b) low-frequency component, and (c) high-frequency component .
[6]. The model is characterized by different impacts of static and dynamic errors; in particular, the latter are modeled as dependent on the first derivative of the output signal [9]. When a sample and hold (S/H) is employed, the dynamic behavior of the acquisition chain as a whole is determined by S/H dynamic properties [29], and the ADC can be described by the model of Fig. 1. The heart of the model is the digital generator. Finding a suitable expression for the function , which usually depends on the ADC architecture, is the main problem of modeling. The idea underlying this work is the characterization of the error variation in the output code bin domain with the aim of finding an unifying concept for main ADC architectures. In particular, the influence of the expression is investigated in terms architecture on the of high-frequency and low-frequency components in the output (a) is code bin domain. In the example of Fig. 3, the decomposed into a low-frequency component (b), responsible for the macroscopic error trend in the output bin domain, and in a low-frequency component (c), responsible for the local error trend. With this aim, in the following the architecture of the most widespread conversion principles are analyzed: integrating, successive approximation, and flash.
Architectures of integrating ADC’s (e.g., dual, multi-slope, or voltage-frequency converters) are basically formed by an analog signal processing section, mainly based on a signal conditioner, an integrator, and a comparator, and a quantizing section, mainly including a counter. In particular, in Fig. 4(a) a block diagram of a dual-slope ADC is reported. The input signal , first conditioned by a suitable block, is integrated for a prefixed interval time measured by a digital counter. Then, the integrator is switched onto the reference until its capacity is returned to the initial condition in an interval time determined by the comparator and digitized by the counter. By imposing the equality of the charge exchanged during the two phases, the mean value of the input during is derived. In the architecture of Fig. 4(a), the conditioning block is a source of nonlinearity owing to actual amplifier response, parasitic effects in passive attenuators, and so on [30]–[32]. The reference is affected by intrinsic uncertainty, whereas the integrator introduces inaccuracies and nonlinear effects mainly owing to its limited bandwidth, finite response time, parasitic effects, and, particularly, dielectric absorption effects on the integrating capacity. The comparator also affects overall static accuracy with offset and hysteresis effects. The remaining blocks, apart from time quantization error, can be considered as negligible error sources. As a matter of fact, the integration for the input signal and for the reference signal times are derived from the same clock frequency and thus mainly short term instability of clock and a systematic delay of gate response arise. On this basis, the integrating ADC architecture has been modeled by two cascaded converters [Fig. 4(b)]: a first, converting analog input signal into a continuous time interval (Analog Signal Processing Section), and a second, coninto the code bin (Quantizing verting the time interval Section). All the nonlinear effects of the above described error sources are taken into account by the model of the nonlinear block in the Analog Signal Processing Section of Fig. 4(b). Consequently, the operations of signal conditioning, integration, and voltage-to-time conversion carried out in the corresponding
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blocks of Fig. 4(a) will be considered as ideal. Finally, an ideal quantizer will introduce the quantization error in the corresponding Quantizing Section. The behavior of the nonlinear block of the ideal Analog Signal Processing Section is modeled by a polynomial approximation (3) of order higher than 3 is The impact of the coefficients generally negligible [30], [31] for time intervals corresponding to the conversion times of modern integrating ADC’s for instrumentation (much longer than microseconds range). This is due mainly to the fact that the conversion principle does not intrinsically introduce any discontinuities in the signal processing, and, moreover, the integration process reduces variations in the amplitude domain. Furthermore, integrating converters for instrumentation exhibit transfer functions with only small deviations from their ideal linear trend. is ideally scaled in the conditioning The distorted signal block
Fig. 5. Error quantities at the input Signal Processing Section.
(1x) and the output (1y) of the Analog
Furthermore, from the (7) it results
(4) modeled as a multiplier by a constant . Subsequently, it is ideally integrated in the time interval
(9) where Section
is the ideal output of the Analog Signal Processing (10)
(5) Then, the integrated signal continuous time interval sponding block
is ideally converted to a [Fig. 4(b)] through the corre-
indicates the result of the ideal integration of the where input in the time interval , analogously to the (5). On this basis, the error function defined at the output of the Analog Signal Processing Section will result
(6) is the reference signal, and are the polynomial where coefficients of the final input-output relation of the Analog Signal Processing Section. is converted Finally, the actual continuous time interval into a digital code in the Quantizing Section, modeled as an ideal quantizer. This is obtained by rounding the time interval divided by the clock period round
(7)
This behavior of the actual converter has to be expressed in terms of the integral nonlinearity INL. However, rather than in terms of the relative displacement of the actual transition (i.e. an input level), the error analysis turns out level of the Analog to be easier in terms of the actual output Signal Processing Section. In particular, in modern ADC’s for instrumentation, the difference between actual and ideal transfer characteristic is generally lower than a code bin width can be expressed with (Fig. 5). Consequently, the satisfying approximation as (8)
(11) and, therefore, the integral nonlinearity could be estimated by
(12) This error model implies that the error function is expressed as a continuous analytical function. From a mathematical point of view, it can be modeled by a polynom, whose order is determined by the intrinsic low-order of the nonlinear model of the analog processing. Consequently, the will have a dominant low-frequency component in the code bin domain. B. The Successive Approximation ADC In this case, the conversion principle (Fig. 6) is based, as is widely known, on a digital-to-analog converter (DAC) in a feedback loop. The DAC is controlled by a digital value selected through a suitable weighting process. Main error sources in locating code bin transition levels are the comparator and the DAC. The comparator is affected
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If is the total voltage contribution given by the th branch of the circuit in Fig. 9, under all the above conditions, and according to the superposition principle, the DAC output is dependent upon binary codes (16) Fig. 6. Successive approximation conversion principle.
mostly by a constant error due to offset and drift ef, depending on the code bin fects, and an error (with or ), due to the comparator hysteresis effect (13) is the least significant bit of the code . The DAC where is given by output voltage (14) is the DAC error. where At the end of conversion, the input , ideally corresponding to the code bin , will be comprised between the two successive actual transition levels
(15) Equation (15) gives the error limits for the code . In the cases of multiplying DAC’s with switched voltage sources and switched current sources, the circuit schemes have a similar structure shown in Fig. 7. As an example, the basic error characteristics of multiplying DAC’s with switched voltage sources are shown in the following. The main errors are (Fig. 7) ; 1) reference voltage error ; 2) resistor errors in the weighting networks 3) nonlinearities of the voltage and current output characteristics of the digital controlled analog switches . In the hypothesis that the switch commutation does not affect voltages and currents in this network, according to the and can compensation principle, the resistor errors be substituted by voltage sources (Fig. 8). In the hypothesis of nonlinear characteristic equality for switches in both positions, the nonzero voltage across the actual switches (or the leakage current parallel to the current switches) can be included in these sources, too. (which compensates The effect of the sources in longitudinal branches) for the effect of resistor errors can be transposed beyond the nodes to the transversal branches . Furthermore, the effect and modeled by the sources can be replaced by of the reference source in nodes using Thevenin’s theorem with the voltage sources . In this case the DAC circuit is simplified as shown in Fig. 9.
By combining (15) and (16) the DAC error function is a distinct reference inaccuracies linear combination of the having as weighting coefficients the values of the single bits [31], [33]–[35]. Distinct error sources arise periodically along the code bin scale at setting the various bits in the error effects scale. In particular, it will be only distinct on the ADC output, each one arising along the scale with an own periodicity. Hence, the ADC error presents different periodicities along the scale, each related to the periodicity of a single bit in the binary code. These independent periodical effects have been modeled through a multiperiodical model for differential nonlinearity [33]. As shown in Table I, the differential nonlinearity has distinct values, each one arising correspondingly to only the code bin (17) and each one having periodicity eled differential nonlinearity values experimental
. Consequently, the modis derived from the
(18) Equation (18) implies that the minimum number of indesamples for the model identification is . pendent In this way, all the DNL values are estimated with only experimental values (i.e. measurements of code transition levels). In order to increase the accuracy, in the determination the code bin number having homologous DNL of values should be large. The maximum accuracy of the model is achieved when all the homologous code bins are taken into account (19) Hence, the number of experimental values used for the modevaluation belongs to the interval . eled is derived as the sum of the However, since the values, the biases of estimate errors are added, and in practice this evaluation is not feasible. The has to be filtered to obtain a unbiased differential nonlinearity
(20)
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Fig. 7. Circuit scheme for a multiplying DAC with switched voltage sources.
Fig. 8. Circuit scheme for a multiplying DAC obtained from Fig. 7 by substituting resistor errors compensation principle.
R
di
and
R
Di
with voltage sources according to
Fig. 9. Circuit scheme for a multiplying DAC obtained from Fig. 8 by substituting the effect of the reference source in nodes voltage sources (ki UR =2 1 2i01 ) according to the Thevenin’s theorem.
where
is the number of code bins
(21)
C. The Flash ADC In flash ADC’s (Fig. 10) the input signal is simultaneously connected to several comparators [15]. The other input of the comparators is connected to suitable scaled voltage sources.
A; B;
. . . N with the
Then the conversion in a binary value is carried out in a decoding circuit. The number of conversion phases depends on the architecture variants. In the most simple, the conversion is carried out in one step; in this case, several comparators connected to voltage sources, created from a unique standard voltage source by a divider, are needed. Hence, the static component of the error is determined by the errors of the reference voltages. Another variant is the serial-parallel architecture, where the output value is achieved by several steps of parallel conversion with
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TABLE I MULTIPERIODICAL MODEL FOR SUCCESSIVE APPROXIMATIONS ADC’s
Fig. 11. Proposed unified model for an actual ADC.
Fig. 10.
Flash conversion principle.
increasing resolution from coarse to fine digital values. By increasing the number of conversion phases the error function is a repetition of the error features of the single parallel structure. The flash architecture nonidealities give rise to two INL components in the output code bin domain: 1) at low frequency and 2) at high frequency. The low-frequency component is mainly due to the following error sources: 1) nonlinear transfer function of the input buffer amplifier; 2) slowly variable offset of the common voltage of comparators; 3) increasing value of the current flowing across the voltage divider due to the nonzero comparator input currents; 4) internal thermal effects increasing with outputs resistors. Since these error sources act continuously across the scale, the low-frequency INL component has a polynomial characteristic. Owing to the intrinsic DNL capability of expressing the error as a function of the single code bin (i.e. locally in the code bin domain), the INL high-frequency component is better represented in terms of DNL. In particular, the DNL can be also subdivided into two main components: , due to the effects of systematic error sources 1) inside the ADC architecture; to the effects of random errors mainly related 2) to the nonidealities of divider resistors. component the possible sources of systemFor the atic errors are 1) periodical current absorption from the supply for different values of output (i.e. odd and even output codes);
2) periodicity of the basic error properties in the multistep serial-parallel architecture variant (i.e., the systematic error sources operate in succession in the cascade stages). component is generally adjusted to be negligible The through trimming procedures carried compared to out in the last stage of production cycle. In some cases, the above mentioned periodical effects of error sources give rise to a dominant periodicity feature for responsible for the INL high-frequency component. Differently from successive approximation converters, the flash DNL period is constant, and easily obtainable through a regression analysis with low correlation errors. Since averaging algorithms filter stochastic components, the is estimated by averaging the differential nonlinearity samples of the corresponding code bins
(22) where
is the DNL period. III. UNIFIED ERROR MODEL
The analysis of the three ADC classes highlighted two main components of the error in the output code domain: at low frequency and at high frequency. In particular: • the continuous error function of integrating ADC’s can be modeled in terms of INL by means of a low-frequency analytical function through a polynomial model; • the successive approximation ADC error characteristic can be modeled in terms of DNL as a function having dominant high-frequency components through a multiperiodical model; • the flash ADC error characteristic can be modeled in terms of both 1) a low-frequency component expressed in terms of INL through a polynomial model, and 2) a high-frequency component expressed in terms of DNL through a periodical model. On this basis, a unified model (Fig. 11) capable of taking into account both the low-frequency error component, expressed in terms of INL through a polynomial model, and the highfrequency component, expressed in terms of DNL through a multiperiodical or periodical model, has been proposed. The model is derived from the one of Fig. 1, by particularizing
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the block according to the ADC architecture. It is composed of two paths (Fig. 11): 1) in the upper, the lowfrequency INL is estimated through smoothing techniques and the polynomial model of (12), and 2) in the lower, the high-frequency INL local discontinuities are modeled related to the ADC through a periodical unbiased architecture. The results of the two feedback processing blocks are then summed and ideally converted to analog values. The low-frequency component is obtained 1) by applying a experimenmoving-window average algorithm to the tal values (23)
where is the DNL period. In most frequent cases, flash . It implies ADC’s are characterized by a periodicity that (28) Since and (29) it is derived that
is the window length, and 2) by using the where values to identify the polynomial model. The high-frequency component is determined as
(30)
(24) From these values, the corresponding DNL is determined through (2)
(25) is the integral nonlinearity corresponding to the where defined by (20), and is the differential unbiased defined by (23). The nonlinearity corresponding to the is made negligible by a suitable selection of term window length, thus the unified model results (26) In the case of the integrating ADC, the INL is approximated and the DNL-based term by the continuous function of (26) is negligible. On the other hand, for the successive approximation ADC the error has a multiperiodical characteristic and in the model (26) the first term is almost null. The flash ADC is modeled by both the terms by estimating simultaneously. Owing to the periodicity of , (26) is simplified
(27)
that expresses the unified model in the case of a flash having .
IV. CRITERIA
FOR
MODEL IDENTIFICATION
For integrating ADC’s the polynom order of the lowis derived as the maximum frequency component value that, if increased, does not significantly improve the model accuracy. It is evaluated by estimating the model for increasing values of , until differences in correspondvalues are negligible. The determination of ing through the least the polynom coefficients mean squared deviation method requires a high number of operations and experimental INL samples. More efficient methods are available for this aim (spline cubic approximation, Lagrange polynom, Newton approximation, and so on [36]). In particular, the spline cubic has a stable solution when the approximation points are equally spaced in the measuring range. Only a few INL sample sets (e.g., three) equispaced across the full-scale have to be recorded. Each set includes a few of the INL samples related to successive code bins and measured through standard techniques [28]. The basic problem is how many samples are needed for a given accuracy. When the INL function does not have any three experimental points are sufficient inflection point for spline cubic interpolation. In general, the number of . However, points needed is determined as: is not known in advance. One way to find an generally is the comparison of two approximation results optimum and . The first approximation is carried with out by 3 interpolation points: the first in the middle and the other two near the opposite borders of the measuring range. The next approximation is performed using four points , where two of them are close to the range limits. The approximation is assessed by the absolute difference between the estimates of two splines functions (e.g.,
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TABLE II SIMULATION VALUES OF THE UNIFIED MODEL PARAMETERS (R: IDENTIFICATION RANGES, FS: FULLSCALE)
obtained for
) in the points
and (31)
where is a prefixed significance threshold (e.g., a percent of the maximum INL). The further approximation should be and . In this case, performed in the points condition (31) will be checked in the interleaving points and . If a better approximation is needed, the accuracy of each selected experimental point can be improved by repeating the measurement in the same conditions. The repetition factor for in the scale can be each point and the number of points optimized as proposed in [37]. For the successive approximation ADC’s, the experimental DNL samples are derived as indicated in Table I, and the is an average value. The number modeled value used for comof measured DNL values and puting could be lower than the maximum value this depends on the accuracy of the measured values during the testing phase. In practice, values between half and three-quarter of full-scale are the best. As far as flash ADC’s are concerned, the experimental samples have to be taken at a constant code bin (DNL period). The value of depends on the distance architecture (number of phases in the serial-parallel variant) or the internal chip layout. A practical way to estimate is the correlation analysis of measured data in close subranges of the scale (in practice, values in the subrange between half and three-quarter of full-scale are the best). The optimum is and the value showing the highest similarity between represented by the highest correlation coefficient. The different values of DNL are obtained as the average value
(32) The number of data required for averaging belongs to the . interval V. NUMERICAL
AND
EXPERIMENTAL RESULTS
In the following, some sample results of numerical and experimental tests related to the validation and the identification of the unified model are discussed for the three
(a)
(b)
(c) Fig. 12. Example of INL (a) experimental and model simulation results obtained through least squared deviations (b) (MSD: 0.098LSB), and (c) spline cubic (MSD: 0.13LSB) interpolations for ICL7109CPL 12 bit integrating ADC.
aforementioned ADC classes. The maximum confidence in the model validation was attained by identifying the model with the maximum accuracy achievable with all the experimental samples, ignoring the experimental burden. Numerical simulations were performed by implementing models in MATLAB. Experimental tests were carried out by means of a measuring station mainly based on 1) calibrator Fluke 5442A; 2) digital I/O of the board Advantech PCL-812PG; 3) National Instruments IEEE 488.2 interface board; 4) 386 IBM-compatible PC. and values were derived from Experimental the code transition levels obtained through the IEEE 1057 standard static method [28]. Gain and offset errors were estimated
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(a)
(a)
(b) Fig. 13. Example of (a) experimental and (b) model simulation DNL results, (MSD: 0.061LSB) for AD7880BN 12 bit successive approximation ADC (particular on code bin range: 2500–3000).
and corrected through algorithms of the same standard. As far as integrating ADC’s are concerned, in Fig. 12 a validation example of the polynomial branch of the unified model is shown for an actual 12-bit dual slope ADC. The comparison between experimental (a) and simulation results, obtained through the least square interpolation method (b) on 4096 experimental points, highlights the model effectiveness. In Table II, the corresponding values of the model parameters obtained in the identification through the least square interpolating method are reported. Furthermore, Fig. 12, this identification method (b) is compared with a spline cubic interpolation (c). The estimate error [expressed as mean square deviation (MSD)] is 0.098LSB for the least square method and 0.13LSB for spline cubic method, respectively. The small difference in model accuracy does not justify the increase in experimental burden: 4096 INL experimental measures for the least-square case, and only 45 (i.e., 15 sets of three points each) for the spline cubic. As far as successive approximation ADC’s are concerned, in Fig. 13 a validation example of the multiperiodical branch of the unified model is shown for an actual ADC of 12 bit . In order to better highlight the multiperiodicity, for sake of clarity the particulars related to code bin range from 2500 to 3000 of DNL results are shown. Also in this case, the comparison among (a) experimental and (b) simulation results indicates the model effectiveness. was Each value of the 12 DNL independent points obtained by averaging the maximum number of experimental points reported in Table II. As far as flash ADC’s are concerned, in Fig. 14, for an actual 8 bit ADC example, INL (a) experimental and (b) simulation results are compared. In this case, for the identification of the model polynomial path, a spline cubic interpolation on six sets, each of three points, was carried out. The MSD obtained is equal to 0.068LSB. In Fig. 14(c) and (d), the corresponding polynomial low-frequency and periodical components are highlighted, respectively. The high-frequency
(b)
(c)
(d) Fig. 14. Example of (a) experimental and (b) simulation INL results, (MSD: 0.068LSB) for MP7684KN 8 bit flash ADC. Particular of (c) low-frequency and (d) high-frequency components.
periodicity is shown in Fig. 15, where DNL (a) experimental and (b) simulation results are compared. The MSD obtained is equal to 0.014LSB. VI. CONCLUSION Starting from the theoretical model of Fig. 1, the analysis of the error characteristics for the most widespread
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(a)
(b) Fig. 15. Periodical (p = 2) high-frequency component expressed in terms of DNL for the same flash ADC of Fig. 13: (a) experimental and (b) simulation results (MSD: 0.014LSB).
ADC architectures (integrating, successive approximations and to be modeled in flash) allowed the feedback block an unified way (Fig. 11). Integrating ADC errors have a polynomial dominant nature, and correspondingly, the unified model lower path has null output value. Discontinuities in INL typical of successive approximation or flash architecture are more accurately taken into account in terms of DNL through a periodical model. The periodicity is multiple for successive approximation ADC’s and constant for flash ADC’s. However, in the flash case, the simplification involved by the symmetry of the modeled DNL does not allow the INL error spread over the whole measuring range to be characterized. Thus, a further polynomial model for INL description is also necessary. The static model effectiveness in experimental validation suggested further investigation on dynamic ADC behavior [39], [40]. Current work is now devoted to define the applicability limits of the general model. REFERENCES [1] A. Van den Bos and P. Eykhoff, “Model building and parameter estimation as means for intelligent measurement,” Measurement, vol. 6, pp. 25–32, Jan.–Mar. 1988. [2] Proc. 3rd Int. IMEKO Workshop ADC Modeling and Testing, P. Daponte and L. Michaeli, Eds., Napoli, Italy, Sept. 1998. [3] R. J. Patton, J. Chen, and S. B. Nielsen, “Model-based methods for fault diagnosis: Some guidelines,” Trans. Inst. Meas. Contr., vol. 17, no. 2, pp. 73–83, 1995. [4] S. Brigati, V. Liberali, and F. Maloberti, “Precision behavioral modeling of circuit components for data converters,” in Proc. IEE Conf. Advanced A-D D-A Conversion Techniques Applications, Cambridge, U.K., July 6–8, 1994, pp. 110–115. [5] P. Arpaia, F. Cennamo, P. Daponte, and M. D’Apuzzo, “A behavioral model for scan converter-based transient digitizers,” Measurement, vol. 17, no. 2, 1996. [6] D. Asta and F. H. Irons, “Dynamic error compensation of analogto-digital converters,” Lincoln Lab. J., vol. 2, no. 2, pp. 161–182, 1989. [7] E. A. Sloane, “System of converter testing using Walsh transform techniques,” in Proc. Int. Test Conf., Philadelphia, PA, Oct. 27–29, 1981.
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[8] M. V. Bossche, J. Schoukens, and J. Renneboog, “Dynamic testing and diagnostics of A/D converters,” IEEE Trans. Circuits Syst., vol. CAS-33, pp. 773–785, Aug. 1986. [9] T. A. Rebold and F. H. Irons, “A phase-plane approach to the compensation of high-speed analog-to-digital converters,” in IEEE Int. Symp. Circuits Syst., Philadelphia, PA, May 4–7, 1987, pp. 455–458. [10] F. H. Irons, D. M. Hummels, and S. P. Kennedy, “Improved compensation for analog-to-digital converters,” IEEE Trans. Circuits Syst., vol. 38, pp. 958–961, Aug. 1991. [11] Y. C. Jenq, “Digital spectra of nonuniformly sampled signals: Fundamentals and high-speed waveform digitizers,” IEEE Trans. Instrum. Meas., vol. 37, pp. 245–251, June 1988. [12] E. G. Soenen, P. M. Vanpeteghem, H. Liu, S. Narayan, and J. T. Cummings, “A framework for design and testing of analog integrated circuits,” IEEE Trans. Instrum. Meas., vol. 39, pp. 890–893, Dec. 1990. [13] A. Petraglia and S. K. Mitra, “Analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizers,” IEEE Trans. Instrum. Meas., vol. 40, pp. 831–835, Oct. 1991. [14] N. Giaquinto, M. Savino, and A. Trotta, “Testing and optimizing ADC performance: A probabilistic approach,” IEEE Trans. Instrum. Meas., vol. 45, pp. 621–626, Apr. 1996. [15] M. F. Wagdy and P. Xie, “Comparative ADC performance evaluation using a new emulation model for flash ADC architectures,” in Proc. 37th Mid-West Symp. Circuits Syst., Lafayette, LA, Aug. 3–5, 1994. [16] F. Cennamo, P. Daponte, M. D’Apuzzo, and M. Savastano, “Dynamic testing and diagnostics of digitizing signal analyzer,” IEEE Trans. Instrum. Meas., vol. 41, pp. 840–844, Dec. 1992. [17] A. Baccigalupi, P. Daponte, and M. D’Apuzzo, “An improved error model of data acquisition systems,” IEEE Trans. Instrum. Meas., vol. 43, pp. 220–225, 1994. [18] G. Ruan, “A behavioral model of A/D converters using a mixed-mode simulator,” IEEE J. Solid-State Circuits, vol. 26, Mar. 1991. [19] J. Kuffel, R. Malewsky, and R. van Heeswijk, “Modeling of the dynamic performance of transient recorders used for high voltage impulse tests,” IEEE Trans. Power Delivery, vol. 6, pp. 507–515, Apr. 1991. [20] P. Arpaia, F. Cennamo, P. Daponte, and M. D’Apuzzo, “Dynamic characterization of scan conversion-based transient digitizers,” IEEE Trans. Instrum. Meas., vol. 44, June 1995. [21] P. Arpaia, F. Cennamo, P. Daponte, and M. D’Apuzzo, “Performance enhancement of scan conversion-based transient digitizers,” IEEE Trans. Instrum. Meas., vol. 45, pp. 422–425, Apr. 1996. [22] G. N. Stenbakken and T. M. Souders, “Developing linear error models for analog devices,” IEEE Trans. Instrum. Meas., vol. 43, pp. 157–163, Apr. 1994. [23] M. T. Abuelma’Atti, “Effect of bit-threshold errors on the harmonic and intermodulation performance of successive approximation A/D converters,” IEEE Trans. Commun., vol. 41, pp. 1155–1560, Aug. 1993. [24] B. Boser and B. Wooley, “The design of sigma-delta modulation analogto-digital converters,” IEEE J. Solid-State Circuits, vol. 33, Dec. 1988. [25] K. H. Hadidi and G. C. Temes, “Error analysis in pipeline A/D converters and its applications,” IEEE Trans. Circuits Syst., vol. 39, pp. 506–515, Aug. 1992. [26] K. Kim, “Analog-to-digital conversion and harmonic noises due to the integral nonlinearity,” IEEE Trans. Instrum. Meas., vol. 43, pp. 151–156, Apr. 1994. [27] M. F. Wagdy, “Validity of uniform error model for sinusoidal signals without and with dither,” IEEE Trans. Instrum. Meas., vol. 38, pp. 718–722, Apr. 1989. [28] IEEE Standard for Digitizing Waveform Recorders, IEEE Std. 1057, Dec. 1994. [29] D. Mirri, G. Iuculano, F. Filicori, G. Pasini, and G. Vannini, “Modeling of non ideal dynamic characteristics in S/H-ADC devices,” in Proc. IEEE Conf. Instrum. Meas., IMTC/95, Waltham, MA, Apr. 1995, pp. 27–32. [30] H. M. Paynter, Analysis and Design of Engineering Systems. London, U.K.: Harrap, 1961. [31] L. Michaeli, “Error analysis of the integrating ADC with nonlinear transfer characteristic,” Ph.D. dissertation, Slovak Technical Univ., Bratislava, Slovak Republic, 1979. , “A fast method for correction of systematic errors of ADC in [32] histogram measurements,” in Proc. IMEKO 10th Int. Congr., Prague, Czech Republic, 1985, vol. 2, pp. 40–47. [33] L. O. Chua, C. A. Desoer, and E. S. Kuh, Linear and Nonlinear Circuits. New York: McGraw-Hill, 1987. [34] L. Michaeli, “Computer simulation of autocalibration for successive approximation ADC,” in Proc. II Int. IMEKO TC-4 Symp., Warsaw, Poland, May 26–28, 1987, pp. 125–131.
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[35] K. Hejn and I. Kale, “Some theorems on Walsh transforms of quantizer differential and integral nonlinearity,” IEEE Trans. Instrum. Meas., vol. 41, pp. 218–225, Apr. 1992. [36] C. Young, “An enhanced method for characterizing successive approximation converters,” IEEE Trans. Instrum. Meas., vol. 39, pp. 335–339, Apr. 1990. [37] E. Kreyszig, Advanced Engineering Mathematics 7th ed. New York: Wiley, 1993. [38] G. Betta and M. Dell’Isola, “An optimized approach to sensor calibration design,” in Proc. IEEE IMTC/93 Conf., Irvine, CA, 1993, pp. 316–322. [39] P. Arpaia, P. Daponte, and L. Michaeli, “Analytical A-priori approach to phase plane modeling of SAR A/D converters,” IEEE Trans. Instrum. Meas., vol. 47, pp. 849–857, Aug. 1998. [40] P. Arpaia, P. Daponte, and L. Michaeli, “A dynamic error model for integrating analog-to-digital converters,” Measurement, vol. 25, no. 4, pp. 255–264, 1999.
Pasquale Arpaia (M’99) was born in Napoli, Italy, in 1961. He teaches electrical measurement at the University of Napoli, Federico II. He has been Consultant on the EU IV Framework Program Standard Measurement and Testing and Evaluator for EU INTAS projects. He is Consultant to the Physikalisch-Technische Bundesanstalt, Berlin, Germany, in the field of ADC metrological characterization. He is responsible for the Promoting Committee of the EUPAS Project of the IMEKO TC-4 A/D and D/A Metrology Workgroup, and is voting member of the IEEE IM TC-10 Waveform Measurement and Analysis. He is Associate Editor of the journal Computer Standards & Interfaces. He has organized some international meetings in the field of electronic measurements and European cooperation. His main research interests include ADC modeling, testing, and standardization, measurement systems on geographic networks, and statisticalbased characterization of measurement systems. In this field, he has published more than 60 scientific papers. Dr. Arpaia is a member of the Electrical and Electronic Measurements Group of the National Council of Research, the Italian Electrical Engineering Association, the IMEKO TC-4 WG on A/D and D/A Metrology, the IEEE Instrumentation and Measurement Society, the IEEE Components, Packaging, and Manufacturing Technology Society, and the European Committee for Electrolytic Corrosion.
Pasquale Daponte (M’91) was born in Minori, Italy, in 1957. Since 1994, he has been teaching digital signal processing and measurement information at the Faculty of Computer Engineering, University of Sannio, Benevento, Italy. He is member of the editorial board of the journal Measurement, as well as of the board of the Italian Society for Computer Simulation. He is coordinator of the IMEKO Working Group on A/D and D/A Metrology. His main research interests are wavelet-based digital signal processing for the harmonic analysis in electrical power systems and for the thin thickness measurements; A/D and D/A metrological characterization; artificial neural network for signal processing; and computer networking for distributed measurement systems. He published more than 130 scientific papers in journals and national and international conference proceedings. He has organized some national or international meetings in the field of electronic measurements and European cooperation. Dr. Daponte is a member of the Scientific Committee of the Electrical and Electronic Measurements Group, the National Council of Research, Italian Electrical Engineering Association, IEEE Instrumentation and Measurement Society, Italian Society for Computer Simulation, and Societas Internationalis pro Diagnostica Ultrasonica in Opthalmologia. In 1987, he received an award from the Italian Society of Oftalmology for studies on the digital signal processing of the ultrasounds in echo-oftalmology.
Linus Michaeli was born in the Slovak Republic in 1945. He received the M.S. degree in electrical engineering from the Technical University of Transport, Zilina, Slovak Republic, in 1968, and the Ph.D. degree in measurement technology Slovak Technical University, Bratislava, in 1979. Since 1994, he has been a Full Professor with the Department of Electronics and Multimedia Telecommunications, Technical University of Kosice, Kosice, Slovak Republic. His main research interests are in ADC modeling and testing and artificial neural network for measurement signal processing. He is a member of the editorial board of the Computer Standards and Interfaces. Dr. Michaeli is the Slovak member of the IMEKO TC4.
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Influence of the Architecture on ADC Error Modeling Pasquale Arpaia, Member, IEEE, Pasquale Daponte, Member, IEEE, and Linus Michaeli Abstract—The influence of the architecture on analog-to-digital converter modeling is investigated for the three most widespread architectures: integrating, successive approximations, and flash. The effects of main error sources are analyzed in terms of integral and differential nonlinearity with the aim of setting up a unified error model. Such a model is useful both to economically generate a look-up table for error correction and to quickly produce diagnosis models for fault detection and isolation. Numerical simulations aimed to show the model effectiveness and experimental tests carried out to validate the model are discussed.
Fig. 1. General error model of ADC.
Index Terms— Analog–digital conversion, error analysis, integrated circuit testing, measurement, measurement errors, modeling.
I. INTRODUCTION
A
NALOG-TO-DIGITAL converters (ADC’s) are the basic components of digital measurement systems and can have a significant impact on dynamic range, distortions and error in general. As in other fields, in ADC error investigation the use of models is becoming more widespread [1], [2]. Models of actual ADC’s allow error characteristics to be analyzed and, hence, correction to be carried out more easily. Furthermore, in diagnostic processes, fault models are used in order to detect and isolate possible fault conditions [2]. Several error models have been proposed to describe ADC behavior [3]–[5]. From a behavioral model such as proposed by Irons [6], some proposals [7]–[16] were set up to compute corrections and linearize ADC transfer characteristic. While proposals based on device-level models are intrinsically devoted to a specific architecture, macromodels and behavioral models are useful for a more general modeling due to their higher level abstraction [17]. As an example, among various proposals dedicated to a specific architecture, the behavioral model proposed by Ruan [18], based on an analogical and a discrete state block, seems to be general and device-independent. However, such a model was described and identified referring only to a successive approximation converter. A critical review of the most recent developments in ADC error modeling [2], [19]–[22] shows that majority of proposed models are either strictly related to the conversion principle or take into account only a particular ADC typology, or a specific error [23]–[26]. Manuscript received September 15, 1996; revised June 24, 1999. P. Arpaia is with the Dipartimento di Ingegneria Elettrica, Universit`a di Napoli Federico II, 80125 Napoli, Italy (e-mail: [email protected]). P. Daponte is with the Facolt`a di Ingegneria, Universit`a del Sannio, 82100 Benevento, Italy (e-mail: [email protected]). L. Michaeli is with the Department of Electronics and Multimedial Telecommunications, Technical University of Kosice, 04120 Kosice, Slovak Republic (e-mail: [email protected]). Publisher Item Identifier S 0018-9456(99)08379-5.
Fig. 2. Dynamic error model.
In the following, a unified behavioral error model is proposed for the most widespread ADC architectures: integrating, successive approximation and flash. The model is derived by analyzing in detail the influence of the architecture on error modeling. Some criteria for the model identification are also given. Finally, the model validation is discussed by reporting results of numerical simulations and experimental tests on actual ADC’s. II. ERROR FEATURES FOR MAIN ADC ARCHITECTURES In an actual ADC of bit, the absolute error in terms of integral nonlinearity (INL) is usually expressed as the ( th transition level) difference between the input level to which corresponds the th output code bin and the related of an ideal ADC with the same bit number value (1) The differential nonlinearity (DNL) can be determined as (2) is the average of the actual code bin widths [28]. where From (1) a general error model (Fig. 1), based on an ideal ADC having a digital to analog (DAC) converter and an INL digital voltage source in a feedback loop, is derived. A model pointing out dynamic errors can be obtained by describing the error dependence on the input signal frequency (Fig. 2)
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(a)
(a)
(b) Fig. 4. (a) Block diagram and (b) error model of a dual slope integrating ADC.
A. The Integrating ADC (b)
(c) Fig. 3. Example of analysis in the output code bin domain of (a) ADC error characteristic, (b) low-frequency component, and (c) high-frequency component .
[6]. The model is characterized by different impacts of static and dynamic errors; in particular, the latter are modeled as dependent on the first derivative of the output signal [9]. When a sample and hold (S/H) is employed, the dynamic behavior of the acquisition chain as a whole is determined by S/H dynamic properties [29], and the ADC can be described by the model of Fig. 1. The heart of the model is the digital generator. Finding a suitable expression for the function , which usually depends on the ADC architecture, is the main problem of modeling. The idea underlying this work is the characterization of the error variation in the output code bin domain with the aim of finding an unifying concept for main ADC architectures. In particular, the influence of the expression is investigated in terms architecture on the of high-frequency and low-frequency components in the output (a) is code bin domain. In the example of Fig. 3, the decomposed into a low-frequency component (b), responsible for the macroscopic error trend in the output bin domain, and in a low-frequency component (c), responsible for the local error trend. With this aim, in the following the architecture of the most widespread conversion principles are analyzed: integrating, successive approximation, and flash.
Architectures of integrating ADC’s (e.g., dual, multi-slope, or voltage-frequency converters) are basically formed by an analog signal processing section, mainly based on a signal conditioner, an integrator, and a comparator, and a quantizing section, mainly including a counter. In particular, in Fig. 4(a) a block diagram of a dual-slope ADC is reported. The input signal , first conditioned by a suitable block, is integrated for a prefixed interval time measured by a digital counter. Then, the integrator is switched onto the reference until its capacity is returned to the initial condition in an interval time determined by the comparator and digitized by the counter. By imposing the equality of the charge exchanged during the two phases, the mean value of the input during is derived. In the architecture of Fig. 4(a), the conditioning block is a source of nonlinearity owing to actual amplifier response, parasitic effects in passive attenuators, and so on [30]–[32]. The reference is affected by intrinsic uncertainty, whereas the integrator introduces inaccuracies and nonlinear effects mainly owing to its limited bandwidth, finite response time, parasitic effects, and, particularly, dielectric absorption effects on the integrating capacity. The comparator also affects overall static accuracy with offset and hysteresis effects. The remaining blocks, apart from time quantization error, can be considered as negligible error sources. As a matter of fact, the integration for the input signal and for the reference signal times are derived from the same clock frequency and thus mainly short term instability of clock and a systematic delay of gate response arise. On this basis, the integrating ADC architecture has been modeled by two cascaded converters [Fig. 4(b)]: a first, converting analog input signal into a continuous time interval (Analog Signal Processing Section), and a second, coninto the code bin (Quantizing verting the time interval Section). All the nonlinear effects of the above described error sources are taken into account by the model of the nonlinear block in the Analog Signal Processing Section of Fig. 4(b). Consequently, the operations of signal conditioning, integration, and voltage-to-time conversion carried out in the corresponding
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blocks of Fig. 4(a) will be considered as ideal. Finally, an ideal quantizer will introduce the quantization error in the corresponding Quantizing Section. The behavior of the nonlinear block of the ideal Analog Signal Processing Section is modeled by a polynomial approximation (3) of order higher than 3 is The impact of the coefficients generally negligible [30], [31] for time intervals corresponding to the conversion times of modern integrating ADC’s for instrumentation (much longer than microseconds range). This is due mainly to the fact that the conversion principle does not intrinsically introduce any discontinuities in the signal processing, and, moreover, the integration process reduces variations in the amplitude domain. Furthermore, integrating converters for instrumentation exhibit transfer functions with only small deviations from their ideal linear trend. is ideally scaled in the conditioning The distorted signal block
Fig. 5. Error quantities at the input Signal Processing Section.
(1x) and the output (1y) of the Analog
Furthermore, from the (7) it results
(4) modeled as a multiplier by a constant . Subsequently, it is ideally integrated in the time interval
(9) where Section
is the ideal output of the Analog Signal Processing (10)
(5) Then, the integrated signal continuous time interval sponding block
is ideally converted to a [Fig. 4(b)] through the corre-
indicates the result of the ideal integration of the where input in the time interval , analogously to the (5). On this basis, the error function defined at the output of the Analog Signal Processing Section will result
(6) is the reference signal, and are the polynomial where coefficients of the final input-output relation of the Analog Signal Processing Section. is converted Finally, the actual continuous time interval into a digital code in the Quantizing Section, modeled as an ideal quantizer. This is obtained by rounding the time interval divided by the clock period round
(7)
This behavior of the actual converter has to be expressed in terms of the integral nonlinearity INL. However, rather than in terms of the relative displacement of the actual transition (i.e. an input level), the error analysis turns out level of the Analog to be easier in terms of the actual output Signal Processing Section. In particular, in modern ADC’s for instrumentation, the difference between actual and ideal transfer characteristic is generally lower than a code bin width can be expressed with (Fig. 5). Consequently, the satisfying approximation as (8)
(11) and, therefore, the integral nonlinearity could be estimated by
(12) This error model implies that the error function is expressed as a continuous analytical function. From a mathematical point of view, it can be modeled by a polynom, whose order is determined by the intrinsic low-order of the nonlinear model of the analog processing. Consequently, the will have a dominant low-frequency component in the code bin domain. B. The Successive Approximation ADC In this case, the conversion principle (Fig. 6) is based, as is widely known, on a digital-to-analog converter (DAC) in a feedback loop. The DAC is controlled by a digital value selected through a suitable weighting process. Main error sources in locating code bin transition levels are the comparator and the DAC. The comparator is affected
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If is the total voltage contribution given by the th branch of the circuit in Fig. 9, under all the above conditions, and according to the superposition principle, the DAC output is dependent upon binary codes (16) Fig. 6. Successive approximation conversion principle.
mostly by a constant error due to offset and drift ef, depending on the code bin fects, and an error (with or ), due to the comparator hysteresis effect (13) is the least significant bit of the code . The DAC where is given by output voltage (14) is the DAC error. where At the end of conversion, the input , ideally corresponding to the code bin , will be comprised between the two successive actual transition levels
(15) Equation (15) gives the error limits for the code . In the cases of multiplying DAC’s with switched voltage sources and switched current sources, the circuit schemes have a similar structure shown in Fig. 7. As an example, the basic error characteristics of multiplying DAC’s with switched voltage sources are shown in the following. The main errors are (Fig. 7) ; 1) reference voltage error ; 2) resistor errors in the weighting networks 3) nonlinearities of the voltage and current output characteristics of the digital controlled analog switches . In the hypothesis that the switch commutation does not affect voltages and currents in this network, according to the and can compensation principle, the resistor errors be substituted by voltage sources (Fig. 8). In the hypothesis of nonlinear characteristic equality for switches in both positions, the nonzero voltage across the actual switches (or the leakage current parallel to the current switches) can be included in these sources, too. (which compensates The effect of the sources in longitudinal branches) for the effect of resistor errors can be transposed beyond the nodes to the transversal branches . Furthermore, the effect and modeled by the sources can be replaced by of the reference source in nodes using Thevenin’s theorem with the voltage sources . In this case the DAC circuit is simplified as shown in Fig. 9.
By combining (15) and (16) the DAC error function is a distinct reference inaccuracies linear combination of the having as weighting coefficients the values of the single bits [31], [33]–[35]. Distinct error sources arise periodically along the code bin scale at setting the various bits in the error effects scale. In particular, it will be only distinct on the ADC output, each one arising along the scale with an own periodicity. Hence, the ADC error presents different periodicities along the scale, each related to the periodicity of a single bit in the binary code. These independent periodical effects have been modeled through a multiperiodical model for differential nonlinearity [33]. As shown in Table I, the differential nonlinearity has distinct values, each one arising correspondingly to only the code bin (17) and each one having periodicity eled differential nonlinearity values experimental
. Consequently, the modis derived from the
(18) Equation (18) implies that the minimum number of indesamples for the model identification is . pendent In this way, all the DNL values are estimated with only experimental values (i.e. measurements of code transition levels). In order to increase the accuracy, in the determination the code bin number having homologous DNL of values should be large. The maximum accuracy of the model is achieved when all the homologous code bins are taken into account (19) Hence, the number of experimental values used for the modevaluation belongs to the interval . eled is derived as the sum of the However, since the values, the biases of estimate errors are added, and in practice this evaluation is not feasible. The has to be filtered to obtain a unbiased differential nonlinearity
(20)
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Fig. 7. Circuit scheme for a multiplying DAC with switched voltage sources.
Fig. 8. Circuit scheme for a multiplying DAC obtained from Fig. 7 by substituting resistor errors compensation principle.
R
di
and
R
Di
with voltage sources according to
Fig. 9. Circuit scheme for a multiplying DAC obtained from Fig. 8 by substituting the effect of the reference source in nodes voltage sources (ki UR =2 1 2i01 ) according to the Thevenin’s theorem.
where
is the number of code bins
(21)
C. The Flash ADC In flash ADC’s (Fig. 10) the input signal is simultaneously connected to several comparators [15]. The other input of the comparators is connected to suitable scaled voltage sources.
A; B;
. . . N with the
Then the conversion in a binary value is carried out in a decoding circuit. The number of conversion phases depends on the architecture variants. In the most simple, the conversion is carried out in one step; in this case, several comparators connected to voltage sources, created from a unique standard voltage source by a divider, are needed. Hence, the static component of the error is determined by the errors of the reference voltages. Another variant is the serial-parallel architecture, where the output value is achieved by several steps of parallel conversion with
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TABLE I MULTIPERIODICAL MODEL FOR SUCCESSIVE APPROXIMATIONS ADC’s
Fig. 11. Proposed unified model for an actual ADC.
Fig. 10.
Flash conversion principle.
increasing resolution from coarse to fine digital values. By increasing the number of conversion phases the error function is a repetition of the error features of the single parallel structure. The flash architecture nonidealities give rise to two INL components in the output code bin domain: 1) at low frequency and 2) at high frequency. The low-frequency component is mainly due to the following error sources: 1) nonlinear transfer function of the input buffer amplifier; 2) slowly variable offset of the common voltage of comparators; 3) increasing value of the current flowing across the voltage divider due to the nonzero comparator input currents; 4) internal thermal effects increasing with outputs resistors. Since these error sources act continuously across the scale, the low-frequency INL component has a polynomial characteristic. Owing to the intrinsic DNL capability of expressing the error as a function of the single code bin (i.e. locally in the code bin domain), the INL high-frequency component is better represented in terms of DNL. In particular, the DNL can be also subdivided into two main components: , due to the effects of systematic error sources 1) inside the ADC architecture; to the effects of random errors mainly related 2) to the nonidealities of divider resistors. component the possible sources of systemFor the atic errors are 1) periodical current absorption from the supply for different values of output (i.e. odd and even output codes);
2) periodicity of the basic error properties in the multistep serial-parallel architecture variant (i.e., the systematic error sources operate in succession in the cascade stages). component is generally adjusted to be negligible The through trimming procedures carried compared to out in the last stage of production cycle. In some cases, the above mentioned periodical effects of error sources give rise to a dominant periodicity feature for responsible for the INL high-frequency component. Differently from successive approximation converters, the flash DNL period is constant, and easily obtainable through a regression analysis with low correlation errors. Since averaging algorithms filter stochastic components, the is estimated by averaging the differential nonlinearity samples of the corresponding code bins
(22) where
is the DNL period. III. UNIFIED ERROR MODEL
The analysis of the three ADC classes highlighted two main components of the error in the output code domain: at low frequency and at high frequency. In particular: • the continuous error function of integrating ADC’s can be modeled in terms of INL by means of a low-frequency analytical function through a polynomial model; • the successive approximation ADC error characteristic can be modeled in terms of DNL as a function having dominant high-frequency components through a multiperiodical model; • the flash ADC error characteristic can be modeled in terms of both 1) a low-frequency component expressed in terms of INL through a polynomial model, and 2) a high-frequency component expressed in terms of DNL through a periodical model. On this basis, a unified model (Fig. 11) capable of taking into account both the low-frequency error component, expressed in terms of INL through a polynomial model, and the highfrequency component, expressed in terms of DNL through a multiperiodical or periodical model, has been proposed. The model is derived from the one of Fig. 1, by particularizing
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the block according to the ADC architecture. It is composed of two paths (Fig. 11): 1) in the upper, the lowfrequency INL is estimated through smoothing techniques and the polynomial model of (12), and 2) in the lower, the high-frequency INL local discontinuities are modeled related to the ADC through a periodical unbiased architecture. The results of the two feedback processing blocks are then summed and ideally converted to analog values. The low-frequency component is obtained 1) by applying a experimenmoving-window average algorithm to the tal values (23)
where is the DNL period. In most frequent cases, flash . It implies ADC’s are characterized by a periodicity that (28) Since and (29) it is derived that
is the window length, and 2) by using the where values to identify the polynomial model. The high-frequency component is determined as
(30)
(24) From these values, the corresponding DNL is determined through (2)
(25) is the integral nonlinearity corresponding to the where defined by (20), and is the differential unbiased defined by (23). The nonlinearity corresponding to the is made negligible by a suitable selection of term window length, thus the unified model results (26) In the case of the integrating ADC, the INL is approximated and the DNL-based term by the continuous function of (26) is negligible. On the other hand, for the successive approximation ADC the error has a multiperiodical characteristic and in the model (26) the first term is almost null. The flash ADC is modeled by both the terms by estimating simultaneously. Owing to the periodicity of , (26) is simplified
(27)
that expresses the unified model in the case of a flash having .
IV. CRITERIA
FOR
MODEL IDENTIFICATION
For integrating ADC’s the polynom order of the lowis derived as the maximum frequency component value that, if increased, does not significantly improve the model accuracy. It is evaluated by estimating the model for increasing values of , until differences in correspondvalues are negligible. The determination of ing through the least the polynom coefficients mean squared deviation method requires a high number of operations and experimental INL samples. More efficient methods are available for this aim (spline cubic approximation, Lagrange polynom, Newton approximation, and so on [36]). In particular, the spline cubic has a stable solution when the approximation points are equally spaced in the measuring range. Only a few INL sample sets (e.g., three) equispaced across the full-scale have to be recorded. Each set includes a few of the INL samples related to successive code bins and measured through standard techniques [28]. The basic problem is how many samples are needed for a given accuracy. When the INL function does not have any three experimental points are sufficient inflection point for spline cubic interpolation. In general, the number of . However, points needed is determined as: is not known in advance. One way to find an generally is the comparison of two approximation results optimum and . The first approximation is carried with out by 3 interpolation points: the first in the middle and the other two near the opposite borders of the measuring range. The next approximation is performed using four points , where two of them are close to the range limits. The approximation is assessed by the absolute difference between the estimates of two splines functions (e.g.,
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TABLE II SIMULATION VALUES OF THE UNIFIED MODEL PARAMETERS (R: IDENTIFICATION RANGES, FS: FULLSCALE)
obtained for
) in the points
and (31)
where is a prefixed significance threshold (e.g., a percent of the maximum INL). The further approximation should be and . In this case, performed in the points condition (31) will be checked in the interleaving points and . If a better approximation is needed, the accuracy of each selected experimental point can be improved by repeating the measurement in the same conditions. The repetition factor for in the scale can be each point and the number of points optimized as proposed in [37]. For the successive approximation ADC’s, the experimental DNL samples are derived as indicated in Table I, and the is an average value. The number modeled value used for comof measured DNL values and puting could be lower than the maximum value this depends on the accuracy of the measured values during the testing phase. In practice, values between half and three-quarter of full-scale are the best. As far as flash ADC’s are concerned, the experimental samples have to be taken at a constant code bin (DNL period). The value of depends on the distance architecture (number of phases in the serial-parallel variant) or the internal chip layout. A practical way to estimate is the correlation analysis of measured data in close subranges of the scale (in practice, values in the subrange between half and three-quarter of full-scale are the best). The optimum is and the value showing the highest similarity between represented by the highest correlation coefficient. The different values of DNL are obtained as the average value
(32) The number of data required for averaging belongs to the . interval V. NUMERICAL
AND
EXPERIMENTAL RESULTS
In the following, some sample results of numerical and experimental tests related to the validation and the identification of the unified model are discussed for the three
(a)
(b)
(c) Fig. 12. Example of INL (a) experimental and model simulation results obtained through least squared deviations (b) (MSD: 0.098LSB), and (c) spline cubic (MSD: 0.13LSB) interpolations for ICL7109CPL 12 bit integrating ADC.
aforementioned ADC classes. The maximum confidence in the model validation was attained by identifying the model with the maximum accuracy achievable with all the experimental samples, ignoring the experimental burden. Numerical simulations were performed by implementing models in MATLAB. Experimental tests were carried out by means of a measuring station mainly based on 1) calibrator Fluke 5442A; 2) digital I/O of the board Advantech PCL-812PG; 3) National Instruments IEEE 488.2 interface board; 4) 386 IBM-compatible PC. and values were derived from Experimental the code transition levels obtained through the IEEE 1057 standard static method [28]. Gain and offset errors were estimated
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(a)
(a)
(b) Fig. 13. Example of (a) experimental and (b) model simulation DNL results, (MSD: 0.061LSB) for AD7880BN 12 bit successive approximation ADC (particular on code bin range: 2500–3000).
and corrected through algorithms of the same standard. As far as integrating ADC’s are concerned, in Fig. 12 a validation example of the polynomial branch of the unified model is shown for an actual 12-bit dual slope ADC. The comparison between experimental (a) and simulation results, obtained through the least square interpolation method (b) on 4096 experimental points, highlights the model effectiveness. In Table II, the corresponding values of the model parameters obtained in the identification through the least square interpolating method are reported. Furthermore, Fig. 12, this identification method (b) is compared with a spline cubic interpolation (c). The estimate error [expressed as mean square deviation (MSD)] is 0.098LSB for the least square method and 0.13LSB for spline cubic method, respectively. The small difference in model accuracy does not justify the increase in experimental burden: 4096 INL experimental measures for the least-square case, and only 45 (i.e., 15 sets of three points each) for the spline cubic. As far as successive approximation ADC’s are concerned, in Fig. 13 a validation example of the multiperiodical branch of the unified model is shown for an actual ADC of 12 bit . In order to better highlight the multiperiodicity, for sake of clarity the particulars related to code bin range from 2500 to 3000 of DNL results are shown. Also in this case, the comparison among (a) experimental and (b) simulation results indicates the model effectiveness. was Each value of the 12 DNL independent points obtained by averaging the maximum number of experimental points reported in Table II. As far as flash ADC’s are concerned, in Fig. 14, for an actual 8 bit ADC example, INL (a) experimental and (b) simulation results are compared. In this case, for the identification of the model polynomial path, a spline cubic interpolation on six sets, each of three points, was carried out. The MSD obtained is equal to 0.068LSB. In Fig. 14(c) and (d), the corresponding polynomial low-frequency and periodical components are highlighted, respectively. The high-frequency
(b)
(c)
(d) Fig. 14. Example of (a) experimental and (b) simulation INL results, (MSD: 0.068LSB) for MP7684KN 8 bit flash ADC. Particular of (c) low-frequency and (d) high-frequency components.
periodicity is shown in Fig. 15, where DNL (a) experimental and (b) simulation results are compared. The MSD obtained is equal to 0.014LSB. VI. CONCLUSION Starting from the theoretical model of Fig. 1, the analysis of the error characteristics for the most widespread
ARPAIA et al.: INFLUENCE OF THE ARCHITECTURE ON ADC ON ADC ERROR MODELING
(a)
(b) Fig. 15. Periodical (p = 2) high-frequency component expressed in terms of DNL for the same flash ADC of Fig. 13: (a) experimental and (b) simulation results (MSD: 0.014LSB).
ADC architectures (integrating, successive approximations and to be modeled in flash) allowed the feedback block an unified way (Fig. 11). Integrating ADC errors have a polynomial dominant nature, and correspondingly, the unified model lower path has null output value. Discontinuities in INL typical of successive approximation or flash architecture are more accurately taken into account in terms of DNL through a periodical model. The periodicity is multiple for successive approximation ADC’s and constant for flash ADC’s. However, in the flash case, the simplification involved by the symmetry of the modeled DNL does not allow the INL error spread over the whole measuring range to be characterized. Thus, a further polynomial model for INL description is also necessary. The static model effectiveness in experimental validation suggested further investigation on dynamic ADC behavior [39], [40]. Current work is now devoted to define the applicability limits of the general model. REFERENCES [1] A. Van den Bos and P. Eykhoff, “Model building and parameter estimation as means for intelligent measurement,” Measurement, vol. 6, pp. 25–32, Jan.–Mar. 1988. [2] Proc. 3rd Int. IMEKO Workshop ADC Modeling and Testing, P. Daponte and L. Michaeli, Eds., Napoli, Italy, Sept. 1998. [3] R. J. Patton, J. Chen, and S. B. Nielsen, “Model-based methods for fault diagnosis: Some guidelines,” Trans. Inst. Meas. Contr., vol. 17, no. 2, pp. 73–83, 1995. [4] S. Brigati, V. Liberali, and F. Maloberti, “Precision behavioral modeling of circuit components for data converters,” in Proc. IEE Conf. Advanced A-D D-A Conversion Techniques Applications, Cambridge, U.K., July 6–8, 1994, pp. 110–115. [5] P. Arpaia, F. Cennamo, P. Daponte, and M. D’Apuzzo, “A behavioral model for scan converter-based transient digitizers,” Measurement, vol. 17, no. 2, 1996. [6] D. Asta and F. H. Irons, “Dynamic error compensation of analogto-digital converters,” Lincoln Lab. J., vol. 2, no. 2, pp. 161–182, 1989. [7] E. A. Sloane, “System of converter testing using Walsh transform techniques,” in Proc. Int. Test Conf., Philadelphia, PA, Oct. 27–29, 1981.
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[35] K. Hejn and I. Kale, “Some theorems on Walsh transforms of quantizer differential and integral nonlinearity,” IEEE Trans. Instrum. Meas., vol. 41, pp. 218–225, Apr. 1992. [36] C. Young, “An enhanced method for characterizing successive approximation converters,” IEEE Trans. Instrum. Meas., vol. 39, pp. 335–339, Apr. 1990. [37] E. Kreyszig, Advanced Engineering Mathematics 7th ed. New York: Wiley, 1993. [38] G. Betta and M. Dell’Isola, “An optimized approach to sensor calibration design,” in Proc. IEEE IMTC/93 Conf., Irvine, CA, 1993, pp. 316–322. [39] P. Arpaia, P. Daponte, and L. Michaeli, “Analytical A-priori approach to phase plane modeling of SAR A/D converters,” IEEE Trans. Instrum. Meas., vol. 47, pp. 849–857, Aug. 1998. [40] P. Arpaia, P. Daponte, and L. Michaeli, “A dynamic error model for integrating analog-to-digital converters,” Measurement, vol. 25, no. 4, pp. 255–264, 1999.
Pasquale Arpaia (M’99) was born in Napoli, Italy, in 1961. He teaches electrical measurement at the University of Napoli, Federico II. He has been Consultant on the EU IV Framework Program Standard Measurement and Testing and Evaluator for EU INTAS projects. He is Consultant to the Physikalisch-Technische Bundesanstalt, Berlin, Germany, in the field of ADC metrological characterization. He is responsible for the Promoting Committee of the EUPAS Project of the IMEKO TC-4 A/D and D/A Metrology Workgroup, and is voting member of the IEEE IM TC-10 Waveform Measurement and Analysis. He is Associate Editor of the journal Computer Standards & Interfaces. He has organized some international meetings in the field of electronic measurements and European cooperation. His main research interests include ADC modeling, testing, and standardization, measurement systems on geographic networks, and statisticalbased characterization of measurement systems. In this field, he has published more than 60 scientific papers. Dr. Arpaia is a member of the Electrical and Electronic Measurements Group of the National Council of Research, the Italian Electrical Engineering Association, the IMEKO TC-4 WG on A/D and D/A Metrology, the IEEE Instrumentation and Measurement Society, the IEEE Components, Packaging, and Manufacturing Technology Society, and the European Committee for Electrolytic Corrosion.
Pasquale Daponte (M’91) was born in Minori, Italy, in 1957. Since 1994, he has been teaching digital signal processing and measurement information at the Faculty of Computer Engineering, University of Sannio, Benevento, Italy. He is member of the editorial board of the journal Measurement, as well as of the board of the Italian Society for Computer Simulation. He is coordinator of the IMEKO Working Group on A/D and D/A Metrology. His main research interests are wavelet-based digital signal processing for the harmonic analysis in electrical power systems and for the thin thickness measurements; A/D and D/A metrological characterization; artificial neural network for signal processing; and computer networking for distributed measurement systems. He published more than 130 scientific papers in journals and national and international conference proceedings. He has organized some national or international meetings in the field of electronic measurements and European cooperation. Dr. Daponte is a member of the Scientific Committee of the Electrical and Electronic Measurements Group, the National Council of Research, Italian Electrical Engineering Association, IEEE Instrumentation and Measurement Society, Italian Society for Computer Simulation, and Societas Internationalis pro Diagnostica Ultrasonica in Opthalmologia. In 1987, he received an award from the Italian Society of Oftalmology for studies on the digital signal processing of the ultrasounds in echo-oftalmology.
Linus Michaeli was born in the Slovak Republic in 1945. He received the M.S. degree in electrical engineering from the Technical University of Transport, Zilina, Slovak Republic, in 1968, and the Ph.D. degree in measurement technology Slovak Technical University, Bratislava, in 1979. Since 1994, he has been a Full Professor with the Department of Electronics and Multimedia Telecommunications, Technical University of Kosice, Kosice, Slovak Republic. His main research interests are in ADC modeling and testing and artificial neural network for measurement signal processing. He is a member of the editorial board of the Computer Standards and Interfaces. Dr. Michaeli is the Slovak member of the IMEKO TC4.
