Midterm Fall 2013
ECSE 304-330 Introduction To Electronic Circuits Midterm Examination Wednesday Oct. 30th, 2013, 4:05 - 5:25 PM Examiner: Prof. G. Roberts Associate Examiner: none Name: _____________________________________________ Student No.:_________________________________________ Instructions: • Answer all 3 questions. • Questions have equal weight; Distribution is indicated in brackets. • Answer directly on the question sheet provided. You may use the back of the sheet to continue your answer. • Only the sheets provided will be marked. • This is a Closed-Book Exam; • Write your name and student number on the top of this sheet; if pages are removed from the exam, write your name on the top of each of the question sheets that you want marked. • Only the faculty-approved Standard Calculator is permitted. • You are permitted Translation dictonaries ONLY.
Note To Student: The instructor and / or his representative cannot and will not answer any questions during the final examination period. If you believe a question is in error or requires further clarification, please state your assumptions and work the problem from this point onwards. Clearly, if a question is in error, you will recieve full benefit.
Marking Scheme: Q1
10 points
Q2 10 points
Q3 10 points
TOTAL
Page 1 of 17
Question 1: It is required to design a zener shunt regulator to provide a regulated voltage of about 12 V. The available 12-V, 2.5-W zener is specified to have a 12-V drop at a test current of 20 mA. The zener has a knee current level of 5 mA. At this current level, its rz is 10 ohms. The raw supply available has a nominal value of 25 V but can vary as much as ±25%. The regulator is required to supply a load current of 0 mA to 100 mA. (a) Find VZ0. 2 points
> restart: Given Information: > Vp:=25: Vz:=12.0: Iz:=20e-3: Izk:=5e-3: rz:=10: i[load,max]:= 100e-3: > Vphigh:=Vp*(1+0.25); Vplow:=Vp*(1-0.25); Vdelta:=(VphighVplow)/2; Vphigh := 31.25 Vplow := 18.75 Vdelta := 6.250000000 (1.1.1) The zener diode voltage is found from > Vz0:=Vz-rz*Iz; Vz0 := 11.800 (1.1.2)
(b) Calculate the required value of resistance placed in series with the zener diode. Design for a minimum zener current of 5 mA. 2 points
Page 2 of 17
Under worst-case circuit conditions (low input power supply), the series resistance is selected to be: > Vo:=Vz0+rz*Izk; > Rs := (Vplow-Vo)/(Izk+i[load, max]); Vo := 11.850 Rs := 65.71428571 (1.2.1) The series resistor is equal to 65.7 ohms. (c) Find the line regulation under the design conditions of part (b). What is the change in Vo expressed as a percentage of the nominal voltage corresponding to the ±25% change in supply voltage Vs ? 2 points Circuit problem:
Output Voltage Under Low-Power Supply > eqn1:= (Volow-Vplow)/Rs+(Volow-Vz0)/rz+i[load, max]=0: > Volow:=solve(eqn1,Volow); Volow := 11.85000000 (1.3.1) Output Voltage Under High-Power Supply > eqn2:= (Vohigh-Vphigh)/Rs+(Vohigh-Vz0)/rz+i[load, max]=0: > Vohigh:=solve(eqn2,Vohigh); Vohigh := 13.50094339 (1.3.2) The line regulation becomes : > LineRegulation := (Vohigh-Volow)/(Vphigh-Vplow); (1.3.3)
Page 3 of 17
LineRegulation := 0.1320754712 An alternative approach is to make use of a small-signal model of circuit operation.
(1.3.3)
> # small-signal approximation > v[o,delta]:= rz/(Rs+rz)*v[p,delta]; vo, d := 0.1320754717 vp, d
(1.3.4)
> LineRegulation:= v[o,delta]/v[p,delta]; LineRegulation := 0.1320754717
(1.3.5)
> This particular regulator has a 132 mV/V line regulation factor. What is the change in Vo expressed as a percentage of the nominal voltage corresponding to the ±25% change in supply voltage Vs ? > 'delta_V_o_to_Vo_percent' = (Vohigh-Volow)/Vz *100; delta_V_o_to_Vo_percent = 13.75786158 (1.3.6) The per-centage change in the output voltage becomes 13.7 % of the nominal output voltage. (d) Find the load regulation. By what percentage does Vo change from the no-load to full-load condition relative to the nominal output voltage? 2 points Circuit problem:
Page 4 of 17
Output Voltage Under No load Condition: > eqn3:= (Vonoload-Vp)/Rs+(Vonoload-Vz0)/rz=0: > Vonoload:=solve(eqn3,Vonoload); Vonoload := 13.54339623 (1.4.1) Output Voltage Under Max. Load Condition: > eqn4:= (Vomaxload-Vp)/Rs+(Vomaxload-Vz0)/rz+i[load, max]=0: > Vomaxload:=solve(eqn4,Vomaxload); Vomaxload := 12.67547170 (1.4.2) The load regulation becomes : > LoadRegulation := -1* (Vonoload-Vomaxload)/i[load, max]; LoadRegulation := K8.679245300 (1.4.3) This particular regulator has a - 8.7 mV/mA load regulation factor. By what percentage does Vo change from the no-load to full-load condition relative to the nominal output voltage? > 'delta_Vo_to_Vo_percent' = -100*(Vonoload-Vomaxload)/Vz; delta_Vo_to_Vo_percent = K7.232704417 (1.4.4) The per-centage change in the output voltage becomes -7.2 % of the nominal output voltage. (e) What is the maximum current that the zener in your design is required to conduct? What is the zener power dissipation under this condition? 2 points Circuit problem:
Page 5 of 17
The maximum zener diode current condition occurs under no-load conditions when the input power supply is at its maximum level. > i[zener,max]:=(Vphigh-Vz0)/(rz+Rs); izener, max := 0.2568867925 (1.5.1) The maximum zener current is 256 mA. What is the zener power dissipation under this condition? What is the expected outcome of thi zener diode? > P[zener]:=i[zener,max]*Vonoload; Pzener := 3.479119617 (1.5.2) The power dissipated by the zener under this condition is 3.48 W. As this level exceeds the 2.5 W level of the diode, it is expected to burn out prematurely.
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Question 2: The transient behavior of the op amp circuit shown below is to be verified using Spice subject to a 100 mV differential signal with a 1-V 60 Hz common-mode level. Using the Spice summary sheet found at the end of this exam, answer the following questions.
(a) Identify the nodes on the above schematic that will be used by Spice to perform analysis. Include all required voltage sources. [3 points] Solution Circuit that is to be simulated with transistent source added:
(b) Describe the model of the op amp you would use to simulate the frequency dependent behavior of the op amp having a 3-dB bandwidth of 20 rad/s and a DC gain of 15,000 V/V. [3 points]
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Solution
> restart: For a DC gain of 15,000 V/V, we set > Ao:=15e3; Ao := 15000.
(2.2.1.1)
Establishing the op amp parameters for a 3 db bandwidth of 100 rad/s, we solve for R, assuming C is 1 uF as follows: > wb:=20;
wb := 20
(2.2.1.2)
> C:=1e-6;
C := 0.000001 > R:=solve(wb=1/(R*C), R); R := 50000.
(c) Write a Spice netlist that describes your circuit and perform a transient analysis of the instrumentation amplifier circuit for 5 cylces of the common-mode signals. [4 points] PSpice Netlist Instrumentation Amplifier * op-amp subcircuit .subckt gbw_opamp 1 2 3 * connections: ||| * output | | * +ve input |
(2.2.1.3) (2.2.1.4)
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* -ve input E1 4 0 2 3 15e3 R 4 5 50e3 C 5 0 1e-6 Eoutput 1 0 5 0 1 .ends ideal_opamp ** Main Circuit ** * signal sources Vcm 1 0 SIN (0 1V 60Hz) Vdc1 1 2 DC 50mV Vdc2 3 1 DC 50mV * instrumentation amplifier Xop_A1 6 2 5 gbw_opamp Xop_A2 7 3 4 gbw_opamp Xop_A3 10 9 8 gbw_opamp R1 5 4 50k R2 4 6 10k R3 5 7 10k R4 6 8 10k R5 7 9 10k R6 9 0 10k R7 8 10 10k ** Analysis Requests ** .TRAN 0.1ms 80ms 0 0.1ms ** Output Requests ** .PRINT TRAN V(1,2) V(3) V(10) .probe .end
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Question 3: (a) Design a difference amplifier to realize a differential gain of 50 V/V and a differential input resistance of 50 kΩ. Assume the op amp to be ideal. Specify all resistor values. [2 points] Solution
Given Data in Problem: > restart: > G_desired:=50: > R_desired:=25e3: First step of the design process is to describe the input-output transfer function, G: KCL at -ve input terminal of op amp: > eqn1:=(v[I,1]-v[neg])/R[1]=(v[neg]-v[o])/R[2]; vI, 1 K vneg vneg K vo eqn1 := = R1 R2 KCL at +ve input terminal of op amp: > eqn2:=(v[I,2]-v[pos])/R[3]=(v[pos]-0)/R[4]; vI, 2 K vpos vpos eqn2 := = R3 R4
(3.1.1.1)
(3.1.1.2)
Solving for the positive input, we get > v[pos]:=solve(eqn2, v[pos]); (3.1.1.3)
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vpos :=
vI, 2 R4 R3 C R4
Now, the op amp input-output behavior can be described as > v[neg]:=v[pos]; vI, 2 R4 vneg := R3 C R4 Solving for the output, we get > v[o]:=solve(eqn1, v[o]); R1 R4 vI, 2 K R2 R3 vI, 1 K R2 R4 vI, 1 C R2 R4 vI, 2 vo := R3 C R4 R1 Input refering the two inputs vI,1 and vI,2 in DM and CM terms, we write: > v[DM]=v[I,2]-v[I,1]; vDM = vI, 2 K vI, 1
(3.1.1.3)
(3.1.1.4)
(3.1.1.5)
(3.1.1.6)
> v[CM]=(v[I,2]+v[I,1])/2; 1 1 vCM = vI, 2 C v (3.1.1.7) 2 2 I, 1 > sol:=solve({v[DM]=v[I,2]-v[I,1], v[CM]=(v[I,2]+v[I,1])/2}, [v[I,1], v[I,2]]); 1 1 sol := vI, 1 = K vDM C vCM, vI, 2 = vCM C v (3.1.1.8) 2 2 DM > assign(sol); > 'v[o]'=collect(v[o], [v[CM], v[DM]], recursive); 1 1 R1 R4 C R R C R2 R4 vDM R1 R4 K R2 R3 vCM 2 2 2 3 vo = C (3.1.1.9) R3 C R4 R1 R3 C R4 R1 To force the CM component of the output to zero, > R[1]=solve( coeff(v[o], v[CM])=0, R[1]); R2 R3 R1 = R4
(3.1.1.10)
> 'v[o]'=collect( subs(R[1]=solve( coeff(v[o], v[CM])=0, R[1] ), v[o]), [v[CM], v[DM]], recursive); R2 R3 C R2 R4 R4 vDM vo = (3.1.1.11) R3 C R4 R2 R3 Going back several steps, we'll assign the following degrees fo freedom: > R[3]:=R[1]; R[4]:=R[2]; R3 := R1 R4 := R2
(3.1.1.12)
> 'v[o]'=simplify(collect(v[o], [v[CM], v[DM]], recursive)); vDM R2 vo = (3.1.1.13) R1
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Establish the differential gain and input resistance > R[IN]:=R[1]+R[3];
RIN := 2 R1
> G:=R[2]/R[1]; G :=
R2 R1
(3.1.1.14)
(3.1.1.15)
In order to obtain an input resistance of 50 kohms, Let R1 =25 kΩ, then we solve for R2 according to > R[1]:=R_desired; R1 := 25000. (3.1.1.16) > R[2]:=solve(G=G_desired, R[2]); R2 := 1.250000 106
(3.1.1.17)
Therefore we select R1 = 25 kΩ and R2 = 1.25 MΩ. (b) Design a Miller integrator circuit assuming the op amp is ideal with a time constant of one millisecond and an input resistance of 50 kΩ. Assuming a step input of -1 V at time 0 s, how long does it take for the output to reach +5 V? [2 points] Solution
Given Data in Problem: > restart: > tc_desired:=1e-3:
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> R[IN]:=50e3: > Vintial:=-1: > Vfinal:=5: As the value of R1 is determined by the input resistance of amplifier, we write > R[1]:=R[IN]; R1 := 50000. According to KVL at op amp input: > eqn1:=(v[I]-0)/R=(0-v[o])/(1/(s*C)); vI eqn1 := = Kvo s C R > v[o,s]:=solve(eqn1, v[o]); vI vo, s := K RsC
(3.2.1.1)
(3.2.1.2)
(3.2.1.3)
Imposing the given data: > R:=R[IN]; > C:=tc_desired/R;
R := 50000.
(3.2.1.4)
C := 2.000000000 10-8
(3.2.1.5)
Therefore the integrator cicuit will be realized using a 100 kΩ input resistor and a 10 nF feedback capacitor. As the input specification data is expressed in terms of the time domain response of the intergrator, we'll have to convert the transfer function into a step response requirement: > with(inttrans): Consider the first case: V=-1 V: > v[I]:=Vintial/s: > 'v[o,s]'=v[o,s]; vo, s =
1000.000000
s2 > v[o,t]:= invlaplace(v[o,s], s, t); vo, t := 1000. t >
t=solve(v[o,t]=Vfinal, t); t = 0.005000000000
(3.2.1.6) (3.2.1.7)
(3.2.1.8)
Therefore we the output reaches the 5 V output level at 5.0 ms for a -1 V step input. (c) What is the unity-gain requirements of an op amp that is used in an inverting amplifier with a DC gain of magnitude greater than or equal to 20 dB and having a 3-dB bandwidth of at least 10,000 rad/s.
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[3 points] Solution
> restart: #clear memory > A_dB_desired:=20: > BW_desired:=10e3: In closed-loop, an amplifier follows the familar gain-bandwidth trade off curve:
> A_desired:=10^(A_dB_desired/20);
(3.3.1.1)
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> omega[t] := A_desired * BW_desired; A_desired := 10 wt := 1.00 105
(3.3.1.1)
Therefore the op amp needs a unity-gain bandwidth slightly larger than 100 krad/s. (d) It is required to design a noninverting amplifier with a DC gain of 10 V/V. When a step input of 100 mV is applied at the input, it is required that the output be within 1% of its final value of 1 V in at most 100 ns. What must be the unity gain frequency of the op amp? [3 points]
Solution
> restart:
#clear memory
Writing KCL at the negative terminal of the op amp, we get > eqn1:=(0-v[neg])/R[1]=(v[neg]-v[o])/R[2]; vneg vneg K vo eqn1 := K = R1 R2 > v[neg]=solve(eqn1, v[neg] ); vo R1 vneg = R1 C R2 Imposing the op amp condition, we set > v[pos]:=v[I]; vpos := vI
(3.4.1.1)
(3.4.1.2)
(3.4.1.3)
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> A[op]:=omega[t_]/s; Aop :=
wt_
s > eqn2:=v[pos]-v[neg]=v[o]/A[op]; vo s eqn2 := vI K vneg = wt_ > v[neg]=solve(eqn2, v[neg]); vo s K vI wt_ vneg = K wt_ Combining the two results, and solving for vo we write > eqn3:=solve(eqn1, v[neg] ) = solve(eqn2, v[neg]); vo R1 vo s K vI wt_ eqn3 := =K R1 C R2 wt_ > v[o,s]:=solve(eqn3, v[o]); vI wt_ R1 C R2 vo, s := s R1 C s R2 C R1 wt_
(3.4.1.4)
(3.4.1.5)
(3.4.1.6)
(3.4.1.7)
(3.4.1.8)
System behavior can be described by a first-order transfer fucntion with DC gain an pole: > A[DC]:=eval(v[o,s]/v[I], s=0); R1 C R2 ADC := (3.4.1.9) R1 > p[1]:=solve(denom(v[o,s]/v[I])=0, s); R1 wt_ p1 := K R1 C R2
(3.4.1.10)
Setting the DC gain to 10, we let the resistors take ont he following values: > R[1]:=10e3; R1 := 10000.
(3.4.1.11)
> R[2]:=solve(A[DC]=10, R[2]); R2 := 90000.
(3.4.1.12)
The step response of a single pole system can be found from > with(inttrans): > H:=v[o,s]/v[I]*V[step]/s; 1.00000 105 wt_ Vstep H := 1.00000 105 s C 10000. wt_ s
(3.4.1.13)
> v[o,t]:= invlaplace(H, s, t);
K0.1000000000 w t t_
vo, t := 10. Vstep 1. K 1. e
(3.4.1.14)
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Now, consider the input data > V[step]:=100e-3: > V[final]:=limit(s*H, s=0); Vfinal := 1.
(3.4.1.15)
Next, we want to set the determine the value of ft such that the error at 100 ns after the step signal is applied is less than 1% or 1-0.01=0.99 V. > eqn:=100e-9=solve(v[o,t]=1-0.01, t); 46.05170186 eqn := 1.00 10-7 = (3.4.1.16) wt_ > omega[t_]:=solve(eqn, omega[t_]); wt_ := 4.605170186 108
(3.4.1.17)
> f[t_]=solve(omega[t_]=2*Pi*f[t_], f[t_]); ft_ = 7.329355989 107
(3.4.1.18)
Therefore we select R1 = 10 kΩ, R2 = 90 kΩ, and ft=73.3 MHz.
Note To Student: The instructor and / or his representative cannot and will not answer any questions during the final examination period. If you believe a question is in error or requires further clarification, please state your assumptions and work the problem from this point onwards. Clearly, if a question is in error, you will recieve full benefit.
Marking Scheme: Q1
10 points
Q2 10 points
Q3 10 points
TOTAL
Page 1 of 17
Question 1: It is required to design a zener shunt regulator to provide a regulated voltage of about 12 V. The available 12-V, 2.5-W zener is specified to have a 12-V drop at a test current of 20 mA. The zener has a knee current level of 5 mA. At this current level, its rz is 10 ohms. The raw supply available has a nominal value of 25 V but can vary as much as ±25%. The regulator is required to supply a load current of 0 mA to 100 mA. (a) Find VZ0. 2 points
> restart: Given Information: > Vp:=25: Vz:=12.0: Iz:=20e-3: Izk:=5e-3: rz:=10: i[load,max]:= 100e-3: > Vphigh:=Vp*(1+0.25); Vplow:=Vp*(1-0.25); Vdelta:=(VphighVplow)/2; Vphigh := 31.25 Vplow := 18.75 Vdelta := 6.250000000 (1.1.1) The zener diode voltage is found from > Vz0:=Vz-rz*Iz; Vz0 := 11.800 (1.1.2)
(b) Calculate the required value of resistance placed in series with the zener diode. Design for a minimum zener current of 5 mA. 2 points
Page 2 of 17
Under worst-case circuit conditions (low input power supply), the series resistance is selected to be: > Vo:=Vz0+rz*Izk; > Rs := (Vplow-Vo)/(Izk+i[load, max]); Vo := 11.850 Rs := 65.71428571 (1.2.1) The series resistor is equal to 65.7 ohms. (c) Find the line regulation under the design conditions of part (b). What is the change in Vo expressed as a percentage of the nominal voltage corresponding to the ±25% change in supply voltage Vs ? 2 points Circuit problem:
Output Voltage Under Low-Power Supply > eqn1:= (Volow-Vplow)/Rs+(Volow-Vz0)/rz+i[load, max]=0: > Volow:=solve(eqn1,Volow); Volow := 11.85000000 (1.3.1) Output Voltage Under High-Power Supply > eqn2:= (Vohigh-Vphigh)/Rs+(Vohigh-Vz0)/rz+i[load, max]=0: > Vohigh:=solve(eqn2,Vohigh); Vohigh := 13.50094339 (1.3.2) The line regulation becomes : > LineRegulation := (Vohigh-Volow)/(Vphigh-Vplow); (1.3.3)
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LineRegulation := 0.1320754712 An alternative approach is to make use of a small-signal model of circuit operation.
(1.3.3)
> # small-signal approximation > v[o,delta]:= rz/(Rs+rz)*v[p,delta]; vo, d := 0.1320754717 vp, d
(1.3.4)
> LineRegulation:= v[o,delta]/v[p,delta]; LineRegulation := 0.1320754717
(1.3.5)
> This particular regulator has a 132 mV/V line regulation factor. What is the change in Vo expressed as a percentage of the nominal voltage corresponding to the ±25% change in supply voltage Vs ? > 'delta_V_o_to_Vo_percent' = (Vohigh-Volow)/Vz *100; delta_V_o_to_Vo_percent = 13.75786158 (1.3.6) The per-centage change in the output voltage becomes 13.7 % of the nominal output voltage. (d) Find the load regulation. By what percentage does Vo change from the no-load to full-load condition relative to the nominal output voltage? 2 points Circuit problem:
Page 4 of 17
Output Voltage Under No load Condition: > eqn3:= (Vonoload-Vp)/Rs+(Vonoload-Vz0)/rz=0: > Vonoload:=solve(eqn3,Vonoload); Vonoload := 13.54339623 (1.4.1) Output Voltage Under Max. Load Condition: > eqn4:= (Vomaxload-Vp)/Rs+(Vomaxload-Vz0)/rz+i[load, max]=0: > Vomaxload:=solve(eqn4,Vomaxload); Vomaxload := 12.67547170 (1.4.2) The load regulation becomes : > LoadRegulation := -1* (Vonoload-Vomaxload)/i[load, max]; LoadRegulation := K8.679245300 (1.4.3) This particular regulator has a - 8.7 mV/mA load regulation factor. By what percentage does Vo change from the no-load to full-load condition relative to the nominal output voltage? > 'delta_Vo_to_Vo_percent' = -100*(Vonoload-Vomaxload)/Vz; delta_Vo_to_Vo_percent = K7.232704417 (1.4.4) The per-centage change in the output voltage becomes -7.2 % of the nominal output voltage. (e) What is the maximum current that the zener in your design is required to conduct? What is the zener power dissipation under this condition? 2 points Circuit problem:
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The maximum zener diode current condition occurs under no-load conditions when the input power supply is at its maximum level. > i[zener,max]:=(Vphigh-Vz0)/(rz+Rs); izener, max := 0.2568867925 (1.5.1) The maximum zener current is 256 mA. What is the zener power dissipation under this condition? What is the expected outcome of thi zener diode? > P[zener]:=i[zener,max]*Vonoload; Pzener := 3.479119617 (1.5.2) The power dissipated by the zener under this condition is 3.48 W. As this level exceeds the 2.5 W level of the diode, it is expected to burn out prematurely.
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Question 2: The transient behavior of the op amp circuit shown below is to be verified using Spice subject to a 100 mV differential signal with a 1-V 60 Hz common-mode level. Using the Spice summary sheet found at the end of this exam, answer the following questions.
(a) Identify the nodes on the above schematic that will be used by Spice to perform analysis. Include all required voltage sources. [3 points] Solution Circuit that is to be simulated with transistent source added:
(b) Describe the model of the op amp you would use to simulate the frequency dependent behavior of the op amp having a 3-dB bandwidth of 20 rad/s and a DC gain of 15,000 V/V. [3 points]
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Solution
> restart: For a DC gain of 15,000 V/V, we set > Ao:=15e3; Ao := 15000.
(2.2.1.1)
Establishing the op amp parameters for a 3 db bandwidth of 100 rad/s, we solve for R, assuming C is 1 uF as follows: > wb:=20;
wb := 20
(2.2.1.2)
> C:=1e-6;
C := 0.000001 > R:=solve(wb=1/(R*C), R); R := 50000.
(c) Write a Spice netlist that describes your circuit and perform a transient analysis of the instrumentation amplifier circuit for 5 cylces of the common-mode signals. [4 points] PSpice Netlist Instrumentation Amplifier * op-amp subcircuit .subckt gbw_opamp 1 2 3 * connections: ||| * output | | * +ve input |
(2.2.1.3) (2.2.1.4)
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* -ve input E1 4 0 2 3 15e3 R 4 5 50e3 C 5 0 1e-6 Eoutput 1 0 5 0 1 .ends ideal_opamp ** Main Circuit ** * signal sources Vcm 1 0 SIN (0 1V 60Hz) Vdc1 1 2 DC 50mV Vdc2 3 1 DC 50mV * instrumentation amplifier Xop_A1 6 2 5 gbw_opamp Xop_A2 7 3 4 gbw_opamp Xop_A3 10 9 8 gbw_opamp R1 5 4 50k R2 4 6 10k R3 5 7 10k R4 6 8 10k R5 7 9 10k R6 9 0 10k R7 8 10 10k ** Analysis Requests ** .TRAN 0.1ms 80ms 0 0.1ms ** Output Requests ** .PRINT TRAN V(1,2) V(3) V(10) .probe .end
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Question 3: (a) Design a difference amplifier to realize a differential gain of 50 V/V and a differential input resistance of 50 kΩ. Assume the op amp to be ideal. Specify all resistor values. [2 points] Solution
Given Data in Problem: > restart: > G_desired:=50: > R_desired:=25e3: First step of the design process is to describe the input-output transfer function, G: KCL at -ve input terminal of op amp: > eqn1:=(v[I,1]-v[neg])/R[1]=(v[neg]-v[o])/R[2]; vI, 1 K vneg vneg K vo eqn1 := = R1 R2 KCL at +ve input terminal of op amp: > eqn2:=(v[I,2]-v[pos])/R[3]=(v[pos]-0)/R[4]; vI, 2 K vpos vpos eqn2 := = R3 R4
(3.1.1.1)
(3.1.1.2)
Solving for the positive input, we get > v[pos]:=solve(eqn2, v[pos]); (3.1.1.3)
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vpos :=
vI, 2 R4 R3 C R4
Now, the op amp input-output behavior can be described as > v[neg]:=v[pos]; vI, 2 R4 vneg := R3 C R4 Solving for the output, we get > v[o]:=solve(eqn1, v[o]); R1 R4 vI, 2 K R2 R3 vI, 1 K R2 R4 vI, 1 C R2 R4 vI, 2 vo := R3 C R4 R1 Input refering the two inputs vI,1 and vI,2 in DM and CM terms, we write: > v[DM]=v[I,2]-v[I,1]; vDM = vI, 2 K vI, 1
(3.1.1.3)
(3.1.1.4)
(3.1.1.5)
(3.1.1.6)
> v[CM]=(v[I,2]+v[I,1])/2; 1 1 vCM = vI, 2 C v (3.1.1.7) 2 2 I, 1 > sol:=solve({v[DM]=v[I,2]-v[I,1], v[CM]=(v[I,2]+v[I,1])/2}, [v[I,1], v[I,2]]); 1 1 sol := vI, 1 = K vDM C vCM, vI, 2 = vCM C v (3.1.1.8) 2 2 DM > assign(sol); > 'v[o]'=collect(v[o], [v[CM], v[DM]], recursive); 1 1 R1 R4 C R R C R2 R4 vDM R1 R4 K R2 R3 vCM 2 2 2 3 vo = C (3.1.1.9) R3 C R4 R1 R3 C R4 R1 To force the CM component of the output to zero, > R[1]=solve( coeff(v[o], v[CM])=0, R[1]); R2 R3 R1 = R4
(3.1.1.10)
> 'v[o]'=collect( subs(R[1]=solve( coeff(v[o], v[CM])=0, R[1] ), v[o]), [v[CM], v[DM]], recursive); R2 R3 C R2 R4 R4 vDM vo = (3.1.1.11) R3 C R4 R2 R3 Going back several steps, we'll assign the following degrees fo freedom: > R[3]:=R[1]; R[4]:=R[2]; R3 := R1 R4 := R2
(3.1.1.12)
> 'v[o]'=simplify(collect(v[o], [v[CM], v[DM]], recursive)); vDM R2 vo = (3.1.1.13) R1
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Establish the differential gain and input resistance > R[IN]:=R[1]+R[3];
RIN := 2 R1
> G:=R[2]/R[1]; G :=
R2 R1
(3.1.1.14)
(3.1.1.15)
In order to obtain an input resistance of 50 kohms, Let R1 =25 kΩ, then we solve for R2 according to > R[1]:=R_desired; R1 := 25000. (3.1.1.16) > R[2]:=solve(G=G_desired, R[2]); R2 := 1.250000 106
(3.1.1.17)
Therefore we select R1 = 25 kΩ and R2 = 1.25 MΩ. (b) Design a Miller integrator circuit assuming the op amp is ideal with a time constant of one millisecond and an input resistance of 50 kΩ. Assuming a step input of -1 V at time 0 s, how long does it take for the output to reach +5 V? [2 points] Solution
Given Data in Problem: > restart: > tc_desired:=1e-3:
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> R[IN]:=50e3: > Vintial:=-1: > Vfinal:=5: As the value of R1 is determined by the input resistance of amplifier, we write > R[1]:=R[IN]; R1 := 50000. According to KVL at op amp input: > eqn1:=(v[I]-0)/R=(0-v[o])/(1/(s*C)); vI eqn1 := = Kvo s C R > v[o,s]:=solve(eqn1, v[o]); vI vo, s := K RsC
(3.2.1.1)
(3.2.1.2)
(3.2.1.3)
Imposing the given data: > R:=R[IN]; > C:=tc_desired/R;
R := 50000.
(3.2.1.4)
C := 2.000000000 10-8
(3.2.1.5)
Therefore the integrator cicuit will be realized using a 100 kΩ input resistor and a 10 nF feedback capacitor. As the input specification data is expressed in terms of the time domain response of the intergrator, we'll have to convert the transfer function into a step response requirement: > with(inttrans): Consider the first case: V=-1 V: > v[I]:=Vintial/s: > 'v[o,s]'=v[o,s]; vo, s =
1000.000000
s2 > v[o,t]:= invlaplace(v[o,s], s, t); vo, t := 1000. t >
t=solve(v[o,t]=Vfinal, t); t = 0.005000000000
(3.2.1.6) (3.2.1.7)
(3.2.1.8)
Therefore we the output reaches the 5 V output level at 5.0 ms for a -1 V step input. (c) What is the unity-gain requirements of an op amp that is used in an inverting amplifier with a DC gain of magnitude greater than or equal to 20 dB and having a 3-dB bandwidth of at least 10,000 rad/s.
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[3 points] Solution
> restart: #clear memory > A_dB_desired:=20: > BW_desired:=10e3: In closed-loop, an amplifier follows the familar gain-bandwidth trade off curve:
> A_desired:=10^(A_dB_desired/20);
(3.3.1.1)
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> omega[t] := A_desired * BW_desired; A_desired := 10 wt := 1.00 105
(3.3.1.1)
Therefore the op amp needs a unity-gain bandwidth slightly larger than 100 krad/s. (d) It is required to design a noninverting amplifier with a DC gain of 10 V/V. When a step input of 100 mV is applied at the input, it is required that the output be within 1% of its final value of 1 V in at most 100 ns. What must be the unity gain frequency of the op amp? [3 points]
Solution
> restart:
#clear memory
Writing KCL at the negative terminal of the op amp, we get > eqn1:=(0-v[neg])/R[1]=(v[neg]-v[o])/R[2]; vneg vneg K vo eqn1 := K = R1 R2 > v[neg]=solve(eqn1, v[neg] ); vo R1 vneg = R1 C R2 Imposing the op amp condition, we set > v[pos]:=v[I]; vpos := vI
(3.4.1.1)
(3.4.1.2)
(3.4.1.3)
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> A[op]:=omega[t_]/s; Aop :=
wt_
s > eqn2:=v[pos]-v[neg]=v[o]/A[op]; vo s eqn2 := vI K vneg = wt_ > v[neg]=solve(eqn2, v[neg]); vo s K vI wt_ vneg = K wt_ Combining the two results, and solving for vo we write > eqn3:=solve(eqn1, v[neg] ) = solve(eqn2, v[neg]); vo R1 vo s K vI wt_ eqn3 := =K R1 C R2 wt_ > v[o,s]:=solve(eqn3, v[o]); vI wt_ R1 C R2 vo, s := s R1 C s R2 C R1 wt_
(3.4.1.4)
(3.4.1.5)
(3.4.1.6)
(3.4.1.7)
(3.4.1.8)
System behavior can be described by a first-order transfer fucntion with DC gain an pole: > A[DC]:=eval(v[o,s]/v[I], s=0); R1 C R2 ADC := (3.4.1.9) R1 > p[1]:=solve(denom(v[o,s]/v[I])=0, s); R1 wt_ p1 := K R1 C R2
(3.4.1.10)
Setting the DC gain to 10, we let the resistors take ont he following values: > R[1]:=10e3; R1 := 10000.
(3.4.1.11)
> R[2]:=solve(A[DC]=10, R[2]); R2 := 90000.
(3.4.1.12)
The step response of a single pole system can be found from > with(inttrans): > H:=v[o,s]/v[I]*V[step]/s; 1.00000 105 wt_ Vstep H := 1.00000 105 s C 10000. wt_ s
(3.4.1.13)
> v[o,t]:= invlaplace(H, s, t);
K0.1000000000 w t t_
vo, t := 10. Vstep 1. K 1. e
(3.4.1.14)
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Now, consider the input data > V[step]:=100e-3: > V[final]:=limit(s*H, s=0); Vfinal := 1.
(3.4.1.15)
Next, we want to set the determine the value of ft such that the error at 100 ns after the step signal is applied is less than 1% or 1-0.01=0.99 V. > eqn:=100e-9=solve(v[o,t]=1-0.01, t); 46.05170186 eqn := 1.00 10-7 = (3.4.1.16) wt_ > omega[t_]:=solve(eqn, omega[t_]); wt_ := 4.605170186 108
(3.4.1.17)
> f[t_]=solve(omega[t_]=2*Pi*f[t_], f[t_]); ft_ = 7.329355989 107
(3.4.1.18)
Therefore we select R1 = 10 kΩ, R2 = 90 kΩ, and ft=73.3 MHz.
