Packaging of integrated circuits and vertical integration
US006693361B1
(12)
United States Patent
(10) Patent N0.: (45) Date of Patent:
Siniaguine et al.
(54)
US 6,693,361 B1 Feb. 17, 2004
PACKAGING OF INTEGRATED CIRCUITS AND VERTICAL INTEGRATION
5,831,832 A 5,834,830 A
5,858,815 A
1/1999 Heo et al. .
438/112
(75) Inventors: Oleg Siniaguine, San Jose, CA (US);
5,863,812 A
1/1999 Manteghi ..
438/108
Sergey Savastiouk, San Jose, CA (US)
5,863,816
(73) Assignee: Tru-Si Technologies, Inc., Sunnyvale, CA (US)
(*)
Notice:
Subject to any disclaimer, the term of this patent is extended or adjusted under 35
U.S.C. 154(b) by 0 days.
11/1998 Gillette et al. ............ .. 361/760 11/1998 Cho ......................... .. 257/667
A
1/1999
Cho
5,872,051 A 5,879,964 A
2/1999 3/1999
Fallon et al. ............. .. 438/616 Paik et al. ................ .. 438/113
... .. ... ... .
. . . ..
438/123
5,886,398 A 5,886,414 A *
3/1999 Low et al. 3/1999 Galloway
257/667 257/784
5,889,332 A
3/1999
Lawson et al.
5,892,273 A 5,892,290 A 5,918,113 A
4/1999 4/1999 6/1999
IWasaki et al. ........... .. 257/690 Chakravorty et al. ..... .. 257/786 Higashi et al. ........... .. 438/119
.....
. . . ..
257/778
(List continued on neXt page.)
(21) Appl. No.: 09/716,092 Nov. 16, 2000 (22) Filed:
FOREIGN PATENT DOCUMENTS JP W0
Related US. Application Data
(62)
Division of application No. 09/456,225, ?led on Dec. 6,
(51)
Int. Cl.7 ....................... .. H01L 23/48; H01L 23/52;
(52) (58)
US. Cl. ...................... .. 257/777; 257/774; 257/778 Field of Search ............................... .. 257/774, 777,
403283641 A * 12/1991 WO 98/19337 5/1998
OTHER PUBLICATIONS
1999.
H01L 29/40
M. Amagai, et al., “Development of Chip Scale Packages (CSP) for Center Pad Devices,” 1997 Electronic Compo nents and Technology Conference, 1997 IEEE, pp. 343—352. (List continued on neXt page.)
257/778 Primary Examiner—Eddie Lee References Cited
(56)
Assistant Examiner—Joseph Nguyen (74) Attorney, Agent, or Firm—Michael
U.S. PATENT DOCUMENTS 4,612,083 A 4,704,785 A
4,890,784 A 4,933,743 A
5,064,771 A
9/1986 Yasumoto et al. ........ .. 156/633 * 11/1987
*
Curran ........... ..
1/1990 Bampton .... .. 6/1990 Thomas et al.
11/1991 Solomon
437/110
228/194 .. 357/71
437/3
5,225,771 A
7/1993 Leedy ............ ..
324/158
5,258,330 A
11/1993 Khandros et al. .
437/209
5,322,816 A 5,627,106 A
5,654,127 A
Shenker;
MacPherson KWok Chen & Heid LLP
6/1994 Pinter ............. .. 438/667 5/1997 Hsu ......................... .. 438/459
8/1997 Leedy ...................... .. 430/315
5,684,330 A
11/1997 Lee ................ ..
257/692
5,742,100 A
4/1998 Schroeder et al.
257/778
5,759,873 A 5,786,271 A
6/1998 Kata et al. ...... .. 438/118 7/1998 Ohida et al. .............. .. 438/615
5,798,567 A 5,817,541 A
10/1998 Averkiou et al. ......... .. 438/107
(57)
ABSTRACT
A ?rst level packaging Wafer is made of a semiconductor or
insulating material. The bumps on the Wafer are made using vertical integration technology, Without solder or electro plating. More particularly, vias are etched part Way into a ?rst surface of the substrate. Metal is deposited into the vias. Then the substrate is blanket-etched from the back side until the metal is exposed and protrudes from the vias to form
suitable bumps. Dicing methods and vertical integration methods are also provided. Solder or electroplating are used in some embodiments.
8/1998 Kelly et al. ............... .. 257/723
29 Claims, 13 Drawing Sheets
US 6,693,361 B1 Page 2
US. PATENT DOCUMENTS 5,998,292 A 6,083,773 A
12/1999 Black et al. .............. .. 438/618 7/2000 Lake .......... .. 438/108
6,087,719 A
*
7/2000
Tsunashima .... ..
257/686
6,157,082 A
* 12/2000 Merchant et al. .
257/758
6,184,060 B1 *
2/2001 Siniaguine
6,194,781 B1 * 6,229,209 B1 *
2/2001 5/2001
438/106
Ikegami .................... .. 257/737 Nakamura et al. ........ .. 257/737
OTHER PUBLICATIONS
P. Elenius, “Flex on Cap—Solder Paste Bumping”, 1997
Electronic Components and Technology Conference, 1997 IEEE, pp. 248—252.
R. Fillion, et al., “Chip Scale Packaging Using Chip—on— Flex Technology”, 1997 Electronic Components and Tech nology Conference, 1997 IEEE, pp. 638—641. J. Kloeser et al., “Fine Pitch Stencil Printing of Sn/Pb and Lead Free Solders for Flip Chip Technology”, 1997 Elec
tronic Components and Technology Conference, 1997 IEEE, pp. 254—263.
Sara M. Chen, “Electroplated Hermetic Fiber”, 1998 Elec tronic Conference, 1998 IEEE, p. 418. L. Li, et al., “Stencil Printing Process Development for LoW
Cost Flip Chip Interconnect”, 1998 Electronic Components and Technology Conference, 1998 IEEE, pp. 421—426. G. Rinne, “Solder Bumping Methods for Flip Chip Pack aging”, 1997 Electronic Components and Technology Con ference, 1997 IEEE, pp. 241—247.
K. ShimokaWa, et al, “Micro—ball Bump for Flip Intercon nections”, 1998 Electronic Components and Technology Conference, 1998 IEEE, pp. 1472—1476. Y.C. Teo, “Low Cost Chip—Scale Package”, 1997 Electronic Components and Technology Conference, 1997 IEEE, pp. 358—363.
Y. Yamaji, et al., “Development of Highly Reliable CSP”, 1997 Electronic Components and Technology Conference,
L. Levine, “Ball Bumping and Coining Operations for Tab and Flip Chip”, 1997 Electronic Components and Technol
1997 IEEE, pp. 1022—1027.
ogy Conference, 1997 IEEE, pp. 265—273.
* cited by examiner
U.S. Patent
Feb. 17, 2004
Sheet 1 0f 13
US 6,693,361 B1
QNN
mo? CNN mom. . N
.05 mom. mom?
U.S. Patent
Feb. 17, 2004
Sheet 3 0f 13
US 6,693,361 B1
mom p _
.uE w
U.S. Patent
Feb. 17, 2004
Sheet 4 0f 13
3
F3
l F
US 6,693,361 B1
L
o
\f9
r?
F“
\
g
430
420
510430420
510420
FIG. 5
U.S. Patent
Feb. 17, 2004
Sheet 5 0f 13
-
US 6,693,361 B1
ll).
4%0
502 €,
l ~430
\ l
FIG. 6
@506
U.S. Patent
Feb. 17, 2004
Sheet 6 6f 13
US 6,693,361 B1
.05 w
U.S. Patent
Feb. 17, 2004
o:
Sheet 7 0f 13
US 6,693,361 B1
c2
.05 @
U.S. Patent
Feb. 17, 2004
o:
Sheet 8 0f 13
US 6,693,361 B1
ow.
mom _
82mom?
.052
U.S. Patent
Feb. 17, 2004
21
Sheet 9 0f 13
US 6,693,361 B1
2 1 a : , P...
o:
8+ .,
\\. ./\wa.. A a:f
ca2m5:Q58Q52OS
/ \ \ 1 \ I 1
.wE 2
U.S. Patent
Feb. 17, 2004
Sheet 10 0f 13
US 6,693,361 B1
.UE
(12)
United States Patent
(10) Patent N0.: (45) Date of Patent:
Siniaguine et al.
(54)
US 6,693,361 B1 Feb. 17, 2004
PACKAGING OF INTEGRATED CIRCUITS AND VERTICAL INTEGRATION
5,831,832 A 5,834,830 A
5,858,815 A
1/1999 Heo et al. .
438/112
(75) Inventors: Oleg Siniaguine, San Jose, CA (US);
5,863,812 A
1/1999 Manteghi ..
438/108
Sergey Savastiouk, San Jose, CA (US)
5,863,816
(73) Assignee: Tru-Si Technologies, Inc., Sunnyvale, CA (US)
(*)
Notice:
Subject to any disclaimer, the term of this patent is extended or adjusted under 35
U.S.C. 154(b) by 0 days.
11/1998 Gillette et al. ............ .. 361/760 11/1998 Cho ......................... .. 257/667
A
1/1999
Cho
5,872,051 A 5,879,964 A
2/1999 3/1999
Fallon et al. ............. .. 438/616 Paik et al. ................ .. 438/113
... .. ... ... .
. . . ..
438/123
5,886,398 A 5,886,414 A *
3/1999 Low et al. 3/1999 Galloway
257/667 257/784
5,889,332 A
3/1999
Lawson et al.
5,892,273 A 5,892,290 A 5,918,113 A
4/1999 4/1999 6/1999
IWasaki et al. ........... .. 257/690 Chakravorty et al. ..... .. 257/786 Higashi et al. ........... .. 438/119
.....
. . . ..
257/778
(List continued on neXt page.)
(21) Appl. No.: 09/716,092 Nov. 16, 2000 (22) Filed:
FOREIGN PATENT DOCUMENTS JP W0
Related US. Application Data
(62)
Division of application No. 09/456,225, ?led on Dec. 6,
(51)
Int. Cl.7 ....................... .. H01L 23/48; H01L 23/52;
(52) (58)
US. Cl. ...................... .. 257/777; 257/774; 257/778 Field of Search ............................... .. 257/774, 777,
403283641 A * 12/1991 WO 98/19337 5/1998
OTHER PUBLICATIONS
1999.
H01L 29/40
M. Amagai, et al., “Development of Chip Scale Packages (CSP) for Center Pad Devices,” 1997 Electronic Compo nents and Technology Conference, 1997 IEEE, pp. 343—352. (List continued on neXt page.)
257/778 Primary Examiner—Eddie Lee References Cited
(56)
Assistant Examiner—Joseph Nguyen (74) Attorney, Agent, or Firm—Michael
U.S. PATENT DOCUMENTS 4,612,083 A 4,704,785 A
4,890,784 A 4,933,743 A
5,064,771 A
9/1986 Yasumoto et al. ........ .. 156/633 * 11/1987
*
Curran ........... ..
1/1990 Bampton .... .. 6/1990 Thomas et al.
11/1991 Solomon
437/110
228/194 .. 357/71
437/3
5,225,771 A
7/1993 Leedy ............ ..
324/158
5,258,330 A
11/1993 Khandros et al. .
437/209
5,322,816 A 5,627,106 A
5,654,127 A
Shenker;
MacPherson KWok Chen & Heid LLP
6/1994 Pinter ............. .. 438/667 5/1997 Hsu ......................... .. 438/459
8/1997 Leedy ...................... .. 430/315
5,684,330 A
11/1997 Lee ................ ..
257/692
5,742,100 A
4/1998 Schroeder et al.
257/778
5,759,873 A 5,786,271 A
6/1998 Kata et al. ...... .. 438/118 7/1998 Ohida et al. .............. .. 438/615
5,798,567 A 5,817,541 A
10/1998 Averkiou et al. ......... .. 438/107
(57)
ABSTRACT
A ?rst level packaging Wafer is made of a semiconductor or
insulating material. The bumps on the Wafer are made using vertical integration technology, Without solder or electro plating. More particularly, vias are etched part Way into a ?rst surface of the substrate. Metal is deposited into the vias. Then the substrate is blanket-etched from the back side until the metal is exposed and protrudes from the vias to form
suitable bumps. Dicing methods and vertical integration methods are also provided. Solder or electroplating are used in some embodiments.
8/1998 Kelly et al. ............... .. 257/723
29 Claims, 13 Drawing Sheets
US 6,693,361 B1 Page 2
US. PATENT DOCUMENTS 5,998,292 A 6,083,773 A
12/1999 Black et al. .............. .. 438/618 7/2000 Lake .......... .. 438/108
6,087,719 A
*
7/2000
Tsunashima .... ..
257/686
6,157,082 A
* 12/2000 Merchant et al. .
257/758
6,184,060 B1 *
2/2001 Siniaguine
6,194,781 B1 * 6,229,209 B1 *
2/2001 5/2001
438/106
Ikegami .................... .. 257/737 Nakamura et al. ........ .. 257/737
OTHER PUBLICATIONS
P. Elenius, “Flex on Cap—Solder Paste Bumping”, 1997
Electronic Components and Technology Conference, 1997 IEEE, pp. 248—252.
R. Fillion, et al., “Chip Scale Packaging Using Chip—on— Flex Technology”, 1997 Electronic Components and Tech nology Conference, 1997 IEEE, pp. 638—641. J. Kloeser et al., “Fine Pitch Stencil Printing of Sn/Pb and Lead Free Solders for Flip Chip Technology”, 1997 Elec
tronic Components and Technology Conference, 1997 IEEE, pp. 254—263.
Sara M. Chen, “Electroplated Hermetic Fiber”, 1998 Elec tronic Conference, 1998 IEEE, p. 418. L. Li, et al., “Stencil Printing Process Development for LoW
Cost Flip Chip Interconnect”, 1998 Electronic Components and Technology Conference, 1998 IEEE, pp. 421—426. G. Rinne, “Solder Bumping Methods for Flip Chip Pack aging”, 1997 Electronic Components and Technology Con ference, 1997 IEEE, pp. 241—247.
K. ShimokaWa, et al, “Micro—ball Bump for Flip Intercon nections”, 1998 Electronic Components and Technology Conference, 1998 IEEE, pp. 1472—1476. Y.C. Teo, “Low Cost Chip—Scale Package”, 1997 Electronic Components and Technology Conference, 1997 IEEE, pp. 358—363.
Y. Yamaji, et al., “Development of Highly Reliable CSP”, 1997 Electronic Components and Technology Conference,
L. Levine, “Ball Bumping and Coining Operations for Tab and Flip Chip”, 1997 Electronic Components and Technol
1997 IEEE, pp. 1022—1027.
ogy Conference, 1997 IEEE, pp. 265—273.
* cited by examiner
U.S. Patent
Feb. 17, 2004
Sheet 1 0f 13
US 6,693,361 B1
QNN
mo? CNN mom. . N
.05 mom. mom?
U.S. Patent
Feb. 17, 2004
Sheet 3 0f 13
US 6,693,361 B1
mom p _
.uE w
U.S. Patent
Feb. 17, 2004
Sheet 4 0f 13
3
F3
l F
US 6,693,361 B1
L
o
\f9
r?
F“
\
g
430
420
510430420
510420
FIG. 5
U.S. Patent
Feb. 17, 2004
Sheet 5 0f 13
-
US 6,693,361 B1
ll).
4%0
502 €,
l ~430
\ l
FIG. 6
@506
U.S. Patent
Feb. 17, 2004
Sheet 6 6f 13
US 6,693,361 B1
.05 w
U.S. Patent
Feb. 17, 2004
o:
Sheet 7 0f 13
US 6,693,361 B1
c2
.05 @
U.S. Patent
Feb. 17, 2004
o:
Sheet 8 0f 13
US 6,693,361 B1
ow.
mom _
82mom?
.052
U.S. Patent
Feb. 17, 2004
21
Sheet 9 0f 13
US 6,693,361 B1
2 1 a : , P...
o:
8+ .,
\\. ./\wa.. A a:f
ca2m5:Q58Q52OS
/ \ \ 1 \ I 1
.wE 2
U.S. Patent
Feb. 17, 2004
Sheet 10 0f 13
US 6,693,361 B1
.UE
