Process Compensated CMOS Temperature Sensor for Microprocessor ...
Process Compensated CMOS Temperature Sensor for Microprocessor Application Yaesuk Jeong and Farrokh Ayazi School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, USA E-mail: [email protected] Abstract— This paper presents the design and implementation of a process compensated CMOS temperature sensor that does not require any BJTs. CTAT and PTAT sensors that are based on temperature-dependent threshold voltage (VTH) are designed to have same process variation and outputs are subtracted to suppress the process spread. Proposed design is fabricated in a TSMC 0.18um 2P6M process and measured results show less than an -1.8°C to +0.9°C error over -40°C to 85°C after 1-point calibration. The noise level is less than 100uV/¥Hz, which is equivalent to 0.043°C and overall power consumption is 478uW.
I.
INTRODUCTION
With microprocessors scaling to higher performance and faster speed, heat dissipation has become a growing concern. Excessive heat degrades performance and increases power consumption of the entire system. To prevent overheating, multiple integrated temperature sensors are employed in the microprocessor to monitor its thermal distribution. Many CMOS based temperature sensors have been reported with wide operating temperature range and high accuracy. Temperature sensors based on temperaturedependent base-emitter voltage of bipolar junction transistor (BJT) are very popular, showing inaccuracy of less than ±0.1°C (3ı) over the military temperature range [1]. However, in a deep sub-micron digital CMOS process, such an approach may experience performance degradation of the parasitic BJT, and require curvature correction using FPGA to ensure high accuracy. Chen [2] proposed another temperature sensor based on the temperature-dependent inverter delay. This work is implemented in all-digital circuit, so the design is suitable for microprocessor applications. However, as output is expressed in time-domain, any variation on the main clock adds additional errors. Another way to sense temperature is by using the threshold voltage of a MOS transistor [3]-[4]. As this method does not require any BJTs, it is scalable with process node, and doesn’t suffer from performance degradation using deep submicron process. Furthermore, as the output is expressed in voltage, it does not impose a strict requirement on the variation in clock frequency at various temperatures. These
978-1-4673-0219-7/12/$31.00 ©2012 IEEE
features make VTH-based sensing suitable for thermal monitoring of the microprocessor. However, threshold voltage suffers from larger process variation compared to base-emitter voltage of BJT, so that inaccuracy between VTHbased sensors become higher than several degrees even after costly two-point calibration. To overcome these issues, we propose a process compensated VTH-based temperature sensor, which eliminates the spread by subtracting outputs from two different temperature sensors (CTAT and PTAT). Both sensors are implemented to have same process variation so that the process-dependent signal is considered as common-mode signal and eliminated by subtraction. II. A.
TEMPERATURE SENSOR DESIGN
Principle of Operation
Figure 1: Schematic of proposed temperature sensing circuit
The proposed sensor is based on the temperature dependency of the threshold voltage VTH, which is expressed in Equation (1) [5]. VTH = VTH 0 + α (T − T0 ) (Į=-0.5~2mV/°C)
(1)
The VTH extractor circuit described in [6] generates this voltage as an output. In this work, which is shown in Figure 1, several modifications were applied to the original design to obtain the desired temperature coefficient (TC) value as well as the TC of VTH.
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(a) (b) Figure 3: (a) Schematic and (b) simulation result of the reference circuit Figure 2: Simulation result of proposed temperature sensing circuit on various transistor size ratios
When a bias voltage is applied, the current flowing on transistor M1 (IDM1) is expressed in Equation (2). Through current mirror, current flow in transistor M2 (IDM2) becomes C times larger than IDM1 (3). From this relationship, the output voltage is expressed as Equation (4). 1 W ID.M 1 = µn Cox ( )(Vφ − Vthn ) 2 2 L
ID.M 2 = C × ID.M 1 VOUT = (1 −
C(W L)1 C(W L)1 )Vthn + Vφ (W L) 2 (W L) 2
III. PROCESS COMPENSATION A. Process Variation in VTH-Based Temperature Sensor Process variation in the VTH-based sensor can result from slope and offset variation. These variations can be expressed as the process-dependent term in Equation (6). ǻaprocess represents a slope variation and ǻbprocess as an offset variation. VOUT = (a + ∆a process )T + (b + ∆bprocess )
Assuming we are subtracting output of two different temperature sensors (7)-(8), the final output is described by following Equation (9).
(2) (3) (4)
V1 = (a1 + ∆a1.process )T + b1 + ∆b1. process
(7)
V2 = (a2 + ∆a2.process )T + b2 + ∆b2. process
(8)
V1 − V2 = ((a1 − a2 )T + (b1 − b2 ))
Equation (4) is simplified to (5) using Equation (1). VOUT = (1− γ )αT + (1− γ )β + γVφ
(6)
(9)
+(∆a1. process − ∆a2. process )T + ∆b1.process − ∆b2.process
(5)
C(W L)1 γ= ,Vthn = αT + β (W L)2
Equation (5) implies that TC is a function of Ȗ, which is the ratio of two transistors widths. Simulations show that the proposed temperature sensing circuit behaves as a CTAT or PTAT sensor depending on the value of Ȗ (Figure 2). B. CMOS Voltage Reference Because (5) also indicates that VOUT is a function of the bias voltage (V˭), the sensor requires a stable reference to maintain a linear output over temperature. Therefore a voltage reference circuit based on the proposed temperature sensor was implemented (Figure 3(a)). Since the sensitivity of the sensor is determined by transistor sizes, TC can be designed very low by having appropriate ratio between transistor sizes. We chose the value of Ȗ as 1 so that the circuit has the least temperature sensitivity, and function as a stable voltage reference. To provide the bias voltage without any external source, the sensor was self-biased by feeding the output to the gate of transistor M1. To prevent zero-current state caused by self-biasing, we inserted the start-up circuit at transistor M1 and M3. The simulation results in Figure 3(b) show less than 10ppm variation over the entire temperature range, which is stable enough for the proposed design.
To suppress the process spread in (9), the processdependent term in each sensor (7)-(8) must have the same polarity. However, temperature coefficients a1 and a2 require opposite polarities (CTAT and PTAT) to avoid a reduction in dynamic range. In conventional VTH-based sensor, which requires a different type of MOS transistor to generate an opposite TC, this condition is not easily realizable. Figure 4(a) and (b) show that VTH of NMOS and PMOS transistors experience different characteristic depending on each corner. As process-dependent term in each sensor is different, proposed method cannot suppress the spread. On the contrary, using the same type of transistor can eliminate the process-dependent term. But it degrades sensor sensitivity, because the sign of TC is same.
(a) (b) Figure 4: Process dependency of threshold voltage of (a) PMOS (b) NMOS transistor with respect to various temperatures.
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(a) (b) Figure 5: Monte-carlo simulation of a temperature sensor (a) with and (b) without process compensation.
Figure 7: System diagram of the proposed temperature sensor
The proposed sensor can achieve both compensation in process spread and increase in sensor sensitivity. As the polarity of the TC can be made opposite by just changing the transistor sizes, but not by changing its type, the condition for proposed compensation technique complies. By subtracting two signals, the process-dependent term in Equation (9) is removed and sensitivity of the sensor becomes higher. To verify the effect of compensation technique, we performed Monte-carlo simulations of two cases, with and without process compensation. Figure 5 shows that when the proposed technique is applied, there is a two-folds decrease in the standard deviation at the output. B. Overall System Structure The temperature sensor system consists of CTAT and PTAT sensors (Figure 7), which are biased from the same CMOS voltage reference to cancel any process variations of the reference itself. A switched capacitor (SC) amplifier and sample and hold circuit subtracts signals from temperature sensor and eliminates common-mode process-dependent term. The reason for using an SC amplifier is that the capacitor has less temperature dependency compared to the resistor and adds less gain error at various temperatures. After sample and hold, the differential signal is converted to a single-ended output by an instrumentation amplifier. The low-frequency noise and offset of the sensor is suppressed by the correlated double sampling (CDS) technique [7] in SC amplifier. Simulation results with and without CDS show it has nearly 10dB improvement in noise performance (Figure 6(a)). A PSRR simulation determined the effect of the supply noise on the sensor (Figure 6(b)).
(a) (b) Figure 6: (a) Noise simulation with and without CDS technique (b) PSRR simulation of proposed temperature sensor
IV.
MEASUREMENTS
The proposed temperature sensor was fabricated in a TSMC 0.18um process (Figure 8). The size of the sensor is 180um x 240um, excluding the pads. The IC was placed on a board, and kept inside an SH-24 temperature chamber with a built-in temperature reference. We measured four ICs from -40°C to 85°C using Agilent 34401 6-bit digital multimeter. The results are shown in Figure 9(a). Figure 9(b) shows the results after one-point calibration at 20°C. The measured TC is 2.33mV/°C, and its R2 value is larger than 0.999. The inaccuracy of the sensor was calculated by dividing the deviation between the sensor outputs and the reference by the TC value. The error after one-point calibration is less than -0.9°C to +1.8°C over the entire temperature range (Figure 10(a)). Accuracy of a two-point calibration is measured to be -1.5°C to +0.5°C, which is less than that of one-point calibration (Figure 10(b)).
Figure 8: Optical micrograph of fabricated temperature sensor
(a) (b) Figure 9: Measured results of (a) four ICs and (b) after 1-point calibration at 20°C
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Sensor measurements showed an error less than -0.9°C to +1.8°C after 1-point calibration in a -40°C to 85°C temperature range. Because of its BJT-less feature and highly linear characteristic on the output voltage, this design is a promising candidate for on-chip thermal monitoring in microprocessor applications. TABLE I. (a) (b) Figure 10: Measured temperature error after (a) 1-point calibration and (b) 2point calibration
Method
We believe that the errors result from non-idealities existing in the temperature sensor. Because both sensors cannot have the same process variation, residual terms still remain after the subtraction and contribute to the error. In addition, the feedback capacitance mismatches of the SC amplifier between each IC create sensitivity variation. To estimate the resolution of the sensor, we measured the output spectrum, while keeping the temperature sensor in a 20°C environment. Figure 11 shows the measured spectrum. Through the CDS technique, results show a noise level of less than 100uV/¥Hz at 1Hz. Considering TC of 2.33mV/°C, this value is equivalent to a temperature of 0.043°C. By integrating the data over the frequency of interest (0.125Hz~50Hz), we calculated overall noise of 461uV. The performance of this work is compared with other temperature sensors in Table I. Through the process compensation technique presented, the sensor shows considerably low temperature error after one-point calibration among VTH-based sensors. Additionally, accurate sensor is realized without relying on any curvature correction method using bulky FPGAs.
Error -0.9°C /+1.8°C
VTH Based
-45°C ~ +85°C
[1]
VBE Based
-55°C ~ +125°C
(1-point Cal)
[2]
Inverter Delay
0 °C ~ +100°C
-0.7°C /+0.9°C
Size 0.04mm (180nm)
478uW
4.5mm2 (0.7um)
187.5uW
0.175mm2 (0.35um)
10uW
(1-point Cal)
±0.1°C
(2-point Cal)
Power 2
2
±1°C
0.003m (1um)
100uW
-2°C /+7°C
-
25uW
0.02mm2 (32nm)
1.6mW
0.12mm2 (130nm)
1.2mW
[3]
VTH Based
+10°C ~ +100°C
[4]
VTH Based
-50°C ~ +125°C
[8]
VBE Based
-10°C ~ +110°C
(no Cal)
[9]
Inverter Delay
0°C ~ +100°C
-1.8°C /+2.3°C
(1-point Cal)
5°C
(1-point Cal)
ACKNOWLEDGMENT The author would like to thank Mr. Mauricio Pardo for fruitful discussion and advice about this research. REFERENCES [1] [2] [3] [4]
[5]
[6] [7]
CONCLUSION
This paper presented a process compensated VTH-based CMOS temperature sensor. Its large process variation feature, which is inherent in the threshold voltage of the MOS transistor, is suppressed by means of subtracting both signals from the CTAT and PTAT sensors. Because the processdependent term inside the sensor output is a common-mode signal, it is removed through the presented method.
Range
This work
Figure 11: Measurement of noise from the proposed temperature sensor
V.
PERFORMANCE COMPARISON WITH OTHER WORKS
[8]
[9]
3121
M. Pertijs, K. Makinwa, and J.Huijsing, “A CMOS Temperature Sensor with a 3 sigma Inaccuracy of 0.1C from -55°C to 120°C” IEEE J. Solid-State Circuits, vol. 40, no.12, pp. 2805-2815, Dec. 2005. P. Chen, C. Chen, C. Tsai, and W. Lu, “A Time-to Digital Converter Based CMOS Smart Temperature sensor” IEEE J. Solid-State Circuits, vol. 40, no.8, pp. 1642-1648, Aug. 2005. V. Szekely, Cs. Marta, Zs. Kohari, and M. Rencz “CMOS Sensors for On-Line Thermal Monitoring of VLSI Circuits” IEEE Trans. Very Large Scale Integration Systems, vol. 5, no. 3, pp. 270-276, Sep. 1997. M. Sasaki, M. Ikeda, K. Asada “A Temperature Sensor with an Inaccuracy of -1/+0.8°C using 90nm 1-V CMOS for Online Thermal Monitoring of VLSI Circuits” IEEE Trans. Semiconductor Manufacturing, vol. 21, no.2, pp. 201-208, May. 2008. I. Filanovsky, and S. Lim, “Interaction of Threshold Voltage and Mobility Temperature Dependencies Applied to Stabilization of Current and Voltage,” IEEE Circuits and Systems, vol. 3, pp. 10221025, Aug. 2000. Z. Wang, “Automatic VT extractors based on an n x n2 MOS transistor array and their application,” IEEE J. Solid-State Circuits, vol.27, no. 9, pp. 1277-1285, Sep. 1992. B. V. Amini, and F. Ayazi “A 2.5-V 14-bit Ȉǻ CMOS SOI capacitive accelerometer” IEEE J. Solid-State Circuits, vol. 39, no.12, pp. 24672476, Dec. 2004. Y. William Li, Hasnain Lakdawala, Arijit Raychowdhury, Greg Taylor, K. Soumyanath “A 1.05V 1.6mW 0.45°C 3ı-Resoultion ǻȈBased Temperature Sensor with Parasitic Resistance Compensation” IEEE ISSCC Dig., pp. 340-341, Feb. 2009. K. Woo, S. Meninger, T. Xanthopoulos, E. Crain, D. Ha, and D. Ham “Dual-DLL Based CMOS All-Digital Temperature Sensor for Microprocessor Thermal Monitoring” IEEE ISSCC Dig., pp. 68-69, Feb. 2009.
I.
INTRODUCTION
With microprocessors scaling to higher performance and faster speed, heat dissipation has become a growing concern. Excessive heat degrades performance and increases power consumption of the entire system. To prevent overheating, multiple integrated temperature sensors are employed in the microprocessor to monitor its thermal distribution. Many CMOS based temperature sensors have been reported with wide operating temperature range and high accuracy. Temperature sensors based on temperaturedependent base-emitter voltage of bipolar junction transistor (BJT) are very popular, showing inaccuracy of less than ±0.1°C (3ı) over the military temperature range [1]. However, in a deep sub-micron digital CMOS process, such an approach may experience performance degradation of the parasitic BJT, and require curvature correction using FPGA to ensure high accuracy. Chen [2] proposed another temperature sensor based on the temperature-dependent inverter delay. This work is implemented in all-digital circuit, so the design is suitable for microprocessor applications. However, as output is expressed in time-domain, any variation on the main clock adds additional errors. Another way to sense temperature is by using the threshold voltage of a MOS transistor [3]-[4]. As this method does not require any BJTs, it is scalable with process node, and doesn’t suffer from performance degradation using deep submicron process. Furthermore, as the output is expressed in voltage, it does not impose a strict requirement on the variation in clock frequency at various temperatures. These
978-1-4673-0219-7/12/$31.00 ©2012 IEEE
features make VTH-based sensing suitable for thermal monitoring of the microprocessor. However, threshold voltage suffers from larger process variation compared to base-emitter voltage of BJT, so that inaccuracy between VTHbased sensors become higher than several degrees even after costly two-point calibration. To overcome these issues, we propose a process compensated VTH-based temperature sensor, which eliminates the spread by subtracting outputs from two different temperature sensors (CTAT and PTAT). Both sensors are implemented to have same process variation so that the process-dependent signal is considered as common-mode signal and eliminated by subtraction. II. A.
TEMPERATURE SENSOR DESIGN
Principle of Operation
Figure 1: Schematic of proposed temperature sensing circuit
The proposed sensor is based on the temperature dependency of the threshold voltage VTH, which is expressed in Equation (1) [5]. VTH = VTH 0 + α (T − T0 ) (Į=-0.5~2mV/°C)
(1)
The VTH extractor circuit described in [6] generates this voltage as an output. In this work, which is shown in Figure 1, several modifications were applied to the original design to obtain the desired temperature coefficient (TC) value as well as the TC of VTH.
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(a) (b) Figure 3: (a) Schematic and (b) simulation result of the reference circuit Figure 2: Simulation result of proposed temperature sensing circuit on various transistor size ratios
When a bias voltage is applied, the current flowing on transistor M1 (IDM1) is expressed in Equation (2). Through current mirror, current flow in transistor M2 (IDM2) becomes C times larger than IDM1 (3). From this relationship, the output voltage is expressed as Equation (4). 1 W ID.M 1 = µn Cox ( )(Vφ − Vthn ) 2 2 L
ID.M 2 = C × ID.M 1 VOUT = (1 −
C(W L)1 C(W L)1 )Vthn + Vφ (W L) 2 (W L) 2
III. PROCESS COMPENSATION A. Process Variation in VTH-Based Temperature Sensor Process variation in the VTH-based sensor can result from slope and offset variation. These variations can be expressed as the process-dependent term in Equation (6). ǻaprocess represents a slope variation and ǻbprocess as an offset variation. VOUT = (a + ∆a process )T + (b + ∆bprocess )
Assuming we are subtracting output of two different temperature sensors (7)-(8), the final output is described by following Equation (9).
(2) (3) (4)
V1 = (a1 + ∆a1.process )T + b1 + ∆b1. process
(7)
V2 = (a2 + ∆a2.process )T + b2 + ∆b2. process
(8)
V1 − V2 = ((a1 − a2 )T + (b1 − b2 ))
Equation (4) is simplified to (5) using Equation (1). VOUT = (1− γ )αT + (1− γ )β + γVφ
(6)
(9)
+(∆a1. process − ∆a2. process )T + ∆b1.process − ∆b2.process
(5)
C(W L)1 γ= ,Vthn = αT + β (W L)2
Equation (5) implies that TC is a function of Ȗ, which is the ratio of two transistors widths. Simulations show that the proposed temperature sensing circuit behaves as a CTAT or PTAT sensor depending on the value of Ȗ (Figure 2). B. CMOS Voltage Reference Because (5) also indicates that VOUT is a function of the bias voltage (V˭), the sensor requires a stable reference to maintain a linear output over temperature. Therefore a voltage reference circuit based on the proposed temperature sensor was implemented (Figure 3(a)). Since the sensitivity of the sensor is determined by transistor sizes, TC can be designed very low by having appropriate ratio between transistor sizes. We chose the value of Ȗ as 1 so that the circuit has the least temperature sensitivity, and function as a stable voltage reference. To provide the bias voltage without any external source, the sensor was self-biased by feeding the output to the gate of transistor M1. To prevent zero-current state caused by self-biasing, we inserted the start-up circuit at transistor M1 and M3. The simulation results in Figure 3(b) show less than 10ppm variation over the entire temperature range, which is stable enough for the proposed design.
To suppress the process spread in (9), the processdependent term in each sensor (7)-(8) must have the same polarity. However, temperature coefficients a1 and a2 require opposite polarities (CTAT and PTAT) to avoid a reduction in dynamic range. In conventional VTH-based sensor, which requires a different type of MOS transistor to generate an opposite TC, this condition is not easily realizable. Figure 4(a) and (b) show that VTH of NMOS and PMOS transistors experience different characteristic depending on each corner. As process-dependent term in each sensor is different, proposed method cannot suppress the spread. On the contrary, using the same type of transistor can eliminate the process-dependent term. But it degrades sensor sensitivity, because the sign of TC is same.
(a) (b) Figure 4: Process dependency of threshold voltage of (a) PMOS (b) NMOS transistor with respect to various temperatures.
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(a) (b) Figure 5: Monte-carlo simulation of a temperature sensor (a) with and (b) without process compensation.
Figure 7: System diagram of the proposed temperature sensor
The proposed sensor can achieve both compensation in process spread and increase in sensor sensitivity. As the polarity of the TC can be made opposite by just changing the transistor sizes, but not by changing its type, the condition for proposed compensation technique complies. By subtracting two signals, the process-dependent term in Equation (9) is removed and sensitivity of the sensor becomes higher. To verify the effect of compensation technique, we performed Monte-carlo simulations of two cases, with and without process compensation. Figure 5 shows that when the proposed technique is applied, there is a two-folds decrease in the standard deviation at the output. B. Overall System Structure The temperature sensor system consists of CTAT and PTAT sensors (Figure 7), which are biased from the same CMOS voltage reference to cancel any process variations of the reference itself. A switched capacitor (SC) amplifier and sample and hold circuit subtracts signals from temperature sensor and eliminates common-mode process-dependent term. The reason for using an SC amplifier is that the capacitor has less temperature dependency compared to the resistor and adds less gain error at various temperatures. After sample and hold, the differential signal is converted to a single-ended output by an instrumentation amplifier. The low-frequency noise and offset of the sensor is suppressed by the correlated double sampling (CDS) technique [7] in SC amplifier. Simulation results with and without CDS show it has nearly 10dB improvement in noise performance (Figure 6(a)). A PSRR simulation determined the effect of the supply noise on the sensor (Figure 6(b)).
(a) (b) Figure 6: (a) Noise simulation with and without CDS technique (b) PSRR simulation of proposed temperature sensor
IV.
MEASUREMENTS
The proposed temperature sensor was fabricated in a TSMC 0.18um process (Figure 8). The size of the sensor is 180um x 240um, excluding the pads. The IC was placed on a board, and kept inside an SH-24 temperature chamber with a built-in temperature reference. We measured four ICs from -40°C to 85°C using Agilent 34401 6-bit digital multimeter. The results are shown in Figure 9(a). Figure 9(b) shows the results after one-point calibration at 20°C. The measured TC is 2.33mV/°C, and its R2 value is larger than 0.999. The inaccuracy of the sensor was calculated by dividing the deviation between the sensor outputs and the reference by the TC value. The error after one-point calibration is less than -0.9°C to +1.8°C over the entire temperature range (Figure 10(a)). Accuracy of a two-point calibration is measured to be -1.5°C to +0.5°C, which is less than that of one-point calibration (Figure 10(b)).
Figure 8: Optical micrograph of fabricated temperature sensor
(a) (b) Figure 9: Measured results of (a) four ICs and (b) after 1-point calibration at 20°C
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Sensor measurements showed an error less than -0.9°C to +1.8°C after 1-point calibration in a -40°C to 85°C temperature range. Because of its BJT-less feature and highly linear characteristic on the output voltage, this design is a promising candidate for on-chip thermal monitoring in microprocessor applications. TABLE I. (a) (b) Figure 10: Measured temperature error after (a) 1-point calibration and (b) 2point calibration
Method
We believe that the errors result from non-idealities existing in the temperature sensor. Because both sensors cannot have the same process variation, residual terms still remain after the subtraction and contribute to the error. In addition, the feedback capacitance mismatches of the SC amplifier between each IC create sensitivity variation. To estimate the resolution of the sensor, we measured the output spectrum, while keeping the temperature sensor in a 20°C environment. Figure 11 shows the measured spectrum. Through the CDS technique, results show a noise level of less than 100uV/¥Hz at 1Hz. Considering TC of 2.33mV/°C, this value is equivalent to a temperature of 0.043°C. By integrating the data over the frequency of interest (0.125Hz~50Hz), we calculated overall noise of 461uV. The performance of this work is compared with other temperature sensors in Table I. Through the process compensation technique presented, the sensor shows considerably low temperature error after one-point calibration among VTH-based sensors. Additionally, accurate sensor is realized without relying on any curvature correction method using bulky FPGAs.
Error -0.9°C /+1.8°C
VTH Based
-45°C ~ +85°C
[1]
VBE Based
-55°C ~ +125°C
(1-point Cal)
[2]
Inverter Delay
0 °C ~ +100°C
-0.7°C /+0.9°C
Size 0.04mm (180nm)
478uW
4.5mm2 (0.7um)
187.5uW
0.175mm2 (0.35um)
10uW
(1-point Cal)
±0.1°C
(2-point Cal)
Power 2
2
±1°C
0.003m (1um)
100uW
-2°C /+7°C
-
25uW
0.02mm2 (32nm)
1.6mW
0.12mm2 (130nm)
1.2mW
[3]
VTH Based
+10°C ~ +100°C
[4]
VTH Based
-50°C ~ +125°C
[8]
VBE Based
-10°C ~ +110°C
(no Cal)
[9]
Inverter Delay
0°C ~ +100°C
-1.8°C /+2.3°C
(1-point Cal)
5°C
(1-point Cal)
ACKNOWLEDGMENT The author would like to thank Mr. Mauricio Pardo for fruitful discussion and advice about this research. REFERENCES [1] [2] [3] [4]
[5]
[6] [7]
CONCLUSION
This paper presented a process compensated VTH-based CMOS temperature sensor. Its large process variation feature, which is inherent in the threshold voltage of the MOS transistor, is suppressed by means of subtracting both signals from the CTAT and PTAT sensors. Because the processdependent term inside the sensor output is a common-mode signal, it is removed through the presented method.
Range
This work
Figure 11: Measurement of noise from the proposed temperature sensor
V.
PERFORMANCE COMPARISON WITH OTHER WORKS
[8]
[9]
3121
M. Pertijs, K. Makinwa, and J.Huijsing, “A CMOS Temperature Sensor with a 3 sigma Inaccuracy of 0.1C from -55°C to 120°C” IEEE J. Solid-State Circuits, vol. 40, no.12, pp. 2805-2815, Dec. 2005. P. Chen, C. Chen, C. Tsai, and W. Lu, “A Time-to Digital Converter Based CMOS Smart Temperature sensor” IEEE J. Solid-State Circuits, vol. 40, no.8, pp. 1642-1648, Aug. 2005. V. Szekely, Cs. Marta, Zs. Kohari, and M. Rencz “CMOS Sensors for On-Line Thermal Monitoring of VLSI Circuits” IEEE Trans. Very Large Scale Integration Systems, vol. 5, no. 3, pp. 270-276, Sep. 1997. M. Sasaki, M. Ikeda, K. Asada “A Temperature Sensor with an Inaccuracy of -1/+0.8°C using 90nm 1-V CMOS for Online Thermal Monitoring of VLSI Circuits” IEEE Trans. Semiconductor Manufacturing, vol. 21, no.2, pp. 201-208, May. 2008. I. Filanovsky, and S. Lim, “Interaction of Threshold Voltage and Mobility Temperature Dependencies Applied to Stabilization of Current and Voltage,” IEEE Circuits and Systems, vol. 3, pp. 10221025, Aug. 2000. Z. Wang, “Automatic VT extractors based on an n x n2 MOS transistor array and their application,” IEEE J. Solid-State Circuits, vol.27, no. 9, pp. 1277-1285, Sep. 1992. B. V. Amini, and F. Ayazi “A 2.5-V 14-bit Ȉǻ CMOS SOI capacitive accelerometer” IEEE J. Solid-State Circuits, vol. 39, no.12, pp. 24672476, Dec. 2004. Y. William Li, Hasnain Lakdawala, Arijit Raychowdhury, Greg Taylor, K. Soumyanath “A 1.05V 1.6mW 0.45°C 3ı-Resoultion ǻȈBased Temperature Sensor with Parasitic Resistance Compensation” IEEE ISSCC Dig., pp. 340-341, Feb. 2009. K. Woo, S. Meninger, T. Xanthopoulos, E. Crain, D. Ha, and D. Ham “Dual-DLL Based CMOS All-Digital Temperature Sensor for Microprocessor Thermal Monitoring” IEEE ISSCC Dig., pp. 68-69, Feb. 2009.
