SLG43880 Power Rail Sequencer
SLG43880 GreenPAK™
Power Rail Sequencer
NC VDD
1
NC
12 11
10
FLAG3
2
9
FLAG2
EN
3
8
FLAG1
NC
4
7
GND
5 6
6
NC
The device is housed in a 1.6 x 1.6 mm STQFN package, and features ultra-low quiescent current making it optimal for use within portable battery powered electronic devices. The SLG3880 features an accurate input comparator and 3 open drain outputs. During a power-up condition these outputs will sequence with a fixed delay. During power-down these outputs will sequence in reverse order to avoid latch-up conditions.
NC
Pin Configuration
Silego SLG43880 Power Rail Sequencer offers simple control over independent voltage rails. Delayed power rail sequencing enables a designer to reduce inrush current and avoid latch up conditions, thus increasing system reliability.
NC
General Description
STQFN-12 TOP VIEW
Features • • • • • • • • •
Power-Up and Power-Down control Low Quiescent current of 35uA 3 independent power rails controls Voltage range 3V to 3.6V Glitch free enable input Only 1 additional passive component required Pb-Free / RoHS Compliant Halogen-Free STQFN-12 Package
Output Summary • • • •
3. 8. 9. 10.
EN FLAG1 FLAG2 FLAG3
Analog input Open Drain Open Drain Open Drain
Silego Technology, Inc. SLG43880_r010
Preliminary
Rev 0.10 Revised October 15, 2017
SLG43880 Power Rail Sequencer Block Diagram
SLG43880_r010
Preliminary
Page 2 2
SLG43880 Power Rail Sequencer Pin Configuration Pin # 1 2 3 4 5 6 7 8 9 10 11 12
Pin Name VDD NC EN NC NC NC GND FLAG1 FLAG2 FLAG3 NC NC
Type PWR Analog GND Open Drain Open Drain Open Drain -
Pin Description Supply Voltage Analog Comparator input Ground Output Flag 1 Output Flag 2 Output Flag 3 -
Internal Resistor
1M Pullup 1M Pullup 1M Pullup
Ordering Information Part Number SLG43880V SLG43880VTR
SLG43880_r010
Package Type V=STQFN-12 STQFN-12 – Tape and Reel (3k units)
Preliminary
Page 3 3
SLG43880 Power Rail Sequencer Absolute Maximum Conditions Parameter
Min.
Max.
Unit
VHIGH to GND
-0.3
7
V
Voltage at input pins
-0.3
7
V
Maximum Average or DC current (Through Pin)
--
18
mA
Current at input pin
-1.0
1.0
mA
Storage temperature range
-65
125
°C
Junction temperature
--
150
°C
ESD Protection (Human Body Model)
2000
--
V
ESD Protection (Charged Device Model)
1000
--
V
Moisture Sensitivity Level
1
Electrical Characteristics (@ 25°C, unless otherwise stated) Symbol Parameter VDD Supply Voltage IQ Quiescent Current TA Operating Temperature Maximal Voltage Applied to VO any PIN in High-Impedance State Maximal Average or DC IO Current (note 1) VAIR Analog Input Voltage Range IIH HIGH-Level Input Current IIL LOW-Level Input Current VOL LOW-Level Output Voltage LOW-Level Output Current IOL (note 2) TSU Start up Time Td1 EN rising edge timer delay Td2 EN falling edge timer delay Tdelay Other Timer Delays Terror Additional Timing error VEN EN pin input threshold Vhysteresis Typical hysteresis
Condition/Note VDD = EN = 3V
Per Each Chip Side
Logic Input PINs; VIN = VDD Logic Input PINs; VIN = 0V Open Drain Outputs VOL = 0.4 V From VDD rising past 1.35V
Min. 3 30 -40
Typ. 3.3 35 25
Max. 3.6 40 85
Unit V µA °C
--
--
VDD
V
--
--
90
mA
0 -1.0 -1.0 --
---0.090
VDD 1.0 1.0 0.130
V µA µA V
8.130
12.410
--
mA
-58 58 58 90 1.1 --
0.27 70 70 60
-80 80 62 110 1.3 --
ms ms ms ms % V mV
100
1. Guaranteed by Design. 2. DC or average current through any pin should not exceed values listed in Absolute Maximum Conditions.
SLG43880_r010
Preliminary
Page 4 4
SLG43880 Power Rail Sequencer Description Overview Upon powerup the output flags are hold LOW by the open drain inputs. Internal 1M Ohm pullups are present on these pins to reduce overall board space. An internal analog comparator and voltage reference will detect transitions on the EN input pin to control the sequencing logic. When the EN pin crosses an input threshold of 1.2 Volts the outputs are These outputs are released into a high-impedance state in the following order FLAG1, FLAG2, FLAG3. Once the input voltage falls below 1.2 volts the outputs are sequenced in reverse order. The EN input is designed to be glitch free to ensure reliable device operation. The internal voltage comparator and reference voltage are configured to run at a reduced duty cycle to reduce quiescent current of the device. As a result, the first delay time will contain some additional jitter.
Enable Pin The enable pin is connected to an internal comparator which is referenced to an internal reference of 1.2V. This enables precision control over the sequencing operation. For added design flexibility an external RC network can be connected to this pin to increase initial startup delay. Alternatively, a resistor divider can be utilized to set a different threshold voltage better suited to your specific application.
Figure 1: Input comparator The input comparator features a 100mV hysteresis and a bandwidth liming system to reduce the effects of noise present on the EN pin. An internal counter is used to deglitch the input signal prior to the FLAG 1 being released. The first counter delays the rising edge of the input signal and any falling edges cause this timer to reset.
Figure 2: EN Deglitch
SLG43880_r010
Preliminary
Page 5 5
SLG43880 Power Rail Sequencer Power Up Operation Once the input pin has been asserted the outputs will begin their sequence after 1 time interval. This first timeinterval is used to deglitch the input (see above). After this initial delay, the outputs will be released according to the following diagram.
Figure 3: Power up Operation The sequence becomes complete 60ms after the last output is released. After this time if the output is released the power down sequence will initiate.
Power Down Operation After a Power-Up sequence has been complete if the EN pin is released the device will perform a power-down sequence. This occurs very similarly to the power-up operation but in reverse. After a unit delay of the input being LOW the output flags will be pulled LOW in a reverse sequence.
Figure 4: Power Down Operation *note due to an internal power reduction system the time between the EN pin releasing and the FLAG 3 being release has additional 10mS jitter. The time between flags being released is not affected.
Output Deglitch If the EN signal is released before the power sequence has completed the device will continue the sequence. Hold FLAG 3 in released state for 120ms then perform a power down sequence. Thus, completing a power up sequence before initiating a power-down sequence. This ensures no glitches occur on the output flags from the device.
SLG43880_r010
Preliminary
Page 6 6
SLG43880 Power Rail Sequencer
Figure 5: Output Deglitch
Low Power Operation To achieve the target quiescent current of 40uA a counter is used to reduce the duty cycle of the Analog comparator. This is possible due to the low bandwidth requirements of this device. The analog comparator is only required to be active during clock transitions incrementing the internal sequence shift register. However, this result in considerable jitter/delay detecting the power-up edge transition. PIN 3 EN
+ CNT/DLY2
Reconstructed Signal
PWR_ON
1.2V
OSC
Falling Edge Delay
CNT/DLY3
Rising Edge Delay
Figure 6: Power Reduction Circuit
A compromise is achieved by running the comparator at a 48Hz frequency, as-well as a reduced duty cycle. Two CNT/DLY modules are used to achieve this. One reduces the input duty cycle by delaying the rising edge. The second is used on the comparator output delaying the falling edge to recreate a digital representation of the analog input signal. A simulation plot is included here to show the input signal has increased jitter of up to 20ms due to the low duty cycle of the comparator.
SLG43880_r010
Preliminary
Page 7 7
SLG43880 Power Rail Sequencer
Figure 7: Internal Signals of power reduction circuit.
SLG43880_r010
Preliminary
Page 8 8
SLG43880 Power Rail Sequencer Typical Application Circuit
Figure 8: Basic Example Circuit
Ensure a decoupling capacitor is placed as close as possible to VCC pin.
SLG43880_r010
Preliminary
Page 9 9
SLG43880 Power Rail Sequencer Functionality Waveforms Standard operation showing input voltage and output sequence Channel 1: (Red/Top line) – Pin 3 (EN) Signal generator Channel 2 (Blue/2nd line) – Pin 8 (FLAG 1) With internal 1M Pull-up Channel 3 (Green/3nd line) – Pin 9 (FLAG 2) With internal 1M Pull-up Channel 4 (Yellow/4nd line) – Pin 10 (FLAG 3) With internal 1M Pull-up
Figure 9: Standard operation
SLG43880_r010
Preliminary
Page 10 10
SLG43880 Power Rail Sequencer Input glitch, showing device not activating for short EN pulse. Channel 1: (Red/Top line) – Pin 3 (EN) Signal generator Channel 2 (Blue/2nd line) – Pin 8 (FLAG 1) With internal 1M Pull-up Channel 3 (Green/3nd line) – Pin 9 (FLAG 2) With internal 1M Pull-up Channel 4 (Yellow/4nd line) – Pin 10 (FLAG 3) With internal 1M Pull-up
Figure 10: Short input rejection
SLG43880_r010
Preliminary
Page 11 11
SLG43880 Power Rail Sequencer Output Glitch, showing device activating and completing correct sequence. Channel 1: (Red/Top line) – Pin 3 (EN) Signal generator Channel 2 (Blue/2nd line) – Pin 8 (FLAG 1) With internal 1M Pull-up Channel 3 (Green/3nd line) – Pin 9 (FLAG 2) With internal 1M Pull-up Channel 4 (Yellow/4nd line) – Pin 10 (FLAG 3) With internal 1M Pull-up
Figure 11: Output Glitch
SLG43880_r010
Preliminary
Page 12 12
SLG43880 Power Rail Sequencer Input Glitch (power down), showing device not performing shutdown procedure on EN glitches shorter than 60ms. Channel 1: (Red/Top line) – Pin 3 (EN) Signal generator Channel 2 (Blue/2nd line) – Pin 8 (FLAG 1) With internal 1M Pull-up Channel 3 (Green/3nd line) – Pin 9 (FLAG 2) With internal 1M Pull-up Channel 4 (Yellow/4nd line) – Pin 10 (FLAG 3) With internal 1M Pull-up
Figure 12: Input Glitch, power down
SLG43880_r010
Preliminary
Page 13 13
SLG43880 Power Rail Sequencer Package Top Marking
Datasheet Revision 0.10
Programming Code Number 001
Locked Status U
Part Code
Revision
Date 15/10/2017
The IC security bit is locked/set for code security for production unless otherwise specified. Revision number is not changed for bit locking.
SLG43880_r010
Preliminary
Page 14 14
SLG43880 Power Rail Sequencer Package Drawing and Dimensions 12 Lead STQFN Package JEDEC MO-220
SLG43880_r010
Preliminary
Page 15 15
SLG43880 Power Rail Sequencer Tape and Reel Specification # of Package Type Pins
STQFN 12L FC 0.4P Green
12
Max Units
Nominal Package Size (mm)
per reel
1.6x1.6x0.55
3000
Trailer A
per box
Reel & Hub Size (mm)
Pockets
3000
178/60
100
Leader B
Pocket (mm)
Length Length Pockets (mm) (mm)
400
100
400
Width
Pitch
8
4
Carrier Tape Drawing and Dimensions Package Type
STQFN 12L FC 0.4P Green
Pocket BTM Length (mm)
Pocket BTM Width (mm)
Pocket Depth (mm)
Index Hole Pitch (mm)
Pocket Pitch (mm)
Index Hole Diameter (mm)
Index Hole Index Hole to Tape to Pocket Tape Width Edge Center (mm) (mm) (mm)
A0
B0
K0
P0
P1
D0
E
F
W
1.9
1.9
0.8
4
4
1.5
1.75
3.5
8
Refer to EIA-481 Specifications
Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 1.408 mm3 (nominal). More information can be found at www.jedec.org.
SLG43880_r010
Preliminary
Page 16 16
SLG43880 Power Rail Sequencer Recommended Land Pattern
SLG43880_r010
Preliminary
Page 17 17
SLG43880 Power Rail Sequencer Datasheet Revision History Date 15/10/2017
Version 0.10
SLG43880_r010
Change New design for SLG43880 chip. (GsD)
Preliminary
Page 18 18
SLG43880 Power Rail Sequencer Silego Website & Support Silego Technology Website Silego Technology provides online support via our website at http://www.silego.com/.This website is used as a means to make files and information easily available to customers. For more information regarding Silego Green products, please visit our website. Our Green product lines feature: GreenPAK1 / GreenPAK2 / GreenPAK3/ GreenPAK 4 / GreenPAK 5: Programmable Mixed Signal Matrix products GreenFET1 / GreenFET3: MOSFET Drivers and ultra-small, low RDSon Load Switches GreenCLK1 / GreenCLK2 / GreenCLK3: Crystal replacement technology Products are also available for purchase directly from Silego at the Silego Online Store at http://www.silego.com/buy/ . Silego Technical Support Datasheets and errata, application notes and example designs, user guides, and hardware support documents and the latest software releases are available at the Silego website or can be requested directly at [email protected]. For specific GreenPAK design or applications questions and support please send e-mail requests to [email protected] Users of Silego products can receive assistance through several channels: Contact Your Local Sales Representative Customers can contact their local sales representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. More information regarding your local representative is available at the Silego website or send a request to [email protected] Contact Silego Directly Silego can be contacted directly via e-mail at [email protected] or user submission form, located at the following URL: http://support.silego.com/ Other Information The latest Silego Technology press releases, listing of seminars and events, listings of world wide Silego Technology offices and representatives are all available at http://www.silego.com/ THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. SILEGO TECHNOLOGY DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. SILEGO TECHNOLOGY RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE
SLG43880_r010
Preliminary
Page 19 19
Power Rail Sequencer
NC VDD
1
NC
12 11
10
FLAG3
2
9
FLAG2
EN
3
8
FLAG1
NC
4
7
GND
5 6
6
NC
The device is housed in a 1.6 x 1.6 mm STQFN package, and features ultra-low quiescent current making it optimal for use within portable battery powered electronic devices. The SLG3880 features an accurate input comparator and 3 open drain outputs. During a power-up condition these outputs will sequence with a fixed delay. During power-down these outputs will sequence in reverse order to avoid latch-up conditions.
NC
Pin Configuration
Silego SLG43880 Power Rail Sequencer offers simple control over independent voltage rails. Delayed power rail sequencing enables a designer to reduce inrush current and avoid latch up conditions, thus increasing system reliability.
NC
General Description
STQFN-12 TOP VIEW
Features • • • • • • • • •
Power-Up and Power-Down control Low Quiescent current of 35uA 3 independent power rails controls Voltage range 3V to 3.6V Glitch free enable input Only 1 additional passive component required Pb-Free / RoHS Compliant Halogen-Free STQFN-12 Package
Output Summary • • • •
3. 8. 9. 10.
EN FLAG1 FLAG2 FLAG3
Analog input Open Drain Open Drain Open Drain
Silego Technology, Inc. SLG43880_r010
Preliminary
Rev 0.10 Revised October 15, 2017
SLG43880 Power Rail Sequencer Block Diagram
SLG43880_r010
Preliminary
Page 2 2
SLG43880 Power Rail Sequencer Pin Configuration Pin # 1 2 3 4 5 6 7 8 9 10 11 12
Pin Name VDD NC EN NC NC NC GND FLAG1 FLAG2 FLAG3 NC NC
Type PWR Analog GND Open Drain Open Drain Open Drain -
Pin Description Supply Voltage Analog Comparator input Ground Output Flag 1 Output Flag 2 Output Flag 3 -
Internal Resistor
1M Pullup 1M Pullup 1M Pullup
Ordering Information Part Number SLG43880V SLG43880VTR
SLG43880_r010
Package Type V=STQFN-12 STQFN-12 – Tape and Reel (3k units)
Preliminary
Page 3 3
SLG43880 Power Rail Sequencer Absolute Maximum Conditions Parameter
Min.
Max.
Unit
VHIGH to GND
-0.3
7
V
Voltage at input pins
-0.3
7
V
Maximum Average or DC current (Through Pin)
--
18
mA
Current at input pin
-1.0
1.0
mA
Storage temperature range
-65
125
°C
Junction temperature
--
150
°C
ESD Protection (Human Body Model)
2000
--
V
ESD Protection (Charged Device Model)
1000
--
V
Moisture Sensitivity Level
1
Electrical Characteristics (@ 25°C, unless otherwise stated) Symbol Parameter VDD Supply Voltage IQ Quiescent Current TA Operating Temperature Maximal Voltage Applied to VO any PIN in High-Impedance State Maximal Average or DC IO Current (note 1) VAIR Analog Input Voltage Range IIH HIGH-Level Input Current IIL LOW-Level Input Current VOL LOW-Level Output Voltage LOW-Level Output Current IOL (note 2) TSU Start up Time Td1 EN rising edge timer delay Td2 EN falling edge timer delay Tdelay Other Timer Delays Terror Additional Timing error VEN EN pin input threshold Vhysteresis Typical hysteresis
Condition/Note VDD = EN = 3V
Per Each Chip Side
Logic Input PINs; VIN = VDD Logic Input PINs; VIN = 0V Open Drain Outputs VOL = 0.4 V From VDD rising past 1.35V
Min. 3 30 -40
Typ. 3.3 35 25
Max. 3.6 40 85
Unit V µA °C
--
--
VDD
V
--
--
90
mA
0 -1.0 -1.0 --
---0.090
VDD 1.0 1.0 0.130
V µA µA V
8.130
12.410
--
mA
-58 58 58 90 1.1 --
0.27 70 70 60
-80 80 62 110 1.3 --
ms ms ms ms % V mV
100
1. Guaranteed by Design. 2. DC or average current through any pin should not exceed values listed in Absolute Maximum Conditions.
SLG43880_r010
Preliminary
Page 4 4
SLG43880 Power Rail Sequencer Description Overview Upon powerup the output flags are hold LOW by the open drain inputs. Internal 1M Ohm pullups are present on these pins to reduce overall board space. An internal analog comparator and voltage reference will detect transitions on the EN input pin to control the sequencing logic. When the EN pin crosses an input threshold of 1.2 Volts the outputs are These outputs are released into a high-impedance state in the following order FLAG1, FLAG2, FLAG3. Once the input voltage falls below 1.2 volts the outputs are sequenced in reverse order. The EN input is designed to be glitch free to ensure reliable device operation. The internal voltage comparator and reference voltage are configured to run at a reduced duty cycle to reduce quiescent current of the device. As a result, the first delay time will contain some additional jitter.
Enable Pin The enable pin is connected to an internal comparator which is referenced to an internal reference of 1.2V. This enables precision control over the sequencing operation. For added design flexibility an external RC network can be connected to this pin to increase initial startup delay. Alternatively, a resistor divider can be utilized to set a different threshold voltage better suited to your specific application.
Figure 1: Input comparator The input comparator features a 100mV hysteresis and a bandwidth liming system to reduce the effects of noise present on the EN pin. An internal counter is used to deglitch the input signal prior to the FLAG 1 being released. The first counter delays the rising edge of the input signal and any falling edges cause this timer to reset.
Figure 2: EN Deglitch
SLG43880_r010
Preliminary
Page 5 5
SLG43880 Power Rail Sequencer Power Up Operation Once the input pin has been asserted the outputs will begin their sequence after 1 time interval. This first timeinterval is used to deglitch the input (see above). After this initial delay, the outputs will be released according to the following diagram.
Figure 3: Power up Operation The sequence becomes complete 60ms after the last output is released. After this time if the output is released the power down sequence will initiate.
Power Down Operation After a Power-Up sequence has been complete if the EN pin is released the device will perform a power-down sequence. This occurs very similarly to the power-up operation but in reverse. After a unit delay of the input being LOW the output flags will be pulled LOW in a reverse sequence.
Figure 4: Power Down Operation *note due to an internal power reduction system the time between the EN pin releasing and the FLAG 3 being release has additional 10mS jitter. The time between flags being released is not affected.
Output Deglitch If the EN signal is released before the power sequence has completed the device will continue the sequence. Hold FLAG 3 in released state for 120ms then perform a power down sequence. Thus, completing a power up sequence before initiating a power-down sequence. This ensures no glitches occur on the output flags from the device.
SLG43880_r010
Preliminary
Page 6 6
SLG43880 Power Rail Sequencer
Figure 5: Output Deglitch
Low Power Operation To achieve the target quiescent current of 40uA a counter is used to reduce the duty cycle of the Analog comparator. This is possible due to the low bandwidth requirements of this device. The analog comparator is only required to be active during clock transitions incrementing the internal sequence shift register. However, this result in considerable jitter/delay detecting the power-up edge transition. PIN 3 EN
+ CNT/DLY2
Reconstructed Signal
PWR_ON
1.2V
OSC
Falling Edge Delay
CNT/DLY3
Rising Edge Delay
Figure 6: Power Reduction Circuit
A compromise is achieved by running the comparator at a 48Hz frequency, as-well as a reduced duty cycle. Two CNT/DLY modules are used to achieve this. One reduces the input duty cycle by delaying the rising edge. The second is used on the comparator output delaying the falling edge to recreate a digital representation of the analog input signal. A simulation plot is included here to show the input signal has increased jitter of up to 20ms due to the low duty cycle of the comparator.
SLG43880_r010
Preliminary
Page 7 7
SLG43880 Power Rail Sequencer
Figure 7: Internal Signals of power reduction circuit.
SLG43880_r010
Preliminary
Page 8 8
SLG43880 Power Rail Sequencer Typical Application Circuit
Figure 8: Basic Example Circuit
Ensure a decoupling capacitor is placed as close as possible to VCC pin.
SLG43880_r010
Preliminary
Page 9 9
SLG43880 Power Rail Sequencer Functionality Waveforms Standard operation showing input voltage and output sequence Channel 1: (Red/Top line) – Pin 3 (EN) Signal generator Channel 2 (Blue/2nd line) – Pin 8 (FLAG 1) With internal 1M Pull-up Channel 3 (Green/3nd line) – Pin 9 (FLAG 2) With internal 1M Pull-up Channel 4 (Yellow/4nd line) – Pin 10 (FLAG 3) With internal 1M Pull-up
Figure 9: Standard operation
SLG43880_r010
Preliminary
Page 10 10
SLG43880 Power Rail Sequencer Input glitch, showing device not activating for short EN pulse. Channel 1: (Red/Top line) – Pin 3 (EN) Signal generator Channel 2 (Blue/2nd line) – Pin 8 (FLAG 1) With internal 1M Pull-up Channel 3 (Green/3nd line) – Pin 9 (FLAG 2) With internal 1M Pull-up Channel 4 (Yellow/4nd line) – Pin 10 (FLAG 3) With internal 1M Pull-up
Figure 10: Short input rejection
SLG43880_r010
Preliminary
Page 11 11
SLG43880 Power Rail Sequencer Output Glitch, showing device activating and completing correct sequence. Channel 1: (Red/Top line) – Pin 3 (EN) Signal generator Channel 2 (Blue/2nd line) – Pin 8 (FLAG 1) With internal 1M Pull-up Channel 3 (Green/3nd line) – Pin 9 (FLAG 2) With internal 1M Pull-up Channel 4 (Yellow/4nd line) – Pin 10 (FLAG 3) With internal 1M Pull-up
Figure 11: Output Glitch
SLG43880_r010
Preliminary
Page 12 12
SLG43880 Power Rail Sequencer Input Glitch (power down), showing device not performing shutdown procedure on EN glitches shorter than 60ms. Channel 1: (Red/Top line) – Pin 3 (EN) Signal generator Channel 2 (Blue/2nd line) – Pin 8 (FLAG 1) With internal 1M Pull-up Channel 3 (Green/3nd line) – Pin 9 (FLAG 2) With internal 1M Pull-up Channel 4 (Yellow/4nd line) – Pin 10 (FLAG 3) With internal 1M Pull-up
Figure 12: Input Glitch, power down
SLG43880_r010
Preliminary
Page 13 13
SLG43880 Power Rail Sequencer Package Top Marking
Datasheet Revision 0.10
Programming Code Number 001
Locked Status U
Part Code
Revision
Date 15/10/2017
The IC security bit is locked/set for code security for production unless otherwise specified. Revision number is not changed for bit locking.
SLG43880_r010
Preliminary
Page 14 14
SLG43880 Power Rail Sequencer Package Drawing and Dimensions 12 Lead STQFN Package JEDEC MO-220
SLG43880_r010
Preliminary
Page 15 15
SLG43880 Power Rail Sequencer Tape and Reel Specification # of Package Type Pins
STQFN 12L FC 0.4P Green
12
Max Units
Nominal Package Size (mm)
per reel
1.6x1.6x0.55
3000
Trailer A
per box
Reel & Hub Size (mm)
Pockets
3000
178/60
100
Leader B
Pocket (mm)
Length Length Pockets (mm) (mm)
400
100
400
Width
Pitch
8
4
Carrier Tape Drawing and Dimensions Package Type
STQFN 12L FC 0.4P Green
Pocket BTM Length (mm)
Pocket BTM Width (mm)
Pocket Depth (mm)
Index Hole Pitch (mm)
Pocket Pitch (mm)
Index Hole Diameter (mm)
Index Hole Index Hole to Tape to Pocket Tape Width Edge Center (mm) (mm) (mm)
A0
B0
K0
P0
P1
D0
E
F
W
1.9
1.9
0.8
4
4
1.5
1.75
3.5
8
Refer to EIA-481 Specifications
Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 1.408 mm3 (nominal). More information can be found at www.jedec.org.
SLG43880_r010
Preliminary
Page 16 16
SLG43880 Power Rail Sequencer Recommended Land Pattern
SLG43880_r010
Preliminary
Page 17 17
SLG43880 Power Rail Sequencer Datasheet Revision History Date 15/10/2017
Version 0.10
SLG43880_r010
Change New design for SLG43880 chip. (GsD)
Preliminary
Page 18 18
SLG43880 Power Rail Sequencer Silego Website & Support Silego Technology Website Silego Technology provides online support via our website at http://www.silego.com/.This website is used as a means to make files and information easily available to customers. For more information regarding Silego Green products, please visit our website. Our Green product lines feature: GreenPAK1 / GreenPAK2 / GreenPAK3/ GreenPAK 4 / GreenPAK 5: Programmable Mixed Signal Matrix products GreenFET1 / GreenFET3: MOSFET Drivers and ultra-small, low RDSon Load Switches GreenCLK1 / GreenCLK2 / GreenCLK3: Crystal replacement technology Products are also available for purchase directly from Silego at the Silego Online Store at http://www.silego.com/buy/ . Silego Technical Support Datasheets and errata, application notes and example designs, user guides, and hardware support documents and the latest software releases are available at the Silego website or can be requested directly at [email protected]. For specific GreenPAK design or applications questions and support please send e-mail requests to [email protected] Users of Silego products can receive assistance through several channels: Contact Your Local Sales Representative Customers can contact their local sales representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. More information regarding your local representative is available at the Silego website or send a request to [email protected] Contact Silego Directly Silego can be contacted directly via e-mail at [email protected] or user submission form, located at the following URL: http://support.silego.com/ Other Information The latest Silego Technology press releases, listing of seminars and events, listings of world wide Silego Technology offices and representatives are all available at http://www.silego.com/ THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. SILEGO TECHNOLOGY DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. SILEGO TECHNOLOGY RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE
SLG43880_r010
Preliminary
Page 19 19
