SOME TECHNIQUES FOR LOW- VOLTAGE CONTINUOUS-TIME ...
SOME TECHNIQUES FOR LOWVOLTAGE CONTINUOUS-TIME ANALOG CIRCUIT OPERATION
Jaime Ramírez Angulo New Mexico State University, Las Cruces, NM
Some techniques for low-voltage operation of continuous-time analog CMOS circuits The drastic reduction in the supply voltages of CMOS VLSI systems driven by technological as well as power reduction constraints has forced analog designers to divert from conventional analog circuit architectures which become non functional in a reduced supply environment and look for new techniques for low voltage, high performance operation of analog CMOS circuits. In this presentation a family of high performance low-voltage analog CMOS circuits is introduced. These are based on the utilization of static, dynamic and switched floating voltage sources. These circuits operate in all cases with a single supply voltage close to a transistor's threshold voltage.Among the circuits discussed in this presentation we include: one and two stage class AB op-amps, rectifiers, filters, transconductors, analog multipliers, etc. Presented by Jaime Ramirez-Angulo, professor of Electrical Engineering , IEEE fellow and director of the VLSI lab at the Klipsch School of Electrical and Computer Engineering at New Mexico State University in Las Cruces, New Mexico (USA). He received a degree in Communications and Electronic Engineering (Professional degree), a M.S.E.E from the National Polytechnic Institute in Mexico City (1973 and 1976 respectively) and a Dr.-Ing. degree from the University of Stuttgart in Germany in 1982. His research is related to following areas of analog and mixed signal VLSI design: low-voltage CMOS circuit design, test techniques for mixed-signal VSLI systems, continuous-time filters and analog array processors.
OUTLINE I. II.
Introduction Basic techniques for continuous-time lowvoltage operation III. Continuous-time low-voltage amplifier schemes IV. Low-voltage op-amp architectures with rail-torail input and output swings V. Low-voltage circuits based on floating gates VI. Conclusions
I. INTRODUCTION: Why low-voltage? Within the next few years most mixed-signal systems will require operation with sub-volt supply voltages (VDD2Vth+VDSsat+Vbat
To minimize Vdd requirements: Inputs must operate close to lower rail at approximately constant voltage (Vinswing=0)
Rail-to-rail swing possible
II. BASIC TECHNIQUES FOR SUPPLY REDUCTION IN CONTINUOUS-TIME ANALOG CIRCUITS IIa. Floating voltage sources: 1) Static (DC level shifters) 2) Dynamic (signal dependent shifters) 3) Switched IIb. Multiple Input Floating gate transistors 1) Conventional 2) Quasi-floating-gate IIc. Flipped voltage followers
IIa: BASIC TECHNIQUES: Supply reduction using DC level shifters +
+
+
Vb
+ A
Vin
Vout
Vin
Vb
Vout
_
(a)
_
A
Vb B
_
I1
I
B
B
_
(b)
A
R
I
(c)
I1+I2 (d)
Fig. IIa1. (a) Conventional cascode current mirror (b) Cascode mirror with reduced supply requirements (c ) Implementations of floating unipolar DC level shifters (d) implementation of floating bipolar DC Level shifter
IIa: BASIC TECHNIQUES: DC Level shifting techniques can be used to reduce the effective threshold voltage of MOS transistors [1] a) Conventional Cascode mirror: Vin=2VGS= 2Vth+2VDSsat; Vout=VGS+VDSsat=Vth+2VDSsat Vtotal=Vin+Vout=3Vth+4Vdsat b) Cascode mirror with DC level shifters Vin=2VTH+2VDSsat-2Vb; Vout=Vth+2VDSsat-Vb Vtotal=3Vth+4VDSsat-3Vb=3VTH’+4VDSsat Where: If
Vth’=Vth-Vb Vb=Vth then Vth’= 0 Then Vtotal= 4VDSsat (
Jaime Ramírez Angulo New Mexico State University, Las Cruces, NM
Some techniques for low-voltage operation of continuous-time analog CMOS circuits The drastic reduction in the supply voltages of CMOS VLSI systems driven by technological as well as power reduction constraints has forced analog designers to divert from conventional analog circuit architectures which become non functional in a reduced supply environment and look for new techniques for low voltage, high performance operation of analog CMOS circuits. In this presentation a family of high performance low-voltage analog CMOS circuits is introduced. These are based on the utilization of static, dynamic and switched floating voltage sources. These circuits operate in all cases with a single supply voltage close to a transistor's threshold voltage.Among the circuits discussed in this presentation we include: one and two stage class AB op-amps, rectifiers, filters, transconductors, analog multipliers, etc. Presented by Jaime Ramirez-Angulo, professor of Electrical Engineering , IEEE fellow and director of the VLSI lab at the Klipsch School of Electrical and Computer Engineering at New Mexico State University in Las Cruces, New Mexico (USA). He received a degree in Communications and Electronic Engineering (Professional degree), a M.S.E.E from the National Polytechnic Institute in Mexico City (1973 and 1976 respectively) and a Dr.-Ing. degree from the University of Stuttgart in Germany in 1982. His research is related to following areas of analog and mixed signal VLSI design: low-voltage CMOS circuit design, test techniques for mixed-signal VSLI systems, continuous-time filters and analog array processors.
OUTLINE I. II.
Introduction Basic techniques for continuous-time lowvoltage operation III. Continuous-time low-voltage amplifier schemes IV. Low-voltage op-amp architectures with rail-torail input and output swings V. Low-voltage circuits based on floating gates VI. Conclusions
I. INTRODUCTION: Why low-voltage? Within the next few years most mixed-signal systems will require operation with sub-volt supply voltages (VDD2Vth+VDSsat+Vbat
To minimize Vdd requirements: Inputs must operate close to lower rail at approximately constant voltage (Vinswing=0)
Rail-to-rail swing possible
II. BASIC TECHNIQUES FOR SUPPLY REDUCTION IN CONTINUOUS-TIME ANALOG CIRCUITS IIa. Floating voltage sources: 1) Static (DC level shifters) 2) Dynamic (signal dependent shifters) 3) Switched IIb. Multiple Input Floating gate transistors 1) Conventional 2) Quasi-floating-gate IIc. Flipped voltage followers
IIa: BASIC TECHNIQUES: Supply reduction using DC level shifters +
+
+
Vb
+ A
Vin
Vout
Vin
Vb
Vout
_
(a)
_
A
Vb B
_
I1
I
B
B
_
(b)
A
R
I
(c)
I1+I2 (d)
Fig. IIa1. (a) Conventional cascode current mirror (b) Cascode mirror with reduced supply requirements (c ) Implementations of floating unipolar DC level shifters (d) implementation of floating bipolar DC Level shifter
IIa: BASIC TECHNIQUES: DC Level shifting techniques can be used to reduce the effective threshold voltage of MOS transistors [1] a) Conventional Cascode mirror: Vin=2VGS= 2Vth+2VDSsat; Vout=VGS+VDSsat=Vth+2VDSsat Vtotal=Vin+Vout=3Vth+4Vdsat b) Cascode mirror with DC level shifters Vin=2VTH+2VDSsat-2Vb; Vout=Vth+2VDSsat-Vb Vtotal=3Vth+4VDSsat-3Vb=3VTH’+4VDSsat Where: If
Vth’=Vth-Vb Vb=Vth then Vth’= 0 Then Vtotal= 4VDSsat (
