Through package vias - Semantic Scholar
First Demonstration of a Surface Mountable, Ultra-Thin Glass BGA Package for Smart Mobile Logic Devices Venky Sundaram*, Yoichiro Sato^, Toshitake Seki+, Yutaka Takagi+, Vanessa Smet, Makoto Kobayashi#, and Rao Tummala 3D Systems Packaging Research Center, Georgia Institute of Technology, Atlanta, GA 30332, USA ^Asahi Glass Company, Yokohama, Japan + NGK Spark Plug Co. Ltd., Aichi Prefecture, Japan # Namics Corporation, Niigata, Japan *[email protected] Abstract This paper presents the first demonstration of an ultra-thin glass BGA package that is assembled on to mother board with standard SMT technology. Such a package has many new advances that include ultra-thin glass, high speed through via hole formation and copper metallization, double-side RDL wiring with advanced 3 micron ground rules, and Cu-SnAg microbump assembly of a 10mm silicon test die. Glass, as a package, overcomes the shortcomings of organic packages in bump pitch, CTE mismatch to Si and warpage and silicon interposers in electrical performance and cost. Glass packages are being developed to manufacture both as wafers for improved performance over Si and as panels to improve bump pitch over organic packages. Glass, therefore, is not just a high performance and low volume technology, like silicon interposers, but a pervasive package technology with lower cost, higher performance and thinner than silicon and organic packages. Glass has compelling benefits in thickness and I/O pitch reduction and reliability for one of the highest volume applications, namely, the packaging of high I/O logic devices for smart mobile systems. This paper represents a paradigm shift in ultra-thin packages using large glass panels for future smart mobile and high performance devices, and the first demonstration of 100um thin glass packages with 50-80um chip-level I/O pitch and 18mm x 18mm body size surface mount assembly at 400um pitch. Introduction Glass packaging started at Georgia Tech and many other R&D groups as a lower cost and higher performance alternative to silicon interposers, due to the low loss and large panel availability of ultra-thin glass [1]. The Georgia Tech team began to demonstrate such an interposer with its industry partners addressing major barriers that include the handling of large, ultra-thin glass panels, forming large number of ultrasmall through vias at small pitch, metallization of these small copper vias without defects and with good adhesion, forming 2-5 micron RDL wiring layers with bump pitch at 20-50 microns, assembly of chips to these brittle substrates, and improving its thermal conductivity. It became clear that glass can be a pervasive platform technology that is both a high performance and very low cost technology. As the glass packaging technology matures and is applied to high volume applications, it should be at the same or lower cost than organic packaging. Glass simplifies the material manufacturing compared to laminates, since FR-4 or low CTE laminates require four different materials and process technologies such as glass fiber, glass and ceramic fillers,
978-1-4799-2407-3/14/$31.00 ©2014 IEEE
epoxy, flame retardant and all these put together to form the 5th material that is called core or prepreg. In the case of glass, it is one material and one process and is ultra-thin to start with, driven by touch displays. Glass also reduces the processing cost per package since it can be scaled to much larger manufacturing panels or roll to roll than FR-4, driven by its superior dimensional stability and higher modulus. Glass is a high temperature material, resistant to moisture and is available in many compositions with many CTEs, from below Si CTE to above GaAs CTE. Glass is seen, therefore, not just as a high performance interposer technology, but as a pervasive low cost platform packaging technology that is suitable for packaging all devices that are packaged currently that include single chip logic and memory packaging, MEMS & Sensors Packaging, RF, Power & Analog Packaging. In addition, it is applicable and is being developed for packaging of 2.5D multichip packaging with ultra-high number of interconnections between chips in sideby-side configuration. Ultimately, it is being developed as a superior alternative to 3D ICs, but without TSVs, in what is called 3D interposers and packages. Other applications that are being explored include 3D IPDs for passives on both sides of ultra-thin glass, and 3DIPAC for ultra-thin passives and actives on both sides with shortest distance between actives and passives. The specific applications for 3D IPACs include cell phone cameras, RF and power modules, 3D optoelectronics replacing electronic TSVs with Photonics. This paper focuses on one of the highest volume applications, namely, the packaging of high I/O logic devices for smart mobile systems. A schematic of the glass BGA package that can be SMT attached to FR-4 motherboard, is shown in Figure 1. IC
180 um
Glass BGA
PWB
Figure 1. Glass BGA Package for Smart Mobile Application Processors Previously, the authors have reported individual building block technologies such as through via hole formation, metallization and reliability, electrical characterization of
365
2014 Electronic Components & Technology Conference
glass substrates and initial board-level assembly and reliability [1, 2]. This paper, for the first time, integrates all the glass package building blocks into the first thin glass BGA package demonstration. The second section describes some of the building block technology advances in glass packaging. The third section presents the first glass substrate process or record (POR) with a full process flow, materials and tools. The fourth section presents the first demonstration of a mobile glass BGA package including test vehicle design, glass substrate fabrication, chip and board level assembly. The fifth section analyzes the warpage and thermal behavior of glass BGA packages and the final section summarizes the research. Glass Package Building Block Technologies Initial advances in through package vias (TPV) and redistribution layers (RDL) on glass have been previously reported [2]. This section describes the latest advances in TPV, RDL and glass assembly. Through Package Vias (TPV) in Ultra-Thin Glass: The single biggest barrier to the use of glass as an interposer and package is its brittleness, resulting in cracking of glass during via hole formation of small diameter TPVs at small pitch. Addressing this barrier requires overcoming a number of fundamental challenges including handling of thin glass, defect-free via hole formation, and low-stress conductive via metallization at high speed. The glass interposer starts with ultra-thin glass (30-180µm) enabled by innovations in fusion draw and float glass formation technologies in defect-free panels and wafers. Thinner glass, not only enables the formation of ultra-small TPVs having TSV-like dimensions (
978-1-4799-2407-3/14/$31.00 ©2014 IEEE
epoxy, flame retardant and all these put together to form the 5th material that is called core or prepreg. In the case of glass, it is one material and one process and is ultra-thin to start with, driven by touch displays. Glass also reduces the processing cost per package since it can be scaled to much larger manufacturing panels or roll to roll than FR-4, driven by its superior dimensional stability and higher modulus. Glass is a high temperature material, resistant to moisture and is available in many compositions with many CTEs, from below Si CTE to above GaAs CTE. Glass is seen, therefore, not just as a high performance interposer technology, but as a pervasive low cost platform packaging technology that is suitable for packaging all devices that are packaged currently that include single chip logic and memory packaging, MEMS & Sensors Packaging, RF, Power & Analog Packaging. In addition, it is applicable and is being developed for packaging of 2.5D multichip packaging with ultra-high number of interconnections between chips in sideby-side configuration. Ultimately, it is being developed as a superior alternative to 3D ICs, but without TSVs, in what is called 3D interposers and packages. Other applications that are being explored include 3D IPDs for passives on both sides of ultra-thin glass, and 3DIPAC for ultra-thin passives and actives on both sides with shortest distance between actives and passives. The specific applications for 3D IPACs include cell phone cameras, RF and power modules, 3D optoelectronics replacing electronic TSVs with Photonics. This paper focuses on one of the highest volume applications, namely, the packaging of high I/O logic devices for smart mobile systems. A schematic of the glass BGA package that can be SMT attached to FR-4 motherboard, is shown in Figure 1. IC
180 um
Glass BGA
PWB
Figure 1. Glass BGA Package for Smart Mobile Application Processors Previously, the authors have reported individual building block technologies such as through via hole formation, metallization and reliability, electrical characterization of
365
2014 Electronic Components & Technology Conference
glass substrates and initial board-level assembly and reliability [1, 2]. This paper, for the first time, integrates all the glass package building blocks into the first thin glass BGA package demonstration. The second section describes some of the building block technology advances in glass packaging. The third section presents the first glass substrate process or record (POR) with a full process flow, materials and tools. The fourth section presents the first demonstration of a mobile glass BGA package including test vehicle design, glass substrate fabrication, chip and board level assembly. The fifth section analyzes the warpage and thermal behavior of glass BGA packages and the final section summarizes the research. Glass Package Building Block Technologies Initial advances in through package vias (TPV) and redistribution layers (RDL) on glass have been previously reported [2]. This section describes the latest advances in TPV, RDL and glass assembly. Through Package Vias (TPV) in Ultra-Thin Glass: The single biggest barrier to the use of glass as an interposer and package is its brittleness, resulting in cracking of glass during via hole formation of small diameter TPVs at small pitch. Addressing this barrier requires overcoming a number of fundamental challenges including handling of thin glass, defect-free via hole formation, and low-stress conductive via metallization at high speed. The glass interposer starts with ultra-thin glass (30-180µm) enabled by innovations in fusion draw and float glass formation technologies in defect-free panels and wafers. Thinner glass, not only enables the formation of ultra-small TPVs having TSV-like dimensions (
