Two-Stage Feedforward Class-AB CMOS OTA for Low-Voltage
IEICE TRANS. ELECTRON., VOL.E90–C, NO.12 DECEMBER 2007
2293
LETTER
Two-Stage Feedforward Class-AB CMOS OTA for Low-Voltage Filtering Applications Phanumas KHUMSAT†a) , Nonmember and Apisak WORAPISHET†† , Member
SUMMARY A compact OTA suitable for low-voltage active-RC and MOSFET-C filters is presented. The input stage of the OTA utilises the NMOS pseudo-differential amplifier with PMOS active load. The output stage relies upon the dual-mode feed-forward class-AB technique (based on an inverter-type transconductor) with common-mode rejection capability that incurs no penalty on transconductance/bias-current efficiency. Simulation results of a 0.5-V 100-kHz 5th-order Chebyshev filter based on the proposed OTA in a 0.18 µm CMOS process indicate SNR and SFDR of 68 dB and 63 dB (at 50 kHz + 55 kHz) respectively. The filter consumes total power consumption of 60 µW. key words: operational transconductance amplifier, OTA, active-RC filters, MOSFET-C filters, feedforward
1.
Introduction
The active-RC and MOSFET-C filter design technique has portrayed itself as a simple and effective method for integrating high complexity continuous-time filters on a single CMOS chip with large dynamic range and accurate frequency response, especially for low-voltage design [1]–[4]. An operational transconductance amplifier (OTA) with a sufficiently large transconductance, can be employed as an active building block of the filter. With the push towards low supply voltages in modern fine-line CMOS processes, extensive research efforts have been witnessed on novel lowvoltage OTA structures [4], [5]. This letter introduces a compact two-stage OTA that features a low-voltage class AB output stage with common-mode rejection relying on a dual feedforward technique. The structure and operation of the OTA is described and analysed. This is followed by performance verification via simulation of a 5th-order Chebyshev filter operating under a 0.5-V supply voltage utilising MOS devices with a nominal threshold voltage of 0.45 V. 2.
Operational Transconductance Amplifier
Figure 1 shows the proposed balanced OTA where its input stage utilises a pseudo-differential amplifier (N1–N2) with gates biased at VG via resistors RG [4], [6]. Also, to promote very low supply voltage requirement, saturated moderate to Manuscript received June 19, 2007. Manuscript revised August 18, 2007. † The author is with the Department of Electrical Engineering, Faculty of Engineering, Prince of Songkla University, Songkhla, Thailand 90112. †† The author is with Mahanakorn Microelectronic Research Centre, Mahanakorn University of Technology, Bangkok, Thailand. a) E-mail: [email protected] DOI: 10.1093/ietele/e90–c.12.2293
weak inversion operation similar to the pseudo-differential input pair in [4] should be adopted for N1–N2 where their quiescent gate-source voltage is set at below their threshold voltage. The output differential current signals from N1–N2 is injected into high impedance realized by a cross-coupling network P1–P4. Note that the bodies of P1, P2 are tied to VBP2 (different from the bodies of P3–P8 which are tied to VBP1 ) where the voltage level can be generated from a Schmitt-trigger-based oscillator to attain the possible maximum dc gain without instability problem [4]. A proper transistor sizing can be set so that a quiescent voltage at drains of P1–P4 is equal to VDD /2 without additional common-mode feedback amplifier (CMFB). The OTA’s output stage is constructed from four pairs of class-AB linear inverter-type transconductor N3–N6, P5– P8 [7] incorporating with a feedforward concept for both differential-mode and common-mode signals. Such structure can be easily explained by a conceptual block diagram in Fig. 2(a). Each gm block (Fig. 2(b)) evenly contributes to the total differential transconductance Gm diff (i+o − i−o )/(v+o − v−o ) = 2gm while at the same time rendering an ideal zero common-mode transconductance Gm cm = 0, i.e. a perfect common-mode rejection, which helps ensure common-mode stability for the entire filter without employing a CMFB amplifier. In contrast to the topology in [8] (as also employed for OTA in [4]), it can be seen that both differential-mode and common-mode signals are fedforward and this maintains a high transconductance/power efficiency because every gm block does contribute to the overall transconductance gain. The input voltage signals are inversed simply by the circuit in Fig. 2(c), alternatively the NMOS version is also applicable as long as the technology allows body and source terminals to be tied together. From Fig. 1, the OTA’s small signal transconductance gain can be found for a differential signal gmi gmv gmp +gmn 1+ (1) Gm diff = gmy −gmx + sC x gmv + sCv and a common-mode signal gmi gmv gmp +gmn 1− Gm cm = gmy +gmx + sC x gmv + sCv
(2)
where gmi , gmx , gmy , gmp and gmn are transconductances of N1–N2, P1–P2, P3–P4, N3–N6, and P5–P8. The parameter gmv is a transconductance of the signal inverting transistors P9–P12. C x is a total capacitance (referred to ground) at
c 2007 The Institute of Electronics, Information and Communication Engineers Copyright
IEICE TRANS. ELECTRON., VOL.E90–C, NO.12 DECEMBER 2007
2294
Fig. 1
Proposed two-stage OTA with a feedforward output stage.
(a) Conceptual block diagram
(b) Inverter-type class-AB transconductor [7]
possess sufficient bandwidth (i.e. large gmv /Cv ) for proper operation of the OTA. The quiescent DC voltage at the output can be set without employing any CMFB amplifier. It fully exploits the fact that in typical MOSFET-C or active-RC filter structures (ladder-based, cascaded etc.), there are always interconnections between the output and input terminals of the same or different OTA stages through triode-biased MOSFET or linear resistors R. Following this, since the input DC voltage of the proposed OTA of Fig. 1 is set at a well-defined voltage VG , the output DC voltage for each of the OTA’s is automatically set at the same VG , if the filter resistors R carry infinitesimal DC currents as of typical cases. To allow optimal signal voltage swing, the OTA’s input and output terminals are normally set at VG = VDD /2. From the aforementioned discussion and analysis, although operating under a low-voltage supply, the active-RC filters utilizing the proposed OTA structure can still render a good common-mode rejection without employing a powerhungry CMFB amplifier. The OTA’s class-AB output structure also allows the filters to possess a large output voltage swing and help maximize the signal-to-noise ratio as well as the dynamic range. 3.
(c) Voltage-signal inverter Fig. 2 Differential-mode/common-mode feedforward technique employed at the output of the proposed OTA.
drains of N1, N2 and Cv is a total capacitance at the signal inversion nodes (drains of P9, P10). The last terms of (1) and (2) signify importance of signal inversion circuitries to
Simulation Results
By employing the OTA of Fig. 1, a 5th-order 100 kHz Chebyshev active-RC filter (Fig. 3) was simulated with Spectre using a 0.18 µm CMOS process (VT N = 0.46 V, VT P = −0.45 V for body bias at VBN = VBP1 = VBP2 = 0.25 V). The transistor dimensions and design parameter values are as shown in Table 1 for VDD = 0.5 V and only two resistance values of 100 kΩ and 200 kΩ have been used for the filter resistors. Note that all the transistors inside the OTA operate in weak inversion region. Figure 4 shows the frequency responses of the filter for differential-mode (with a closed-up passband response) and common-mode signals displaying a good degree of
LETTER
2295
Fig. 3 Table 1
Active-RC 5th-order Chebyshev filter schematic.
Filter’s design parameters for VDD = 0.5 V.
Fig. 5
Fig. 4
Simulated SFDR over input frequency.
Fifth-order Chebyshev filter frequency response.
common-mode suppression. For the intended applications at 0.5-V, the filter exhibits the differential peak output of 0.31 V at less than 1% THD for the single-tone test ranging from 10 kHz to 90 kHz. For the simulated integrated output noise at 7.5×10−9 V 2 , this renders the signal-to-noise ratio (SNR) of 68 dB. Under the two-tone test at 50 kHz and 55 kHz, the spurious-free dynamic range (SFDR) is at 63 dB. The filter’s SFDR was also simulated at different two-tone inputs (from 10 kHz and 15 kHz up to 90 kHz and 95 kHz) and the SFDR was found to be within the range of 55 dB to 65 dB (Fig. 5). The whole filter consumes 120 µA. The practicality of the cross-coupled PMOS P1–P4 was also confirmed by Monte-Carlo simulation where the standard deviation of both gate and drain voltages of N1– N6, due to mismatches of P1–P4, is within 5% of their de-
Fig. 6 Voltages of OTAs’ outputs within the filter responded to a supply step change (from 0 V to 0.5 V).
Table 2
Summarised simulated filter performance.
IEICE TRANS. ELECTRON., VOL.E90–C, NO.12 DECEMBER 2007
2296
sired quiescent values. Also, the filter shows no sign of instability when it is subjected to a rail-to-rail surge of the supply voltage (Fig. 6). The filter performances are summarised in Table 2. Note that the filter frequency tuning to compensate for process or temperature variation can be achieved by utilising low-voltage resistive tuning [9] or capacitive tuning [4] techniques. 4.
Conclusion
A compact OTA suitable for low voltage active-RC filter implementations has been developed. The circuit relies primarily on the feed-forward class AB output stage that features low supply operation and common-mode rejection at no cost to transconductance/bias-current efficiency. In contrast to a conventional design, the proposed dual feedforward technique allows high common-mode rejection without employing a common-mode feedback amplifier. It thus helps minimise power consumption and still assures filter’s common-mode stability. Moreover, a large signal swing can be achieved owing to the OTA’s class-AB output stage. Verified through extensive simulation, it was demonstrated that a low supply voltage filter with a competitive performance at small complexity is entirely viable with the use of the proposed OTA structure. Acknowledgments This work is financially supported by National Science and Technology Development Agency (NSTDA) and Commis-
sion on Higher Education (CHE), Thailand. The authors would like to thank J. Mahattanakul for sharing his views on common-mode stability issues. References [1] M. Banu and Y. Tsividis, “The MOSFET-C technique: Designing power efficient, high frequency filter,” in Design of high frequency integrated analogue filters, ed. Y. Sun, Chapter 2, IEE, UK, 2002. [2] M. Banu and Y.P. Tsividis, “An elliptic continuous-time CMOS filter with on-chip automatic tuning,” IEEE J. Solid-State Circuits, vol.SC-20, no.6, pp.1114–1121, Dec. 1985. [3] A. Yoshizawa and Y. Tsividis, “A channel-select filter with agile blocker detection and adaptive power dissipation,” IEEE J. SolidState Circuits, vol.42, no.5, pp.1090–1099, May 2007. [4] S. Chatterjee, Y. Tsividis, and P. Kinget, “0.5-V analog circuit techniques and their application in OTA and filter design,” IEEE J. SolidState Circuits, vol.40, no.12, pp.2373–2387, Dec. 2005. [5] A.J. L´opez, S. Baswa, J. Ramirez-Angulo, and R. Gonz´alez, “Lowvoltage super class AB CMOS OTA cells with very high slew rate and power efficiency,” IEEE J. Solid-State Circuits, vol.40, no.5, pp.1068–1077, May 2005. [6] S. Karthikeyan, S. Mortezapour, A. Tammineedi, and E.K.F. Lee, “Low-voltage analog circuit design based on biased inverting opamp configuration,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol.47, no.3, pp.176–184, March 2000. [7] B. Nauta and E. Seevinck, “Linear CMOS transconductance element for VHF filters,” Electron. Lett., vol.25, pp.448–450, March 1989. [8] A. Baschirotto, F. Rezzi, and R. Castello, “Low-voltage balanced transconductor with high input common-mode rejection,” Electron. Lett., vol.30, no.20, pp.1669–1671, Sept. 1994. [9] A. Worapishet and P. Khumsat, “Sub-threshold R-MOSFET tunable resistor technique,” Electron. Lett., vol.43, no.7, pp.390–392, March 2007.
2293
LETTER
Two-Stage Feedforward Class-AB CMOS OTA for Low-Voltage Filtering Applications Phanumas KHUMSAT†a) , Nonmember and Apisak WORAPISHET†† , Member
SUMMARY A compact OTA suitable for low-voltage active-RC and MOSFET-C filters is presented. The input stage of the OTA utilises the NMOS pseudo-differential amplifier with PMOS active load. The output stage relies upon the dual-mode feed-forward class-AB technique (based on an inverter-type transconductor) with common-mode rejection capability that incurs no penalty on transconductance/bias-current efficiency. Simulation results of a 0.5-V 100-kHz 5th-order Chebyshev filter based on the proposed OTA in a 0.18 µm CMOS process indicate SNR and SFDR of 68 dB and 63 dB (at 50 kHz + 55 kHz) respectively. The filter consumes total power consumption of 60 µW. key words: operational transconductance amplifier, OTA, active-RC filters, MOSFET-C filters, feedforward
1.
Introduction
The active-RC and MOSFET-C filter design technique has portrayed itself as a simple and effective method for integrating high complexity continuous-time filters on a single CMOS chip with large dynamic range and accurate frequency response, especially for low-voltage design [1]–[4]. An operational transconductance amplifier (OTA) with a sufficiently large transconductance, can be employed as an active building block of the filter. With the push towards low supply voltages in modern fine-line CMOS processes, extensive research efforts have been witnessed on novel lowvoltage OTA structures [4], [5]. This letter introduces a compact two-stage OTA that features a low-voltage class AB output stage with common-mode rejection relying on a dual feedforward technique. The structure and operation of the OTA is described and analysed. This is followed by performance verification via simulation of a 5th-order Chebyshev filter operating under a 0.5-V supply voltage utilising MOS devices with a nominal threshold voltage of 0.45 V. 2.
Operational Transconductance Amplifier
Figure 1 shows the proposed balanced OTA where its input stage utilises a pseudo-differential amplifier (N1–N2) with gates biased at VG via resistors RG [4], [6]. Also, to promote very low supply voltage requirement, saturated moderate to Manuscript received June 19, 2007. Manuscript revised August 18, 2007. † The author is with the Department of Electrical Engineering, Faculty of Engineering, Prince of Songkla University, Songkhla, Thailand 90112. †† The author is with Mahanakorn Microelectronic Research Centre, Mahanakorn University of Technology, Bangkok, Thailand. a) E-mail: [email protected] DOI: 10.1093/ietele/e90–c.12.2293
weak inversion operation similar to the pseudo-differential input pair in [4] should be adopted for N1–N2 where their quiescent gate-source voltage is set at below their threshold voltage. The output differential current signals from N1–N2 is injected into high impedance realized by a cross-coupling network P1–P4. Note that the bodies of P1, P2 are tied to VBP2 (different from the bodies of P3–P8 which are tied to VBP1 ) where the voltage level can be generated from a Schmitt-trigger-based oscillator to attain the possible maximum dc gain without instability problem [4]. A proper transistor sizing can be set so that a quiescent voltage at drains of P1–P4 is equal to VDD /2 without additional common-mode feedback amplifier (CMFB). The OTA’s output stage is constructed from four pairs of class-AB linear inverter-type transconductor N3–N6, P5– P8 [7] incorporating with a feedforward concept for both differential-mode and common-mode signals. Such structure can be easily explained by a conceptual block diagram in Fig. 2(a). Each gm block (Fig. 2(b)) evenly contributes to the total differential transconductance Gm diff (i+o − i−o )/(v+o − v−o ) = 2gm while at the same time rendering an ideal zero common-mode transconductance Gm cm = 0, i.e. a perfect common-mode rejection, which helps ensure common-mode stability for the entire filter without employing a CMFB amplifier. In contrast to the topology in [8] (as also employed for OTA in [4]), it can be seen that both differential-mode and common-mode signals are fedforward and this maintains a high transconductance/power efficiency because every gm block does contribute to the overall transconductance gain. The input voltage signals are inversed simply by the circuit in Fig. 2(c), alternatively the NMOS version is also applicable as long as the technology allows body and source terminals to be tied together. From Fig. 1, the OTA’s small signal transconductance gain can be found for a differential signal gmi gmv gmp +gmn 1+ (1) Gm diff = gmy −gmx + sC x gmv + sCv and a common-mode signal gmi gmv gmp +gmn 1− Gm cm = gmy +gmx + sC x gmv + sCv
(2)
where gmi , gmx , gmy , gmp and gmn are transconductances of N1–N2, P1–P2, P3–P4, N3–N6, and P5–P8. The parameter gmv is a transconductance of the signal inverting transistors P9–P12. C x is a total capacitance (referred to ground) at
c 2007 The Institute of Electronics, Information and Communication Engineers Copyright
IEICE TRANS. ELECTRON., VOL.E90–C, NO.12 DECEMBER 2007
2294
Fig. 1
Proposed two-stage OTA with a feedforward output stage.
(a) Conceptual block diagram
(b) Inverter-type class-AB transconductor [7]
possess sufficient bandwidth (i.e. large gmv /Cv ) for proper operation of the OTA. The quiescent DC voltage at the output can be set without employing any CMFB amplifier. It fully exploits the fact that in typical MOSFET-C or active-RC filter structures (ladder-based, cascaded etc.), there are always interconnections between the output and input terminals of the same or different OTA stages through triode-biased MOSFET or linear resistors R. Following this, since the input DC voltage of the proposed OTA of Fig. 1 is set at a well-defined voltage VG , the output DC voltage for each of the OTA’s is automatically set at the same VG , if the filter resistors R carry infinitesimal DC currents as of typical cases. To allow optimal signal voltage swing, the OTA’s input and output terminals are normally set at VG = VDD /2. From the aforementioned discussion and analysis, although operating under a low-voltage supply, the active-RC filters utilizing the proposed OTA structure can still render a good common-mode rejection without employing a powerhungry CMFB amplifier. The OTA’s class-AB output structure also allows the filters to possess a large output voltage swing and help maximize the signal-to-noise ratio as well as the dynamic range. 3.
(c) Voltage-signal inverter Fig. 2 Differential-mode/common-mode feedforward technique employed at the output of the proposed OTA.
drains of N1, N2 and Cv is a total capacitance at the signal inversion nodes (drains of P9, P10). The last terms of (1) and (2) signify importance of signal inversion circuitries to
Simulation Results
By employing the OTA of Fig. 1, a 5th-order 100 kHz Chebyshev active-RC filter (Fig. 3) was simulated with Spectre using a 0.18 µm CMOS process (VT N = 0.46 V, VT P = −0.45 V for body bias at VBN = VBP1 = VBP2 = 0.25 V). The transistor dimensions and design parameter values are as shown in Table 1 for VDD = 0.5 V and only two resistance values of 100 kΩ and 200 kΩ have been used for the filter resistors. Note that all the transistors inside the OTA operate in weak inversion region. Figure 4 shows the frequency responses of the filter for differential-mode (with a closed-up passband response) and common-mode signals displaying a good degree of
LETTER
2295
Fig. 3 Table 1
Active-RC 5th-order Chebyshev filter schematic.
Filter’s design parameters for VDD = 0.5 V.
Fig. 5
Fig. 4
Simulated SFDR over input frequency.
Fifth-order Chebyshev filter frequency response.
common-mode suppression. For the intended applications at 0.5-V, the filter exhibits the differential peak output of 0.31 V at less than 1% THD for the single-tone test ranging from 10 kHz to 90 kHz. For the simulated integrated output noise at 7.5×10−9 V 2 , this renders the signal-to-noise ratio (SNR) of 68 dB. Under the two-tone test at 50 kHz and 55 kHz, the spurious-free dynamic range (SFDR) is at 63 dB. The filter’s SFDR was also simulated at different two-tone inputs (from 10 kHz and 15 kHz up to 90 kHz and 95 kHz) and the SFDR was found to be within the range of 55 dB to 65 dB (Fig. 5). The whole filter consumes 120 µA. The practicality of the cross-coupled PMOS P1–P4 was also confirmed by Monte-Carlo simulation where the standard deviation of both gate and drain voltages of N1– N6, due to mismatches of P1–P4, is within 5% of their de-
Fig. 6 Voltages of OTAs’ outputs within the filter responded to a supply step change (from 0 V to 0.5 V).
Table 2
Summarised simulated filter performance.
IEICE TRANS. ELECTRON., VOL.E90–C, NO.12 DECEMBER 2007
2296
sired quiescent values. Also, the filter shows no sign of instability when it is subjected to a rail-to-rail surge of the supply voltage (Fig. 6). The filter performances are summarised in Table 2. Note that the filter frequency tuning to compensate for process or temperature variation can be achieved by utilising low-voltage resistive tuning [9] or capacitive tuning [4] techniques. 4.
Conclusion
A compact OTA suitable for low voltage active-RC filter implementations has been developed. The circuit relies primarily on the feed-forward class AB output stage that features low supply operation and common-mode rejection at no cost to transconductance/bias-current efficiency. In contrast to a conventional design, the proposed dual feedforward technique allows high common-mode rejection without employing a common-mode feedback amplifier. It thus helps minimise power consumption and still assures filter’s common-mode stability. Moreover, a large signal swing can be achieved owing to the OTA’s class-AB output stage. Verified through extensive simulation, it was demonstrated that a low supply voltage filter with a competitive performance at small complexity is entirely viable with the use of the proposed OTA structure. Acknowledgments This work is financially supported by National Science and Technology Development Agency (NSTDA) and Commis-
sion on Higher Education (CHE), Thailand. The authors would like to thank J. Mahattanakul for sharing his views on common-mode stability issues. References [1] M. Banu and Y. Tsividis, “The MOSFET-C technique: Designing power efficient, high frequency filter,” in Design of high frequency integrated analogue filters, ed. Y. Sun, Chapter 2, IEE, UK, 2002. [2] M. Banu and Y.P. Tsividis, “An elliptic continuous-time CMOS filter with on-chip automatic tuning,” IEEE J. Solid-State Circuits, vol.SC-20, no.6, pp.1114–1121, Dec. 1985. [3] A. Yoshizawa and Y. Tsividis, “A channel-select filter with agile blocker detection and adaptive power dissipation,” IEEE J. SolidState Circuits, vol.42, no.5, pp.1090–1099, May 2007. [4] S. Chatterjee, Y. Tsividis, and P. Kinget, “0.5-V analog circuit techniques and their application in OTA and filter design,” IEEE J. SolidState Circuits, vol.40, no.12, pp.2373–2387, Dec. 2005. [5] A.J. L´opez, S. Baswa, J. Ramirez-Angulo, and R. Gonz´alez, “Lowvoltage super class AB CMOS OTA cells with very high slew rate and power efficiency,” IEEE J. Solid-State Circuits, vol.40, no.5, pp.1068–1077, May 2005. [6] S. Karthikeyan, S. Mortezapour, A. Tammineedi, and E.K.F. Lee, “Low-voltage analog circuit design based on biased inverting opamp configuration,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol.47, no.3, pp.176–184, March 2000. [7] B. Nauta and E. Seevinck, “Linear CMOS transconductance element for VHF filters,” Electron. Lett., vol.25, pp.448–450, March 1989. [8] A. Baschirotto, F. Rezzi, and R. Castello, “Low-voltage balanced transconductor with high input common-mode rejection,” Electron. Lett., vol.30, no.20, pp.1669–1671, Sept. 1994. [9] A. Worapishet and P. Khumsat, “Sub-threshold R-MOSFET tunable resistor technique,” Electron. Lett., vol.43, no.7, pp.390–392, March 2007.
