A fully parallel CMOS analog median filter - Circuits and ... - IEEE Xplore
ISCAS 2000 - IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland
A FULLY PARALLEL CMOS ANALOG MEDIAN FILTER AIejandro Diaz-Sanchez
('1,
Jaime Ramirez-Angulo (I), Antonio Lopez" and Edgar Sanchez-Sinencio (j).
Klipsch School of Electrical and Computer Engineering. N e w Mexico State University. Area de Teoria de Sefiales y Comunicaciones. Universidad Publica de Navarra. (3) Department of Electrical Engineering. Texas A&M University.
(I)
(2)
ABSTRACT A fully integrated CMOS implementation of a continuous-time
analog median filter is presented. The array median filter uses two compact analog circuits as building blocks to implement the variable delay and median detection. Median detectors are based on transconductance comparators to speed their time response, while the time delay is implemented using all-pass filters. Both circuits allow modular expansion for the implementation of large sized median filter array processors. In addition, a fast novel technique for parallel image processing is presented. It is shown that an image of 91 x 81 pixels is processed in less than 30 pS using an array of high-speed analog processors. Experimental results of a test chip prototype in 2 pn CMOS technology MOSIS process are presented.
1. INTRODUCTION Median filtering is a widely used nonlinear operation in image and speech processing [I]. It is mainly used to remove impulsive and high frequency noise while preserving sharp edges. The median of a sequence of data is denoted by med(X) and it is defined as the data which have the same number of data with greater values as the number of data with lesser values [2]. Despite their popularity, digital implementations of real-time median filters are computationally expensive, because they need to perform a sorting operation for each pixel to compute the median [3]. Since each data must be compared to the others, the circuitry needed to perform the median of a set of data is highly complex and very silicon area intensive for highspeed applications. Digital implementations of median filters are also limited to sequences with odd number of elements. Recent research in high-speed analog implementations of median filters has been based on the use of bipolar [6] and MOS transistors [4-51. For MOS implementations, the low transconductance gain of the MOS transistor produces a smooth comer effect in the nonlinear transfer function of the median circuit. Some reported implementations have used feedback configurations to overcome this problem [5-81, but the real-time parallel image processing applications remains unsolved. This paper presents a novel CMOS implementation of a highly parallel median filter whose main characteristic is the continuous-time parallel processing of the signal. The presented implementation takes images by column of data and, in combination with previous columns of data delayed using continuous-time analog delays, computes the median of the image using a 3 by 3 neighborhood. The presented median filter uses the principle of balanced saturation described by Lee [9], with the novelty of using saturation in current instead voltage to speed the response. The filter has two basic and compact cells: a) continuous-time analog delay elements based on all-pass circuits and b) median detector circuits using high gain transconductance comparators. Both are designed to operate at high frequency and using only NMOS and PMOS '
transistors. The analog delay element has a range from 8011s to 200ns, using bias currents that can be varied between 4 0 a to SOM. Median filter detectors are not limited to odd number of data, computing the even and odd cases. A 3 x 3 median filter cell has been implemented that occupies 352 pm x 389 pn in a 2 p n CMOS process. Experimental results of a test chip prototype of the basic cells are presented. Simulation results of an 80 X 91 image processing, using 89 median filter parallel cells are shown.
2. MEDIAN FILTER BUILDING BLOCKS Figure 1 shows a block diagram of the implemented median filter. The input signal is brought into a delay line, which allows the filter to access previous values of the input. The delay line is implemented using all-pass circuits described in section 2.1. Section 2.2 describes the transconductance comparators that will be used to build the median circuit detector.
2.1. The analog delay cell For the implementation of the analog delay an all-pass circuit is used. Figure 2.a shows the concept, while figure 2.b the implemented analog voltage delay cell. Description of the circuit operation follows. The input voltage applied to transistor M2 produces complementary signal currents it= -iz = i through the current mirrors M3-M5 and M4-M6: 11
=L+i
...(1.a) .(1.b)
For small signal analysis, neglecting the A effects, the currents are given by: i, = -gm
Vin = - i 2
...(2)
where gm is the small signal transconductance gain of a differential pair MOS transistors MI-M2. Selecting (W/L)MT.M~ = 2 (W/L)M4-M6,
where C is the capacitor shown in Fig. 2.b The signal current through MI 1 is given by: iout= i, + i, = = i, + -2
0-7803-5482-6/99/$10.0002000 IEEE
11-593
s-gmlC
s+gmlc gmVin
,..(4.a)
...(4.b)
"O%"hZ
If we chose (W/L)M12,M13
gmIC . S i g m l C ~=
=
(WL) MI,MZ, then the output voltage
is given by:
at the output of the OTA's with the middle values, while Vinmed+l/Zand Vinmd.,/Z the corresponding input values, we have that the zero current conditions will be only satisfied if:
vo s - g m / C =vi=s+gm/C
...(5.a)
~ ~ ~ ~ ) = - 2 (t wa ~n/ .g 'm )
...(5.b)
H(s)
IOmed+l,2 = -IOmed-l,Z
...(8)
In terms of voltages, this can be described as: 5(w) = -2
gm/c
...(5.c)
GIW (Vout - Vmecil/z ) =GW (Vmeci+l/2-Vout)
wL+(gm/qL which represents a first order all-pass transfer function. For the example presented, the NMOS transistors of the differential pairs have dimensions W/L=6cun/3p and the current mirror PMOS transistors have W / L = l b p / 3 p . C = 2 pF and all current sources are I b = 40 M, and implemented with low voltage current mirrors that have dimensions W / L = 2 4 p / 2 p . Experimental results of the delay line for a sinusoidal signal of 500 kHz is shown in figure 3, with 100 nS delayed signal.
2.b. Transconductance comparator Fig. 4 shows a high gain two-stage transconductance comparator circuit. It uses two differential pairs to obtain high gain (>1000) so that it has a gain comparable to a bipolar stage. The first differential pair (MI-M4), is connected as a voltage amplifier with gain:
...(9)
and output voltage will be given by:
Therefore, the arithmetic mean of the input voltages of the OTA,s with the middle values will be at the output of the median filter in the even case. Figure 6 shows the experimental performance of a fabricated test chip prototype including a three input median circuit. Observe that the inputs: sinusoidal, square and triangular yield the median value at all times. The window used as basic cell for the image median filter is a 3 by 3 array of high gain OTA's. Bias currents were set to 60 PA, while power supplies were f 2.5 V.
4. THE COLUMN PROCESSOR ARRAY with a voltage gain A0 of about 50V/V, while the second differential pair (M5-M6) is connected as a transconductance amplifier with a transconductance gm6. Since the second stage saturates in current with I,,, = *Ib, its response to input voltage changes occurs faster than previously reported applications [681. The total transconductance gain of the overall OTA is given by:
As opposed to a voltage mode implementation, the transconductance OTA saturates in current, as is shown in the transfer characteristic at figure 5. Simulations have shown a rising time of 2 nS and a settling time of 4nS. A small hysteresis can be also noticed.
3. THE MEDIAN CIRCUIT The median circuit detector shown in Figure 7 uses a high gain two-stage transconductance comparator (presented in 2.b) per data. During circuit operation, the output current of the OTA's which input data is above the median will saturate in a positive way, driving a saturation current I,: into the node V,,,. Meanwhile, in the OTA's which input data is below the median, the output current will go into negative saturation current Since the number of data below the median is the same as the data above the median, the sum of their currents at the output will equal to zero for V,,, = Vinmed,which is the input voltage corresponding to the median of the data set. For any median filter with odd number of inputs, the output voltage will follow the input of the OTA which input is the median of the data set, trying to set its output current to zero. For median filters with even number of inputs, the two OTA's with the middle values will try to maintain the sum of the current at the are the currents output equal to zero. So, if Io,,~+ID and IO,~~.UZ
In order to avoid the redundant operation during median filtering, the circuit was designed to be used as a column signal processor. The information is processed by taking columns of the data into analog median circuits, thus allowing to process more than a pixel simultaneously without increasing the complexity. The time required for processing is only the analog delay of the circuit, and the continuous-time characteristic of the design discards any synchronization requirements. A block diagram of a column processor is shown in figure 7. Figure 8 shows how the median filtering parallel process is performed. Its operation is described as follows: the filter mask @I receives three lines of information corresponding to the same number of rows of the image to be processed. Using a synchronized pixel input into the delay line, the data corresponding to the times f k d 2 ,t,_,and t k of the lines n + 2 , n + l a n d n are processed into the median data M( t k - , ,n + l ), as shows figure 8.a. Meanwhile, mask filter @z takes n+l , n and n-1 , and are processed into the median data M ( t k - * , n ) . Similar procedure is performed by filter mask @3. Therefore we have an array of analog median filters working in a parallel median process. At the next synchronized inputs, the new center value will be at time t, , with row vector output M(t,) as shows figure 8.b, and t , with column vector output M(tk+,) as shown in figure 8.c.
That process can be repeated as many times as the image number of columns. That will give us an output pixel matrix A of size NC x NR, where NC is the number of columns of the image, and NR, the number of rows, which also is the number of median analog basic cells. Therefore, the required time to process an image will be equal to NC times the analog delay. Simulated processing of an image of 80 by 91 pixels corrupted with 15% salt and pepper noise was used to test the median filter. The original image is shown in Figure 9.a, while Figure 9.b shows the corrupted image. The image was processed taking 80 rows of 91 data each one. All the columns were taken
11-594
at the input as continuous-time signals, and processed in parallel. The time required to compute the median of the entire image is approximately 30 ps. Despite mean square error is greater than the filtered image obtained using MatlabO (5.2% and 4.1% respectively), the edge error is reduced. Figure 9.c shows the reconstructed analog median filter output, where the preservation of the pixel distribution characteristic of the image can be perceived.
Sanchez-Sinencio, “A Fully Parallel Analog Median Filter,“Proceedings of the 5th IEEE Int. Conference on Electronics, Circuits and Systems, Lisboa, Portugal, September 7-10, 1998, pp. 381-384. [9] Median Filters for Real-Time Signal Processing,” IEEE Transactions on Circuit and Systems, Pt:II, CASII-40,
5. CONCLUSIONS A true continuous-time analog median filter is presented. It was implemented using two novel and compact circuit building blocks that were designed to be used in a modular fashion. The median circuit proposed is very compact compared with previously reported applications [6-81. That compactness of the design allows the implementation of highly parallel analog image processors. An additional advantage over those application is the current saturation characteristic of the median circuit, which grants a linear size increasing when more data were required. The information is processed taking rows of the data, allowing the use of more than one filter at a time without increasing the complexity. The required time for image processing is only the analog delay of the circuit. On the other hand, the continuoustime characteristic of the design discards any synchronization requirements. Since the median filter presented is analog, A/D and D/A conversions are not necessary. The delay line can be controlled using a single current, thus allowing design quality adjusting mechanisms. The designed blocks can be used for a wide variety of linear and nonlinear applications. Since the filtered output is presented in rows of data, more filter arrays can be used to perform further signal processing.
Figure 1.- Block diagram ofthe median filter.
n
6. REFERENCES.
D.“
I. Pitas and A.N. Venetsanopoulos, Nonlinear Digital Filters: Principles and Applications. Boston, MA: Kluwer Academic Publishers, 1990. B.I. Justusson, “Median filtering: Statistical Properties,” in Two-Dimensional Digital Signal Processing 11, T. S. Huang,Ed. New York, NY: Springer-Verlag, 1981. D. Richards: “ VLSI Median Filters, “ IEEE Transactions on Acoustic, Speech and Signal Processing, vol. 38, no. 2,pp. 145-153, February 1990. P. Dietz and L. Carley, “An AnalogTechnique for Finding the Median,” Proceedings of the IEEE Custom Integrated Circuits Conference, San Diego, CA, May 9-12, 1993, pp. 6.1.1-6.1.4. I. Opris and G. Kovacs, “A High Speed Median Filter, “ IEEE Journal of Solid-state Circuits, vol. 32, no.6, pp, 905-908, June1997. K.T. Lau, E.S. Ng and K.M. Ng, “MOS Circuits for Median Filtering Applications,” IEEE Transactions on Consumer Electronics, vol. 39, no.1, pp. 25-32, Januaryl993. B.D. Liu, C.S. Tsay and C.H. Chen, “Design and Implementation of an Analogue Median Filter for RealTime Processing, “International Journal ofElectronics, vol. 75, no. 2, pp. 289-295, 1993. A. Diaz-Sanchez, J. Ramirez-Angulo, A. Lopez and E.
’-f 0’” I
I
“I,
I
I
(b)
-
Figure 2. Analog delay circuit. a).- Concept. b).- An Implementation.
11-595
Figure 3. - CMOS analog delay input and output signals. Vertical axis is 120 mV/div. Horizontal axis is 200 nS/div Figure 7. - Array of high gain OTA's for a mask of 3 x 3 pixels.
"*A
a
L.
.+' 0, n-1
I
I
0
0
0
0
0
0
0
0
0
0
0
0
0
0
.*I
0
m*3
0
fz& 0,o
0
0
0,o
0
0
. - '0 O 0O 0 O O 0 O0
.-I
I
(a)
0
0
0
0
11 .
t.
t.,
0
@)
VI.
t
Figure 4. - High gain transconductance stage circuit. a). - Intemal structure. b). - Symbol.
t,
1k.I
Figure 8. - Column array median filtering parallel process.
Figure 5.- DC performance of the composite OTA. Axes: Vertical is I O A/div. Horizontal is lV/div.
Figure 6.-Three data median detector performance. Vertical axis200mV/div. Horizontal axis is S/div.
Figure 9. - a). Original image. b). Image corrupted with 15% salt and pepper noise. c). Reconstructed image.
11-596
A FULLY PARALLEL CMOS ANALOG MEDIAN FILTER AIejandro Diaz-Sanchez
('1,
Jaime Ramirez-Angulo (I), Antonio Lopez" and Edgar Sanchez-Sinencio (j).
Klipsch School of Electrical and Computer Engineering. N e w Mexico State University. Area de Teoria de Sefiales y Comunicaciones. Universidad Publica de Navarra. (3) Department of Electrical Engineering. Texas A&M University.
(I)
(2)
ABSTRACT A fully integrated CMOS implementation of a continuous-time
analog median filter is presented. The array median filter uses two compact analog circuits as building blocks to implement the variable delay and median detection. Median detectors are based on transconductance comparators to speed their time response, while the time delay is implemented using all-pass filters. Both circuits allow modular expansion for the implementation of large sized median filter array processors. In addition, a fast novel technique for parallel image processing is presented. It is shown that an image of 91 x 81 pixels is processed in less than 30 pS using an array of high-speed analog processors. Experimental results of a test chip prototype in 2 pn CMOS technology MOSIS process are presented.
1. INTRODUCTION Median filtering is a widely used nonlinear operation in image and speech processing [I]. It is mainly used to remove impulsive and high frequency noise while preserving sharp edges. The median of a sequence of data is denoted by med(X) and it is defined as the data which have the same number of data with greater values as the number of data with lesser values [2]. Despite their popularity, digital implementations of real-time median filters are computationally expensive, because they need to perform a sorting operation for each pixel to compute the median [3]. Since each data must be compared to the others, the circuitry needed to perform the median of a set of data is highly complex and very silicon area intensive for highspeed applications. Digital implementations of median filters are also limited to sequences with odd number of elements. Recent research in high-speed analog implementations of median filters has been based on the use of bipolar [6] and MOS transistors [4-51. For MOS implementations, the low transconductance gain of the MOS transistor produces a smooth comer effect in the nonlinear transfer function of the median circuit. Some reported implementations have used feedback configurations to overcome this problem [5-81, but the real-time parallel image processing applications remains unsolved. This paper presents a novel CMOS implementation of a highly parallel median filter whose main characteristic is the continuous-time parallel processing of the signal. The presented implementation takes images by column of data and, in combination with previous columns of data delayed using continuous-time analog delays, computes the median of the image using a 3 by 3 neighborhood. The presented median filter uses the principle of balanced saturation described by Lee [9], with the novelty of using saturation in current instead voltage to speed the response. The filter has two basic and compact cells: a) continuous-time analog delay elements based on all-pass circuits and b) median detector circuits using high gain transconductance comparators. Both are designed to operate at high frequency and using only NMOS and PMOS '
transistors. The analog delay element has a range from 8011s to 200ns, using bias currents that can be varied between 4 0 a to SOM. Median filter detectors are not limited to odd number of data, computing the even and odd cases. A 3 x 3 median filter cell has been implemented that occupies 352 pm x 389 pn in a 2 p n CMOS process. Experimental results of a test chip prototype of the basic cells are presented. Simulation results of an 80 X 91 image processing, using 89 median filter parallel cells are shown.
2. MEDIAN FILTER BUILDING BLOCKS Figure 1 shows a block diagram of the implemented median filter. The input signal is brought into a delay line, which allows the filter to access previous values of the input. The delay line is implemented using all-pass circuits described in section 2.1. Section 2.2 describes the transconductance comparators that will be used to build the median circuit detector.
2.1. The analog delay cell For the implementation of the analog delay an all-pass circuit is used. Figure 2.a shows the concept, while figure 2.b the implemented analog voltage delay cell. Description of the circuit operation follows. The input voltage applied to transistor M2 produces complementary signal currents it= -iz = i through the current mirrors M3-M5 and M4-M6: 11
=L+i
...(1.a) .(1.b)
For small signal analysis, neglecting the A effects, the currents are given by: i, = -gm
Vin = - i 2
...(2)
where gm is the small signal transconductance gain of a differential pair MOS transistors MI-M2. Selecting (W/L)MT.M~ = 2 (W/L)M4-M6,
where C is the capacitor shown in Fig. 2.b The signal current through MI 1 is given by: iout= i, + i, = = i, + -2
0-7803-5482-6/99/$10.0002000 IEEE
11-593
s-gmlC
s+gmlc gmVin
,..(4.a)
...(4.b)
"O%"hZ
If we chose (W/L)M12,M13
gmIC . S i g m l C ~=
=
(WL) MI,MZ, then the output voltage
is given by:
at the output of the OTA's with the middle values, while Vinmed+l/Zand Vinmd.,/Z the corresponding input values, we have that the zero current conditions will be only satisfied if:
vo s - g m / C =vi=s+gm/C
...(5.a)
~ ~ ~ ~ ) = - 2 (t wa ~n/ .g 'm )
...(5.b)
H(s)
IOmed+l,2 = -IOmed-l,Z
...(8)
In terms of voltages, this can be described as: 5(w) = -2
gm/c
...(5.c)
GIW (Vout - Vmecil/z ) =GW (Vmeci+l/2-Vout)
wL+(gm/qL which represents a first order all-pass transfer function. For the example presented, the NMOS transistors of the differential pairs have dimensions W/L=6cun/3p and the current mirror PMOS transistors have W / L = l b p / 3 p . C = 2 pF and all current sources are I b = 40 M, and implemented with low voltage current mirrors that have dimensions W / L = 2 4 p / 2 p . Experimental results of the delay line for a sinusoidal signal of 500 kHz is shown in figure 3, with 100 nS delayed signal.
2.b. Transconductance comparator Fig. 4 shows a high gain two-stage transconductance comparator circuit. It uses two differential pairs to obtain high gain (>1000) so that it has a gain comparable to a bipolar stage. The first differential pair (MI-M4), is connected as a voltage amplifier with gain:
...(9)
and output voltage will be given by:
Therefore, the arithmetic mean of the input voltages of the OTA,s with the middle values will be at the output of the median filter in the even case. Figure 6 shows the experimental performance of a fabricated test chip prototype including a three input median circuit. Observe that the inputs: sinusoidal, square and triangular yield the median value at all times. The window used as basic cell for the image median filter is a 3 by 3 array of high gain OTA's. Bias currents were set to 60 PA, while power supplies were f 2.5 V.
4. THE COLUMN PROCESSOR ARRAY with a voltage gain A0 of about 50V/V, while the second differential pair (M5-M6) is connected as a transconductance amplifier with a transconductance gm6. Since the second stage saturates in current with I,,, = *Ib, its response to input voltage changes occurs faster than previously reported applications [681. The total transconductance gain of the overall OTA is given by:
As opposed to a voltage mode implementation, the transconductance OTA saturates in current, as is shown in the transfer characteristic at figure 5. Simulations have shown a rising time of 2 nS and a settling time of 4nS. A small hysteresis can be also noticed.
3. THE MEDIAN CIRCUIT The median circuit detector shown in Figure 7 uses a high gain two-stage transconductance comparator (presented in 2.b) per data. During circuit operation, the output current of the OTA's which input data is above the median will saturate in a positive way, driving a saturation current I,: into the node V,,,. Meanwhile, in the OTA's which input data is below the median, the output current will go into negative saturation current Since the number of data below the median is the same as the data above the median, the sum of their currents at the output will equal to zero for V,,, = Vinmed,which is the input voltage corresponding to the median of the data set. For any median filter with odd number of inputs, the output voltage will follow the input of the OTA which input is the median of the data set, trying to set its output current to zero. For median filters with even number of inputs, the two OTA's with the middle values will try to maintain the sum of the current at the are the currents output equal to zero. So, if Io,,~+ID and IO,~~.UZ
In order to avoid the redundant operation during median filtering, the circuit was designed to be used as a column signal processor. The information is processed by taking columns of the data into analog median circuits, thus allowing to process more than a pixel simultaneously without increasing the complexity. The time required for processing is only the analog delay of the circuit, and the continuous-time characteristic of the design discards any synchronization requirements. A block diagram of a column processor is shown in figure 7. Figure 8 shows how the median filtering parallel process is performed. Its operation is described as follows: the filter mask @I receives three lines of information corresponding to the same number of rows of the image to be processed. Using a synchronized pixel input into the delay line, the data corresponding to the times f k d 2 ,t,_,and t k of the lines n + 2 , n + l a n d n are processed into the median data M( t k - , ,n + l ), as shows figure 8.a. Meanwhile, mask filter @z takes n+l , n and n-1 , and are processed into the median data M ( t k - * , n ) . Similar procedure is performed by filter mask @3. Therefore we have an array of analog median filters working in a parallel median process. At the next synchronized inputs, the new center value will be at time t, , with row vector output M(t,) as shows figure 8.b, and t , with column vector output M(tk+,) as shown in figure 8.c.
That process can be repeated as many times as the image number of columns. That will give us an output pixel matrix A of size NC x NR, where NC is the number of columns of the image, and NR, the number of rows, which also is the number of median analog basic cells. Therefore, the required time to process an image will be equal to NC times the analog delay. Simulated processing of an image of 80 by 91 pixels corrupted with 15% salt and pepper noise was used to test the median filter. The original image is shown in Figure 9.a, while Figure 9.b shows the corrupted image. The image was processed taking 80 rows of 91 data each one. All the columns were taken
11-594
at the input as continuous-time signals, and processed in parallel. The time required to compute the median of the entire image is approximately 30 ps. Despite mean square error is greater than the filtered image obtained using MatlabO (5.2% and 4.1% respectively), the edge error is reduced. Figure 9.c shows the reconstructed analog median filter output, where the preservation of the pixel distribution characteristic of the image can be perceived.
Sanchez-Sinencio, “A Fully Parallel Analog Median Filter,“Proceedings of the 5th IEEE Int. Conference on Electronics, Circuits and Systems, Lisboa, Portugal, September 7-10, 1998, pp. 381-384. [9] Median Filters for Real-Time Signal Processing,” IEEE Transactions on Circuit and Systems, Pt:II, CASII-40,
5. CONCLUSIONS A true continuous-time analog median filter is presented. It was implemented using two novel and compact circuit building blocks that were designed to be used in a modular fashion. The median circuit proposed is very compact compared with previously reported applications [6-81. That compactness of the design allows the implementation of highly parallel analog image processors. An additional advantage over those application is the current saturation characteristic of the median circuit, which grants a linear size increasing when more data were required. The information is processed taking rows of the data, allowing the use of more than one filter at a time without increasing the complexity. The required time for image processing is only the analog delay of the circuit. On the other hand, the continuoustime characteristic of the design discards any synchronization requirements. Since the median filter presented is analog, A/D and D/A conversions are not necessary. The delay line can be controlled using a single current, thus allowing design quality adjusting mechanisms. The designed blocks can be used for a wide variety of linear and nonlinear applications. Since the filtered output is presented in rows of data, more filter arrays can be used to perform further signal processing.
Figure 1.- Block diagram ofthe median filter.
n
6. REFERENCES.
D.“
I. Pitas and A.N. Venetsanopoulos, Nonlinear Digital Filters: Principles and Applications. Boston, MA: Kluwer Academic Publishers, 1990. B.I. Justusson, “Median filtering: Statistical Properties,” in Two-Dimensional Digital Signal Processing 11, T. S. Huang,Ed. New York, NY: Springer-Verlag, 1981. D. Richards: “ VLSI Median Filters, “ IEEE Transactions on Acoustic, Speech and Signal Processing, vol. 38, no. 2,pp. 145-153, February 1990. P. Dietz and L. Carley, “An AnalogTechnique for Finding the Median,” Proceedings of the IEEE Custom Integrated Circuits Conference, San Diego, CA, May 9-12, 1993, pp. 6.1.1-6.1.4. I. Opris and G. Kovacs, “A High Speed Median Filter, “ IEEE Journal of Solid-state Circuits, vol. 32, no.6, pp, 905-908, June1997. K.T. Lau, E.S. Ng and K.M. Ng, “MOS Circuits for Median Filtering Applications,” IEEE Transactions on Consumer Electronics, vol. 39, no.1, pp. 25-32, Januaryl993. B.D. Liu, C.S. Tsay and C.H. Chen, “Design and Implementation of an Analogue Median Filter for RealTime Processing, “International Journal ofElectronics, vol. 75, no. 2, pp. 289-295, 1993. A. Diaz-Sanchez, J. Ramirez-Angulo, A. Lopez and E.
’-f 0’” I
I
“I,
I
I
(b)
-
Figure 2. Analog delay circuit. a).- Concept. b).- An Implementation.
11-595
Figure 3. - CMOS analog delay input and output signals. Vertical axis is 120 mV/div. Horizontal axis is 200 nS/div Figure 7. - Array of high gain OTA's for a mask of 3 x 3 pixels.
"*A
a
L.
.+' 0, n-1
I
I
0
0
0
0
0
0
0
0
0
0
0
0
0
0
.*I
0
m*3
0
fz& 0,o
0
0
0,o
0
0
. - '0 O 0O 0 O O 0 O0
.-I
I
(a)
0
0
0
0
11 .
t.
t.,
0
@)
VI.
t
Figure 4. - High gain transconductance stage circuit. a). - Intemal structure. b). - Symbol.
t,
1k.I
Figure 8. - Column array median filtering parallel process.
Figure 5.- DC performance of the composite OTA. Axes: Vertical is I O A/div. Horizontal is lV/div.
Figure 6.-Three data median detector performance. Vertical axis200mV/div. Horizontal axis is S/div.
Figure 9. - a). Original image. b). Image corrupted with 15% salt and pepper noise. c). Reconstructed image.
11-596
