A European ISM Band Power Amplifier Module - Semantic Scholar
A European ISM Band Power Amplifier Module Ming-ta Hsieh, Jonghae Kim and Ramesh Harjani Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455, USA
Abstract PA
S1
In this paper we present a power amplifier module suitable for the 433MHz European ISM band frequency. The PA module provides a maximum 30dBm output level at 433MHz. The included power control circuit provides 30dB of dynamic range control. The overall module was designed on a single test board with a 4.8V supply voltage. The maximum output power deviation is less than 1dB over the complete control range. Measurements for two tone tests (with a 100kHz offset) show that the measured intermodulation products are -35dBc for a -35dBm input power level. Four different variations of our basic design have been implemented. They differ in the types of directional coupler used and the types of power control circuit used. All designs use directional couplers with an envelope detector for the power control feedback circuit, which offers accurate power detection, high linearity and stable output power. The inherent simplicity of the new design makes it useful for many applications. At the highest output power level, the measured power efficiency of the PA module is 40 %. 1
Introduction
Power amplifiers are critical components in wireless systems. They consume a substantial percentage of the total power and precise control of the output power level has significant impact on system performance. In this paper we describe a power amplifier (PA) module with power control where we are able to control the output power level extremely accurately. The design for the overall circuit module is inherently simple. In particular, though the current circuit implementation is in discrete form, the ultimate goal is to integrate the power amplifier module with the rest of the system on a single IC. It is essential to maintain a high level of linearity in the PA so that intermodulation products have limited impact on system performance. For example, for our example design the intermodulation productions are required to be at least -30dBc at a -30dBm input level for two tones that are 100kHz apart. We target a multisensor wireless system application. However, the PA module design is general and can be used in many applications. The targeted system is composed of a number of sensor modules transmitting to a central basestation. Each sensor module amplifies and/or converts the sensor signal which is then transmitted via the power amplifier module to the central basestation. Because the distance from each sensor module to the basestation can vary significantly so does the power level seen at the basestation for each module. For example for the European ISM band (433MHz) [10] a 20dB of power variation is required to maintain a constant power level at the basestation if the distance between the sensor modules and the basestation is varied from 10 meters to 1000 meters.
S2
Interface Circuit
Control Circuit BS
SN
S:Sensor PA :Power amplifier BS : Base station
Figure 1: Block diagram for a wireless multisensor system Wireless multisensor Figure 1 shows a block diagram for a wireless multisensor system. It consists of a numbers of sensors, interface circuit, and power amplifier module. The signals from multiple sensors are multiplexed by the interface circuit and then transmitted via a single power amplifier to one or more basestations (BS). The PA is composed of a control circuit and a multistage power amplifier. The power control level is decided by the distance from the basestation. A lower power level is transmitted if the basestation is closeby and a higher level is transmitted if the basestation is more distant. 2
Power Amplifier Design
S-parameters In RF design, accurate knowledge of scattering parameters (S-parameters) allows for precise design. Unfortunately, these were not available for the power MOSFET (MRF9482T1) used in our circuit [12]. Accurate S-parameters were extracted by designing an appropriate test fixture. The accuracy of the test fixture was verified by using an alternate device whose S-parameters were available from data books. The measured S-parameters for our device were then included in an RF simulator [11] and a single stage of the PA was simulated and experimentally verified. This comparison between measurement and simulations is shown in Figure 2. We note a fairly good match between measurements and simulations which provides some measure of confidence in our simulations for further design. Circuit design The circuit diagram for the proposed power amplifier module is shown in Figure 3. Each module includes a -20dB directional coupler, a smart control circuit, and a four-stage amplifier. A -20dB coupling was selected as a design compromise as it provided sufficient isolation while still providing enough signal for the smart control circuit. Four separate designs based on the same basic theme were implemented and tested. The designs differ in the types of directional coupler used and the type of feedback control circuit used. Each of the amplifier stages uses LDMOS [1, 5] transistors as the active element for the power amplifier because of their inherent linearity [7]. For all four designs the same basic PA design was used. The bias for the first two stages of the PA are con-
Output
20
Isolated
S21(S)
L
Output C
Cc
S21(M)
Cc
L
S11(M)
L
Isolated
Coupled
0
C
t
Input Coupled −10
Directional coupler
S11(S)
Lumped-element directional coupler
S22(M)
−20
S22(S)
Figure 4: Type I and Type II directional couplers
S12(M) −30
30
S12(S) −40
−50
S : Simulation M : Measurement
−60 8 10
9
10
Pout [ dBm ]
RF amplifier [ dB ]
L
Input Lambda/4
10
Frequency [ Hz ]
L4 C3
L6
C6
C13
L8
C5 Directional coupler
C9
C1 M1
M2
M3
0 −10
1.75
1.8
1.85
1.9
1.95
2
2.05
2.1
(a) Vc [ V ] 66
Av[V/V]
VDD
C2
10
−20 1.7
Figure 2: Simulation and measurement results for a single stage of the PA
L1
20
64
62
60
Pout
M4
Pin L3
L2
L5
58 −45
L7
−40
−35
−30
−25
−20
−15
(b) Pin [ dBm ]
Vmid
(a) -
R7
R6
U1
Figure 5: (a) Vc vs. Pout and (b) Pin vs. Av
+
+ U3
-
C12
+ U2 D1
Vmid
C10 R5 U4
-
D2
C11
-
L9
+ U5 C14
+
R8 C13
Vb
Vcp
(b)
Figure 3: PA module circuit schematic trolled by the power control feedback circuit while the bias for the last two stages is held constant. The last two stages of the PA is biased on the edge of class C mode with a constant voltage for power efficiency and stability considerations. The first two stages move from class A to class C mode depending on the output of the power control circuit. The first two stages are biased in class B mode at the midpoint for the largest input dynamic range of approximately 30dB. Directional coupler The Type I directional coupler uses a λ/4 transmission line [8] while the Type II directional coupler uses a lumped-element module. Both couplers are shown in Figure 4. The Type I directional coupler provides slightly higher performance, however, Type II couplers illustrate how a fully integrated version might be implemented. Equations to calculate the component values for Type II couplers are shown in equation 1, where f is the operating frequency, Z0 is the characteristic impedance, and CF is the coupling factor in dB. L=
Z0 , 2π f
C=
1 , 2π f Z0
CF
Cc≈
10( 20 ) 2π f Z0
(1)
Feedback control circuit The two types of control circuits that were used is shown in Figure 3(a) and (b). The first feedback control circuit (Type-C) is setup to provide a constant output power, while the second feedback control circuit (Type-V) is setup to provide controlled but variable output power. In this paper, we limit our detailed discussions to the Type-C feedback control circuit due to space limitations. The first control circuit (Type A), shown in Figure 3(a) fixes the PA output level at a constant output power and can accommodate 30 dB of input dynamic range. The signal that is coupled from the directional coupler is applied to an envelope detector. The average envelope signal is now compared to a reference signal and the difference is amplified by a feedback amplifier. The output voltage of the feedback amplifier is used to control the DC bias level of the first two stages of the power amplifier. An expression for the output power of the overall system can be derived as shown in equation 2, where Pout is the output power, Pin is the input power, A p is the normal gain at midpoint bias, and Vc is the bias voltage for first two stages of the amplifier. Vmid is the nominal bias voltage and the nominal gain factor, k1 =Pout /Vc , is derived from measurements. For our transistors it was measured to be about 126.16 dBm/V as shown in Figure 5(a). Vmid is set to be 1.9V, and results in A p = 40dB, which lets the amplifier operate in class B mode in order to obtain the maximum input dynamic range while allowing the first two stages of the the PA to change operation from class A to class C mode. Pout = Pin + A p + (Vc −Vmid )k1 (2) The DC bias voltage Vc can be shown to be given by equation 3. Where Av is the feedback voltage amplifier gain , k3 is the envelope detector conversion factor and k2 is the coupling factor of the directional coupler. The energy fed into the envelope detector
is given by Pin (detector)=Pout -k2 in dBm. Equation 3, therefore, simply converts the input power level into the voltage level. The conversion factor (K3 ) between the input power and output voltage of the envelope detector was measured to have a value of 0.306. Equation 4 was derived by substituting equation 3 into equation 2 and rearranging the various terms. 10
Pout −k2 10
(3)
One of our goals is to set the optimal gain Av for the feedback amplifier. This is possible because we know k1 , k2 , k3 , A p , and want to maintain a constant Pout . Equation 4 provides a relation between Pin and the necessary Av as shown in Figure 5(b). The optimal gain level is located at the midpoint of the input power level. If the term Pout -A p +Vmid k1 in equation 4 is much larger than Pin then Av is nearly constant for all Pin levels. Hence as the number of bias controlled amplifier stages is increases, the effective gain factor, k1 , will increase, which further reduces the variation in Av . (Pout − A p +Vmid k1 ) 1 − Pout −APpin+Vmid k1 (4) Av = Pout −k2 k1 k3 10 10 The Type-V feedback control circuit, shown in Figure 3(b), provides both variable and constant output levels. This control circuit consists of an envelope detector followed by a comparator and an average detector. The overall transfer function for Pin to Pout with this control block still follows the primary expression shown in equation 2. For this circuit to function properly the comparator must have a bandwidth that is larger than the corner frequency of the envelope detector. The output of the envelope detector is applied to the non-inverting input of the comparator which sets the expected output power level. The time constant of the average detector determines the settling time of overall system. The power control methodologies developed here can be extended to other amplifier classes as well [6]. Here we control a two stage class B amplifier for its simplicity. 3
D-Coupler
IN
Experimental Results
All four implementations were designed and fabricated. For all designs printed circuit boards with a permittivity of 4.5 was used. All of the measurements were performed with the input signal at 433MHz [10] which is one of the European ISM frequency bands. All measurements were done using a HP 8753D network analyzer. Experiment 1: This circuit is for a fixed power level (i.e., TypeC feedback control) and uses a Type II directional coupler. The complete assembled circuit is shown in Figure 6. This circuit is designed to have a maximum output power of 30dBm. The feedback loop is designed to maintain the output power level at 10dBm even when the input power varies between -15dBm to -45dBm. The system is also designed to have a maximum power gain of 55dB at the lowest input signal level. Figure 7 shows the measured power efficiency of the PA module. There are three regions depending on the power level. The high power region operates at PL3 mode and its efficiency is around 25 to 45 percent and the medium power region at PL2 mode has around 10 to 25 percent. The lower power region operates at PL1 mode and its efficiency is under 10 percent. Experimental results for the input dynamic range versus the output power variation is shown in Figure 8(a). The results in this
OUT Control Circuit Figure 6: Photograph of an example PA module 45
PL3( High Power )
40
35
PL2( Medium Power )
30
Efficiency [ % ]
Vc = Av k3
PA
25
20
PL3( Low Power ) 15
10
5
0 10
VDD = 4.8V Frequency = 450MHz 12
14
16
18
20
22
24
26
28
30
Pout [ dBm ]
Figure 7: Measured power efficiency figure shows that the deviation of output power from the midpoint is less than ±0.5dB. The measured output power deviation matches fairly well with predictions made using equation 4. Experimental results for compression (1dB compression point, P1dB [9]) characteristics is shown in Figure 8(b). The measured input and output 1dB compression points [4, 9] are -21dBm and 28dBm respectively. The linearity for the power module without the feedback loop is measured by the intercept point of the two-tone test [2, 3, 9]. This measurement represents the degree of signal corruption caused by the third inter-modulation of two nearby interferers. Two inband tones separated by 100kHz is applied to the input of the power module through a power combiner. The experimental results for the input (IIP3) and output (OIP3) third order intercept points (IP3) are -10dBm and 41dBm respectively. In Figure 9 we show the output power variation as a function of supply voltage with and without the feedback network. For this experiment the supply voltage is varied between 4 and 5 volts. Measurement results for three different input levels are shown. It is clear that the output power is significantly stabilized using our power control circuitry. Figure 10 shows power gain (S21) measurement results. The measured power gain is about 37dB at 450MHz. The power gain has a bandpass characteristic due to input, output and interstage matching networks. In Figure 11 we show the measured output at the power amplifier at a 30dBm level. Here we note it is relatively free of har-
Ripple [ dB ]
0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −45
−40
−35
−30
−25
−20
−15
(a) Pin [ dBm ] Pout [ dBm ]
60
3rd order intercept point 40 20
1st order
0 −20
3rd order
−40 −40
−35
−30
−25
−20
−15
−10
−5
0
Figure 10: Power gain of the PA module
(b) Pin [ dBm ] Figure 8: (a) Pin vs. Ripple and (b) IP3 20
18
Pin = −25dBm with control circuit 16
Pout [ dBm ]
14
12
Pin = −30dBm with control circuit
10
8
Pin = −30dBm without control circuit
6
Figure 11: Power amplifier gain and harmonics
4
2
0
Pin = −35dBm with control circuit 4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5
VDD [ V ] Figure 9: VDD versus Pout
ponents for Integrated RF Power Amplifiers”, IEEE Electron device letters,vol.21,No.2, Feb. 2000. [2] Bo Shi, and Lars Sundstr, “Linearization of RF Amplifiers Using Power Feedback”, IEEE Vehicular Technology Conference,vol.2, 1999. [3] S. Tankaka et al., “A Linearization Technique for CMOS RF Power Amplifiers”, Symposium on VLSI Circuit 1997.
monics. This is primarily due to the filtering effects of the various matching networks.
[4] Behzad Razavi “RF Microelectronics”, Prentice Hall,New Jersey, 1998.
4
[5] Gordon Ma et al., “High efficiency submicron gate LDMOS power FET for low voltage wireless communications”, IEEE MTT-S International Microwave Symposium, V.3, 1997.
Conclusions
In this paper we have demonstrated a power amplifier module based on LDMOS transistors. The design operates at the European ISM band of 433MHz. Two simple power control loops were used to obtain a 30dB input dynamic range from -15dBm to -45dBm of input power with a constant output power at 10dBm. The inherent simplicity of the feedback circuitry makes the design particularly suitable for the low cost multi-wireless sensors and monolithic integrated circuit design. For future designs the power efficiency could be dramatically improved by operating the power module either in class E or class F. References [1] Yun Tan, Mahender Kumar, Johnny K.O Sin, Jun Cai, and Jack Lau, “A LDMOS Technology Compatible with CMOS and Passive Com-
[6] Herbert Zirath, David Rutledge, “LDMOS VHF Class E power amplifier using a high Q novel variable ind uctor”, IEEE Mtt-S International Microwave Symposium,V.1 1999. [7] Christopher P. Dragon, Wayne R. Burger, Bob Davidson, Enver Krvavac, Nagaraj Dixit, and Dale Joersz, “High Power RF-LDMOS Transistors for Base Station Applications”, RF Design Magazine, March 2000. [8] Peter Vizmulle, “RF Design Guide-Systems, Circuits, and Equations”, Artech House ,Boston, 1995. [9] Steve C. Cripps, “RF Power Amplifiers for Wireless Communication”, Artech House, Boston,1999. [10] The radio government of United Kingdom, “Short Range DevicesInformation Sheet”, http://www.radio.gov.uk. [11] TINA Pro http://www.tina.com [12] MRF9482T1 Silicon Lateral FET N-Channel Enhancement-Mode MOSFET Motorola Data Sheet 1998
Abstract PA
S1
In this paper we present a power amplifier module suitable for the 433MHz European ISM band frequency. The PA module provides a maximum 30dBm output level at 433MHz. The included power control circuit provides 30dB of dynamic range control. The overall module was designed on a single test board with a 4.8V supply voltage. The maximum output power deviation is less than 1dB over the complete control range. Measurements for two tone tests (with a 100kHz offset) show that the measured intermodulation products are -35dBc for a -35dBm input power level. Four different variations of our basic design have been implemented. They differ in the types of directional coupler used and the types of power control circuit used. All designs use directional couplers with an envelope detector for the power control feedback circuit, which offers accurate power detection, high linearity and stable output power. The inherent simplicity of the new design makes it useful for many applications. At the highest output power level, the measured power efficiency of the PA module is 40 %. 1
Introduction
Power amplifiers are critical components in wireless systems. They consume a substantial percentage of the total power and precise control of the output power level has significant impact on system performance. In this paper we describe a power amplifier (PA) module with power control where we are able to control the output power level extremely accurately. The design for the overall circuit module is inherently simple. In particular, though the current circuit implementation is in discrete form, the ultimate goal is to integrate the power amplifier module with the rest of the system on a single IC. It is essential to maintain a high level of linearity in the PA so that intermodulation products have limited impact on system performance. For example, for our example design the intermodulation productions are required to be at least -30dBc at a -30dBm input level for two tones that are 100kHz apart. We target a multisensor wireless system application. However, the PA module design is general and can be used in many applications. The targeted system is composed of a number of sensor modules transmitting to a central basestation. Each sensor module amplifies and/or converts the sensor signal which is then transmitted via the power amplifier module to the central basestation. Because the distance from each sensor module to the basestation can vary significantly so does the power level seen at the basestation for each module. For example for the European ISM band (433MHz) [10] a 20dB of power variation is required to maintain a constant power level at the basestation if the distance between the sensor modules and the basestation is varied from 10 meters to 1000 meters.
S2
Interface Circuit
Control Circuit BS
SN
S:Sensor PA :Power amplifier BS : Base station
Figure 1: Block diagram for a wireless multisensor system Wireless multisensor Figure 1 shows a block diagram for a wireless multisensor system. It consists of a numbers of sensors, interface circuit, and power amplifier module. The signals from multiple sensors are multiplexed by the interface circuit and then transmitted via a single power amplifier to one or more basestations (BS). The PA is composed of a control circuit and a multistage power amplifier. The power control level is decided by the distance from the basestation. A lower power level is transmitted if the basestation is closeby and a higher level is transmitted if the basestation is more distant. 2
Power Amplifier Design
S-parameters In RF design, accurate knowledge of scattering parameters (S-parameters) allows for precise design. Unfortunately, these were not available for the power MOSFET (MRF9482T1) used in our circuit [12]. Accurate S-parameters were extracted by designing an appropriate test fixture. The accuracy of the test fixture was verified by using an alternate device whose S-parameters were available from data books. The measured S-parameters for our device were then included in an RF simulator [11] and a single stage of the PA was simulated and experimentally verified. This comparison between measurement and simulations is shown in Figure 2. We note a fairly good match between measurements and simulations which provides some measure of confidence in our simulations for further design. Circuit design The circuit diagram for the proposed power amplifier module is shown in Figure 3. Each module includes a -20dB directional coupler, a smart control circuit, and a four-stage amplifier. A -20dB coupling was selected as a design compromise as it provided sufficient isolation while still providing enough signal for the smart control circuit. Four separate designs based on the same basic theme were implemented and tested. The designs differ in the types of directional coupler used and the type of feedback control circuit used. Each of the amplifier stages uses LDMOS [1, 5] transistors as the active element for the power amplifier because of their inherent linearity [7]. For all four designs the same basic PA design was used. The bias for the first two stages of the PA are con-
Output
20
Isolated
S21(S)
L
Output C
Cc
S21(M)
Cc
L
S11(M)
L
Isolated
Coupled
0
C
t
Input Coupled −10
Directional coupler
S11(S)
Lumped-element directional coupler
S22(M)
−20
S22(S)
Figure 4: Type I and Type II directional couplers
S12(M) −30
30
S12(S) −40
−50
S : Simulation M : Measurement
−60 8 10
9
10
Pout [ dBm ]
RF amplifier [ dB ]
L
Input Lambda/4
10
Frequency [ Hz ]
L4 C3
L6
C6
C13
L8
C5 Directional coupler
C9
C1 M1
M2
M3
0 −10
1.75
1.8
1.85
1.9
1.95
2
2.05
2.1
(a) Vc [ V ] 66
Av[V/V]
VDD
C2
10
−20 1.7
Figure 2: Simulation and measurement results for a single stage of the PA
L1
20
64
62
60
Pout
M4
Pin L3
L2
L5
58 −45
L7
−40
−35
−30
−25
−20
−15
(b) Pin [ dBm ]
Vmid
(a) -
R7
R6
U1
Figure 5: (a) Vc vs. Pout and (b) Pin vs. Av
+
+ U3
-
C12
+ U2 D1
Vmid
C10 R5 U4
-
D2
C11
-
L9
+ U5 C14
+
R8 C13
Vb
Vcp
(b)
Figure 3: PA module circuit schematic trolled by the power control feedback circuit while the bias for the last two stages is held constant. The last two stages of the PA is biased on the edge of class C mode with a constant voltage for power efficiency and stability considerations. The first two stages move from class A to class C mode depending on the output of the power control circuit. The first two stages are biased in class B mode at the midpoint for the largest input dynamic range of approximately 30dB. Directional coupler The Type I directional coupler uses a λ/4 transmission line [8] while the Type II directional coupler uses a lumped-element module. Both couplers are shown in Figure 4. The Type I directional coupler provides slightly higher performance, however, Type II couplers illustrate how a fully integrated version might be implemented. Equations to calculate the component values for Type II couplers are shown in equation 1, where f is the operating frequency, Z0 is the characteristic impedance, and CF is the coupling factor in dB. L=
Z0 , 2π f
C=
1 , 2π f Z0
CF
Cc≈
10( 20 ) 2π f Z0
(1)
Feedback control circuit The two types of control circuits that were used is shown in Figure 3(a) and (b). The first feedback control circuit (Type-C) is setup to provide a constant output power, while the second feedback control circuit (Type-V) is setup to provide controlled but variable output power. In this paper, we limit our detailed discussions to the Type-C feedback control circuit due to space limitations. The first control circuit (Type A), shown in Figure 3(a) fixes the PA output level at a constant output power and can accommodate 30 dB of input dynamic range. The signal that is coupled from the directional coupler is applied to an envelope detector. The average envelope signal is now compared to a reference signal and the difference is amplified by a feedback amplifier. The output voltage of the feedback amplifier is used to control the DC bias level of the first two stages of the power amplifier. An expression for the output power of the overall system can be derived as shown in equation 2, where Pout is the output power, Pin is the input power, A p is the normal gain at midpoint bias, and Vc is the bias voltage for first two stages of the amplifier. Vmid is the nominal bias voltage and the nominal gain factor, k1 =Pout /Vc , is derived from measurements. For our transistors it was measured to be about 126.16 dBm/V as shown in Figure 5(a). Vmid is set to be 1.9V, and results in A p = 40dB, which lets the amplifier operate in class B mode in order to obtain the maximum input dynamic range while allowing the first two stages of the the PA to change operation from class A to class C mode. Pout = Pin + A p + (Vc −Vmid )k1 (2) The DC bias voltage Vc can be shown to be given by equation 3. Where Av is the feedback voltage amplifier gain , k3 is the envelope detector conversion factor and k2 is the coupling factor of the directional coupler. The energy fed into the envelope detector
is given by Pin (detector)=Pout -k2 in dBm. Equation 3, therefore, simply converts the input power level into the voltage level. The conversion factor (K3 ) between the input power and output voltage of the envelope detector was measured to have a value of 0.306. Equation 4 was derived by substituting equation 3 into equation 2 and rearranging the various terms. 10
Pout −k2 10
(3)
One of our goals is to set the optimal gain Av for the feedback amplifier. This is possible because we know k1 , k2 , k3 , A p , and want to maintain a constant Pout . Equation 4 provides a relation between Pin and the necessary Av as shown in Figure 5(b). The optimal gain level is located at the midpoint of the input power level. If the term Pout -A p +Vmid k1 in equation 4 is much larger than Pin then Av is nearly constant for all Pin levels. Hence as the number of bias controlled amplifier stages is increases, the effective gain factor, k1 , will increase, which further reduces the variation in Av . (Pout − A p +Vmid k1 ) 1 − Pout −APpin+Vmid k1 (4) Av = Pout −k2 k1 k3 10 10 The Type-V feedback control circuit, shown in Figure 3(b), provides both variable and constant output levels. This control circuit consists of an envelope detector followed by a comparator and an average detector. The overall transfer function for Pin to Pout with this control block still follows the primary expression shown in equation 2. For this circuit to function properly the comparator must have a bandwidth that is larger than the corner frequency of the envelope detector. The output of the envelope detector is applied to the non-inverting input of the comparator which sets the expected output power level. The time constant of the average detector determines the settling time of overall system. The power control methodologies developed here can be extended to other amplifier classes as well [6]. Here we control a two stage class B amplifier for its simplicity. 3
D-Coupler
IN
Experimental Results
All four implementations were designed and fabricated. For all designs printed circuit boards with a permittivity of 4.5 was used. All of the measurements were performed with the input signal at 433MHz [10] which is one of the European ISM frequency bands. All measurements were done using a HP 8753D network analyzer. Experiment 1: This circuit is for a fixed power level (i.e., TypeC feedback control) and uses a Type II directional coupler. The complete assembled circuit is shown in Figure 6. This circuit is designed to have a maximum output power of 30dBm. The feedback loop is designed to maintain the output power level at 10dBm even when the input power varies between -15dBm to -45dBm. The system is also designed to have a maximum power gain of 55dB at the lowest input signal level. Figure 7 shows the measured power efficiency of the PA module. There are three regions depending on the power level. The high power region operates at PL3 mode and its efficiency is around 25 to 45 percent and the medium power region at PL2 mode has around 10 to 25 percent. The lower power region operates at PL1 mode and its efficiency is under 10 percent. Experimental results for the input dynamic range versus the output power variation is shown in Figure 8(a). The results in this
OUT Control Circuit Figure 6: Photograph of an example PA module 45
PL3( High Power )
40
35
PL2( Medium Power )
30
Efficiency [ % ]
Vc = Av k3
PA
25
20
PL3( Low Power ) 15
10
5
0 10
VDD = 4.8V Frequency = 450MHz 12
14
16
18
20
22
24
26
28
30
Pout [ dBm ]
Figure 7: Measured power efficiency figure shows that the deviation of output power from the midpoint is less than ±0.5dB. The measured output power deviation matches fairly well with predictions made using equation 4. Experimental results for compression (1dB compression point, P1dB [9]) characteristics is shown in Figure 8(b). The measured input and output 1dB compression points [4, 9] are -21dBm and 28dBm respectively. The linearity for the power module without the feedback loop is measured by the intercept point of the two-tone test [2, 3, 9]. This measurement represents the degree of signal corruption caused by the third inter-modulation of two nearby interferers. Two inband tones separated by 100kHz is applied to the input of the power module through a power combiner. The experimental results for the input (IIP3) and output (OIP3) third order intercept points (IP3) are -10dBm and 41dBm respectively. In Figure 9 we show the output power variation as a function of supply voltage with and without the feedback network. For this experiment the supply voltage is varied between 4 and 5 volts. Measurement results for three different input levels are shown. It is clear that the output power is significantly stabilized using our power control circuitry. Figure 10 shows power gain (S21) measurement results. The measured power gain is about 37dB at 450MHz. The power gain has a bandpass characteristic due to input, output and interstage matching networks. In Figure 11 we show the measured output at the power amplifier at a 30dBm level. Here we note it is relatively free of har-
Ripple [ dB ]
0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −45
−40
−35
−30
−25
−20
−15
(a) Pin [ dBm ] Pout [ dBm ]
60
3rd order intercept point 40 20
1st order
0 −20
3rd order
−40 −40
−35
−30
−25
−20
−15
−10
−5
0
Figure 10: Power gain of the PA module
(b) Pin [ dBm ] Figure 8: (a) Pin vs. Ripple and (b) IP3 20
18
Pin = −25dBm with control circuit 16
Pout [ dBm ]
14
12
Pin = −30dBm with control circuit
10
8
Pin = −30dBm without control circuit
6
Figure 11: Power amplifier gain and harmonics
4
2
0
Pin = −35dBm with control circuit 4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5
VDD [ V ] Figure 9: VDD versus Pout
ponents for Integrated RF Power Amplifiers”, IEEE Electron device letters,vol.21,No.2, Feb. 2000. [2] Bo Shi, and Lars Sundstr, “Linearization of RF Amplifiers Using Power Feedback”, IEEE Vehicular Technology Conference,vol.2, 1999. [3] S. Tankaka et al., “A Linearization Technique for CMOS RF Power Amplifiers”, Symposium on VLSI Circuit 1997.
monics. This is primarily due to the filtering effects of the various matching networks.
[4] Behzad Razavi “RF Microelectronics”, Prentice Hall,New Jersey, 1998.
4
[5] Gordon Ma et al., “High efficiency submicron gate LDMOS power FET for low voltage wireless communications”, IEEE MTT-S International Microwave Symposium, V.3, 1997.
Conclusions
In this paper we have demonstrated a power amplifier module based on LDMOS transistors. The design operates at the European ISM band of 433MHz. Two simple power control loops were used to obtain a 30dB input dynamic range from -15dBm to -45dBm of input power with a constant output power at 10dBm. The inherent simplicity of the feedback circuitry makes the design particularly suitable for the low cost multi-wireless sensors and monolithic integrated circuit design. For future designs the power efficiency could be dramatically improved by operating the power module either in class E or class F. References [1] Yun Tan, Mahender Kumar, Johnny K.O Sin, Jun Cai, and Jack Lau, “A LDMOS Technology Compatible with CMOS and Passive Com-
[6] Herbert Zirath, David Rutledge, “LDMOS VHF Class E power amplifier using a high Q novel variable ind uctor”, IEEE Mtt-S International Microwave Symposium,V.1 1999. [7] Christopher P. Dragon, Wayne R. Burger, Bob Davidson, Enver Krvavac, Nagaraj Dixit, and Dale Joersz, “High Power RF-LDMOS Transistors for Base Station Applications”, RF Design Magazine, March 2000. [8] Peter Vizmulle, “RF Design Guide-Systems, Circuits, and Equations”, Artech House ,Boston, 1995. [9] Steve C. Cripps, “RF Power Amplifiers for Wireless Communication”, Artech House, Boston,1999. [10] The radio government of United Kingdom, “Short Range DevicesInformation Sheet”, http://www.radio.gov.uk. [11] TINA Pro http://www.tina.com [12] MRF9482T1 Silicon Lateral FET N-Channel Enhancement-Mode MOSFET Motorola Data Sheet 1998
