A low power high speed class-B buffer amplifier for ... - Semantic Scholar
A Low Power High Speed Class-B Buffer Amplifier for Flat Panel Display Application Chih-Wen Lu Department of Electrical Engineering, National Chi Nan University [email protected]
Abstract A low power, high speed, but with a large input dynamic range and output swing class-B output buffer circuit which is suitable for the flat-panel display application is proposed. The buffer draws little current during static but has a large driving capability during transients. It has been demonstrated with the TSMC 0.6µm CMOS technology.
1. Introduction With the evolution of compact, light-weighted, low power and high quality display, there is a big demand of developing the low power consuming, high efficiency, and high-speed buffer circuit. The circuit should occupy a small die area, consume minimal power, have a settling time smaller than the horizontal scanning time, and a capability of offering high current resolution which can accommodate up to 256 gray levels. For a 4 V of full scale, each gray level corresponds to 16 mV [1-4]. Some output buffers were proposed and demonstrated in recent years. For examples, Yu et al [5] proposed a class-B output buffer for flat-panel-display column driver, for which a comparator was used in the negative feedback path to eliminate the quiescent current in the output stage; Lee et al [6] proposed a dynamic bias technique, to increase the bias current of the differential input stage of a two-stage amplifier when the input voltage difference is large; and Khorramabadi [7] also proposed a class-B amplifier which had a better power efficiency but with a large output transistor. In this work, a class-B CMOS output buffer circuit is proposed. The circuit achieves the large driving capability by employing a simple but elegant comparator circuit to sense the transients of the input to turn on push-pull transistors, which are statically “off” when no input is applied. This increases the speed of the circuit without increasing too much static power consumption. The circuit also features a wide input voltage range, a large output swing.
Chung Len Lee Department of Electronics Engineering, National Chiao Tung University [email protected]
2. The Proposed Class-B Buffer Fig. 1 shows the proposed class-B buffer circuit. As a buffer, the output is connected to the inverting input (in-) and the input signal is applied to the non-inverting terminal (in+). This buffer consists of a differential stage (M4-M8), two comparators (M9-M12) and a rail-to-rail push-pull output stage (M13-M14). The differential pair M5-M6, which is biased by the constant current source M1-M4, is loaded by the diode-connected transistors M7 and M8. The comparators are used to sense and amplify the voltage difference of two inputs. Then the output of the comparators turn on/off the push-pull transistors. The aspect ratios of M9 and M11 are chosen to be the same as those of M7 and M8. However, the W/L of M10 is chosen to be a little bit larger than half of M4 but M12 a little bit smaller than half of M4, i.e., 1 W W W = + ∆ L 10 2 L 4 L
(1)
1 W W W = − ∆ L L 2 12 4 L
(2)
M1
VDD=5V
M7 M8 M9
M11 R1
M13 C1
M2
output
in-
in+ M5
M3
R2
C2
M6
M4
M10
M12
M14 VSS
Fig. 1 The proposed class-B buffer amplifier.
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
In the stable state with no input, the output voltage equals to the input voltage. The currents flowing in M5, M6, M7, M8, M9 and M11 are all I/2. Then, the currents flowing in M10 and M12 are also I/2. However, since the aspect ratio of M10 is designed to be greater than half of M4, this will make M10 go out of the saturation region and be in the triode region. As a result, the gate voltage of M14 will be forced to be close to the value of VSS. M14 will then stay at “off”. For the comparator M11-M12, similarly, M11 will be in the triode region. The gate voltage of M13 will be forced to be close to the value of VDD. M13 will also stay at “off’. That is: when no input is applied, M13 and M14 are cut off from the output. When there is an input, i.e., the input voltage of the non-inverting terminal is raised, say, by a step voltage ∆V1 , the current in M5 I 1 will be increased to + g m ∆V1 but the current in M6 2 2 I 1 will be decreased to − g m ∆V1 , where gm is the 2 2 transconductance of M5 and M6. That is: I 1 + g m ∆V1 2 2 I 1 iD 6 = − g m ∆V1 2 2 where iD 5 =
(3) (4)
W g m = I µ n Cox L 5
(5)
µn and Cox are the electron mobility in the n channel and the gate oxide capacitance per unit area respectively. The current in M6 is mirrored by M8, M9 and M11 to the two comparators M9-M12. Since iD6 is decreased, M10 will still stay in the triode region. M14 will than still stay at I − ∆I , ie.: “off”. However, if iD6 is smaller than 2 ∆V1 > 2
∆I gm
where 1 W ∆I = µ n C OX ∆ 2 L
(6) 2 (VGS 4 − Vtn ) ,
(7)
transistor M11 will go into the saturation region and its drain voltage, i.e., the gate voltage of M13 will decrease to turn on M13. M13 starts to charge the output node. The larger ∆V1 is, the more M13 is turned on. Since the gate voltage of M13 can be decreased to a really low and M13 can be turned to fully “on” to charge the output by a maximal speed. Hence, the output transistors M13-M14 can be designed to be of smaller sizes than the
conventional buffer. When the output voltage reaches the level that the voltage difference between the input and output is less than 2∆I / g m , VSG13 will be reduced and M13 begins to stop charging the output node. The smaller voltage difference is, the more M13 is turned off. Similarly, when the input voltage of the non-inverterting terminal is reduced by a step voltage ∆V1 from the stable state, M13 will still stay at “off”. If ∆V1 is greater than 2∆I / g m , M10 will go into the saturation region and M14 starts to discharge the output node. Also, when the output voltage reaches the level that the voltage difference between the input and output is less than 2∆I / g m , M14 begins to stop discharging output node. Hence, with the consideration of the offset voltage, the operation of this buffer can be summarized as follows: 2∆I , M13 will charge the 1. When Vin+ − Vout − VOS ≥ gm output node. 2∆I , M14 will discharge 2. When Vin+ − Vout − VOS ≤ − gm the output node. 2∆I 2∆I 3. When − ≤ Vin+ − Vout − VOS ≤ , both output gm gm transistors stay at off. where VOS is the input offset voltage of the buffer. Since M13 and M14 are “off” at the stable state, they draws no static current, thus does not consume static power. Hence, this circuit is low power while still can maintain a relatively high-speed. 3. Evaluation of Power Consumption There are two components in the power dissipated in the amplifier. They are: the static dissipation, which is due to the dc bias current from the power supply and the dynamic dissipation due to the charging and discharging of the load capacitance [8]. For this circuit, the static energy dissipation during a scanning period can be expressed as E static =
I biasV DD f scanning
(8)
where Ibias is the total dc bias currents for the whole circuit and fscanning is the scanning frequency. The amplifier always consumes this static dissipation. For the dynamic dissipation, during transitions, as the load capacitance is charged, charges are transferred from VDD through the output PMOS transistor M13 to the load. Power dissipation in this PMOS transistor is given by
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
Pch arg e = (V DD − V0 )i L (9) dV 0 dt The energy dissipated in this PMOS device as the output charges from VL to VH is = (V DD − V0 )C L
VH
Ech arg e = ∫ Pch arg e dt VL
(10) 1 = CLVDD (VH − VL ) − C L VH2 − VL2 2 As the output discharges to a lower value, the power is dissipated in the output NMOS transistor M14. This power dissipation is
(
)
Pdisch arg e = −V0 i L = −V0 C L
(11)
dV 0 dt
The energy dissipated as the output discharges from VH to VL is given by VL
Edisch arg e = ∫ Pdisch arg e dt VH
=
(
1 C L VH2 − VL2 2
(12)
)
µA. The maximum dynamic power consumption is 18 mW while the static power is only 235 µW. The dynamic power consumption depends on the value of the output voltage swing. The maximum value occurs when the image on a column of the display is alternating black-and-white and pixel by pixel. However, when the image on a column is at a constant gray level, the dynamic power is zero. The horizontal scanning frequency ranges from 31.5 to 97.8 KHz [3]. The power dissipation of the buffer can be estimated from equations (13), (14) and (15) for a scanning period. Fig. 3 shows the maximum power consumption versus the scanning frequency with a 4 V output voltage swing (0.8 ~ 4.8 V) for the charging and discharging steps, respectively for the circuit. It can be seen that the power consumptions of the proposed buffer amplifier depend on the scanning frequency. However, they are only 0.833 and 0.997 mW for charging and discharging respectively during one scanning period even for the scanning frequency up to 100 KHz. Fig 4 shows the power consumption versus the output voltage swing for a 97.8 KHz scanning frequency for the proposed buffer. The solid line is the power dissipation as the output voltage is charged from 0.8 V while the dash line is the one discharged to 0.8 V. It can be seen that the power dissipation depends on the output voltage swing.
The total energy dissipated in the amplifier as the output charges from VL to VH during one scanning period is therefore Etot ,ch arg e =
(
)
I biasVDD 1 + C LVDD (VH − VL ) − C L VH2 − VL2 (13) f scanning 2
When the output discharges, the total dissipated energy during one scanning period is Etot ,disch arg e
(
I V 1 = bias DD + C L VH2 − VL2 f scanning 2
)
(14)
The total average power dissipated in one buffer amplifier during one scanning period is Ptot = f scanning Etot
(15)
Fig. 2 shows the simulated results of the power supply currents for this buffer, which is loaded with a large size capacitor of 680 pF with a step-wise input of 0.8 V ~ 4.8 V. Curve (a) is the current supplied from VDD and curve (b) is the current drawn from VSS. The maximum transient current is 3.6 mA. However, the static current is only 47
Fig. 2 The simulated results of power supply currents for the proposed buffer amplifier. Curve (a) is the current supplied from VDD and curve (b) is the current drawn from VSS.
4. Experimental Results The proposed output buffer amplifier was fabricated using the TSMC 0.6-µm CMOS technology. The die photograph of the output buffer is shown in Fig 5. Fig. 6 shows the measured results of the output with the input of a large dynamic range (0.8 ~ 4.8 V) of a 100 KHz triangular wave of the buffer amplifier loaded with a 5 V supply and a large size capacitor of 680pF (not including parasitic capacitances of the pad and the test circuit). The
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
lower trace is the input waveform and the upper one is the measured output waveform. It can be seen that the output basically follows the input. The step response of the buffer with a 100 KHz square wave is shown in Fig. 7, where the lower trace is the input waveform and the upper one is the measured output waveform. The input voltage range is 0.8~4.8 V. The settling times for the outputs to settle to within 0.2% of the final voltage are 1.8 and 1.4 µs for the rising and falling edges, respectively. These values are low as compared with those of [3]. In order to show the small signal performance of the amplifier, Fig. 8 is the small signal step response of a 20 mV step waveform of the circuit. The lower trace is the input waveform and the upper one is the measured output waveform. The output waveform follows exactly the same as the input waveform with a small offset voltage of 5 mV. The total static current is 47 µA.
1.0 charge
Power Dissipation (mW)
Maximum Power Dissipation (mW)
1.0
proposed class-B buffer amplifier, which is loaded with a large size capacitor of 680 pF with the input of a step-wise (0.8 ~ 4.8 V) during one scanning period for a 97.8 KHz scanning frequency, are only 0.833 and 0.997 mW for charging and discharging respectively. Experimental prototype output buffer implemented in the TSMC 0.6-µm CMOS technology had demonstrated that the circuit draws only 47 µA static current, and exhibited settling times of 1.8 µs and 1.4 µs for rise and fall edges under a 680 pF capacitance load. The input swing is 4 V. The measured data do show that the proposed output buffer circuit is very suitable for the application in the flat panel as the display driver.
charge discharge
0.8
discharge
0.8
0.6
0.4
0.6 0.2
0
1
2
3
4
Output Voltage Swing (V)
0.4 20
40
60
80
100
Scanning Frequency (KHz)
Fig. 3 The maximum power consumption versus the scanning frequencies for a 4 V output voltage swing (0.8 ~ 4.8 V) for the charging and discharging steps of the proposed buffer.
Fig. 4 The power consumption versus the output voltage swing for a 97.8 KHz scanning frequency for the proposed buffer. The solid line is the power dissipation as the output voltage is charged from 0.8 V while the dash line is the one discharged to 0.8 V.
5. Conclusion In this paper, we have proposed and demonstrated a low power consumption, high speed, large output swing, and wide input voltage range class-B output buffer circuit which is very suitable for the flat-panel display application for driving the large column line capacitance. The driving capabilities of the circuit are achieved by adding comparators which sense the rising and/or falling edges of the input waveform to turn on a push/pull transistor to charge/discharge the output load. The push-pull transistors stay at “off” when there is no input applied, thus drawing no static power. The theoretical power dissipations of the
Fig. 5 The die photograph of the proposed output buffer.
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
Time (2µs/div) Fig. 7 The output step response of the proposed output buffer with a 100 KHz square wave input under a 680 pF capacitance load. The lower trace is the input waveform and the upper one is the measured output waveform.
Output Voltage (20mV/div)
Output Voltage (2V/div) Output Voltage (2V/div)
Time (2µs/div) Fig. 6 The measured result of the proposed output buffer under a 100 KHz triangular input waveform of an amplitude of 0.8 V to 4.8 V under a 680 pF capacitance load. The lower trace is the input waveform.
Time (2µs/div) Fig. 8 The small signal step response of the proposed output buffer. The amplitude of the step input is 20 mV. The lower trace is the input waveform.
6. References [1] Y. Takahashi et al., “Multimedia projector using 720 × 480 pixel a-Si TFT-LCD’s and a high-speed analogue driver LSI,” Displays: Technology & Application, Vol. 13, No. 1, pp. 5-30, Jan., 1992. [2] C.-C. Wang, J.-C. Wu and C.-M. Huang, “Data line driver design for a 10” 480 × 460 × 3 color FED, “ in Proc. 9th Int. Vacuum Microelectronics Conf., St. Petersburg, FL, July pp. 557-561, 1996. [3] Fan You, S.H.K. Embabi and Edgar Sanchez-Sinencio, “A 1.5 V Class AB Output Buffer” Digest of Technical papers, ISPLED, Monterey, CA, USA, pp. 285-288, 1996. [4] H. Parzhuber and W. Steinhagen, “An adaptive biasing one-stage CMOS operational amplifier for driving high capacitive loads”, IEEE Journal of Solid-State Circuit, Vol. 26, pp. 1457-1460, 1991 [5] Pang-Cheng Yu and Jiin-Chuan Wu, “A Class-B Output Buffer for Flat-Panel-Display Column Driver”, IEEE Journal of Solid-State Circuits, Vol. 34, No.1, Jan. pp. 116-119, 1999. [6] B. W. Lee and B. J. Sheu, “A high-speed CMOS amplifier with dynamic frequency compensation,” in Proc. IEEE CICC 1990, New York, May 1990, pp. 8.4.1-8.4.4. [7] H. Khorramabadi, “A CMOS line driver with 80 dB linearity for ISDN application,” in 1991 Symp. VLSI Circuits Dig. Tech. Papers, June pp. 75-76, 1991. [8] Donald A. Neamen, “Electronic Circuit Analysis and Design,” Second Edition, Published by McGraw-Hill, pp. 1043-1045, 2001.
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
Abstract A low power, high speed, but with a large input dynamic range and output swing class-B output buffer circuit which is suitable for the flat-panel display application is proposed. The buffer draws little current during static but has a large driving capability during transients. It has been demonstrated with the TSMC 0.6µm CMOS technology.
1. Introduction With the evolution of compact, light-weighted, low power and high quality display, there is a big demand of developing the low power consuming, high efficiency, and high-speed buffer circuit. The circuit should occupy a small die area, consume minimal power, have a settling time smaller than the horizontal scanning time, and a capability of offering high current resolution which can accommodate up to 256 gray levels. For a 4 V of full scale, each gray level corresponds to 16 mV [1-4]. Some output buffers were proposed and demonstrated in recent years. For examples, Yu et al [5] proposed a class-B output buffer for flat-panel-display column driver, for which a comparator was used in the negative feedback path to eliminate the quiescent current in the output stage; Lee et al [6] proposed a dynamic bias technique, to increase the bias current of the differential input stage of a two-stage amplifier when the input voltage difference is large; and Khorramabadi [7] also proposed a class-B amplifier which had a better power efficiency but with a large output transistor. In this work, a class-B CMOS output buffer circuit is proposed. The circuit achieves the large driving capability by employing a simple but elegant comparator circuit to sense the transients of the input to turn on push-pull transistors, which are statically “off” when no input is applied. This increases the speed of the circuit without increasing too much static power consumption. The circuit also features a wide input voltage range, a large output swing.
Chung Len Lee Department of Electronics Engineering, National Chiao Tung University [email protected]
2. The Proposed Class-B Buffer Fig. 1 shows the proposed class-B buffer circuit. As a buffer, the output is connected to the inverting input (in-) and the input signal is applied to the non-inverting terminal (in+). This buffer consists of a differential stage (M4-M8), two comparators (M9-M12) and a rail-to-rail push-pull output stage (M13-M14). The differential pair M5-M6, which is biased by the constant current source M1-M4, is loaded by the diode-connected transistors M7 and M8. The comparators are used to sense and amplify the voltage difference of two inputs. Then the output of the comparators turn on/off the push-pull transistors. The aspect ratios of M9 and M11 are chosen to be the same as those of M7 and M8. However, the W/L of M10 is chosen to be a little bit larger than half of M4 but M12 a little bit smaller than half of M4, i.e., 1 W W W = + ∆ L 10 2 L 4 L
(1)
1 W W W = − ∆ L L 2 12 4 L
(2)
M1
VDD=5V
M7 M8 M9
M11 R1
M13 C1
M2
output
in-
in+ M5
M3
R2
C2
M6
M4
M10
M12
M14 VSS
Fig. 1 The proposed class-B buffer amplifier.
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
In the stable state with no input, the output voltage equals to the input voltage. The currents flowing in M5, M6, M7, M8, M9 and M11 are all I/2. Then, the currents flowing in M10 and M12 are also I/2. However, since the aspect ratio of M10 is designed to be greater than half of M4, this will make M10 go out of the saturation region and be in the triode region. As a result, the gate voltage of M14 will be forced to be close to the value of VSS. M14 will then stay at “off”. For the comparator M11-M12, similarly, M11 will be in the triode region. The gate voltage of M13 will be forced to be close to the value of VDD. M13 will also stay at “off’. That is: when no input is applied, M13 and M14 are cut off from the output. When there is an input, i.e., the input voltage of the non-inverting terminal is raised, say, by a step voltage ∆V1 , the current in M5 I 1 will be increased to + g m ∆V1 but the current in M6 2 2 I 1 will be decreased to − g m ∆V1 , where gm is the 2 2 transconductance of M5 and M6. That is: I 1 + g m ∆V1 2 2 I 1 iD 6 = − g m ∆V1 2 2 where iD 5 =
(3) (4)
W g m = I µ n Cox L 5
(5)
µn and Cox are the electron mobility in the n channel and the gate oxide capacitance per unit area respectively. The current in M6 is mirrored by M8, M9 and M11 to the two comparators M9-M12. Since iD6 is decreased, M10 will still stay in the triode region. M14 will than still stay at I − ∆I , ie.: “off”. However, if iD6 is smaller than 2 ∆V1 > 2
∆I gm
where 1 W ∆I = µ n C OX ∆ 2 L
(6) 2 (VGS 4 − Vtn ) ,
(7)
transistor M11 will go into the saturation region and its drain voltage, i.e., the gate voltage of M13 will decrease to turn on M13. M13 starts to charge the output node. The larger ∆V1 is, the more M13 is turned on. Since the gate voltage of M13 can be decreased to a really low and M13 can be turned to fully “on” to charge the output by a maximal speed. Hence, the output transistors M13-M14 can be designed to be of smaller sizes than the
conventional buffer. When the output voltage reaches the level that the voltage difference between the input and output is less than 2∆I / g m , VSG13 will be reduced and M13 begins to stop charging the output node. The smaller voltage difference is, the more M13 is turned off. Similarly, when the input voltage of the non-inverterting terminal is reduced by a step voltage ∆V1 from the stable state, M13 will still stay at “off”. If ∆V1 is greater than 2∆I / g m , M10 will go into the saturation region and M14 starts to discharge the output node. Also, when the output voltage reaches the level that the voltage difference between the input and output is less than 2∆I / g m , M14 begins to stop discharging output node. Hence, with the consideration of the offset voltage, the operation of this buffer can be summarized as follows: 2∆I , M13 will charge the 1. When Vin+ − Vout − VOS ≥ gm output node. 2∆I , M14 will discharge 2. When Vin+ − Vout − VOS ≤ − gm the output node. 2∆I 2∆I 3. When − ≤ Vin+ − Vout − VOS ≤ , both output gm gm transistors stay at off. where VOS is the input offset voltage of the buffer. Since M13 and M14 are “off” at the stable state, they draws no static current, thus does not consume static power. Hence, this circuit is low power while still can maintain a relatively high-speed. 3. Evaluation of Power Consumption There are two components in the power dissipated in the amplifier. They are: the static dissipation, which is due to the dc bias current from the power supply and the dynamic dissipation due to the charging and discharging of the load capacitance [8]. For this circuit, the static energy dissipation during a scanning period can be expressed as E static =
I biasV DD f scanning
(8)
where Ibias is the total dc bias currents for the whole circuit and fscanning is the scanning frequency. The amplifier always consumes this static dissipation. For the dynamic dissipation, during transitions, as the load capacitance is charged, charges are transferred from VDD through the output PMOS transistor M13 to the load. Power dissipation in this PMOS transistor is given by
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
Pch arg e = (V DD − V0 )i L (9) dV 0 dt The energy dissipated in this PMOS device as the output charges from VL to VH is = (V DD − V0 )C L
VH
Ech arg e = ∫ Pch arg e dt VL
(10) 1 = CLVDD (VH − VL ) − C L VH2 − VL2 2 As the output discharges to a lower value, the power is dissipated in the output NMOS transistor M14. This power dissipation is
(
)
Pdisch arg e = −V0 i L = −V0 C L
(11)
dV 0 dt
The energy dissipated as the output discharges from VH to VL is given by VL
Edisch arg e = ∫ Pdisch arg e dt VH
=
(
1 C L VH2 − VL2 2
(12)
)
µA. The maximum dynamic power consumption is 18 mW while the static power is only 235 µW. The dynamic power consumption depends on the value of the output voltage swing. The maximum value occurs when the image on a column of the display is alternating black-and-white and pixel by pixel. However, when the image on a column is at a constant gray level, the dynamic power is zero. The horizontal scanning frequency ranges from 31.5 to 97.8 KHz [3]. The power dissipation of the buffer can be estimated from equations (13), (14) and (15) for a scanning period. Fig. 3 shows the maximum power consumption versus the scanning frequency with a 4 V output voltage swing (0.8 ~ 4.8 V) for the charging and discharging steps, respectively for the circuit. It can be seen that the power consumptions of the proposed buffer amplifier depend on the scanning frequency. However, they are only 0.833 and 0.997 mW for charging and discharging respectively during one scanning period even for the scanning frequency up to 100 KHz. Fig 4 shows the power consumption versus the output voltage swing for a 97.8 KHz scanning frequency for the proposed buffer. The solid line is the power dissipation as the output voltage is charged from 0.8 V while the dash line is the one discharged to 0.8 V. It can be seen that the power dissipation depends on the output voltage swing.
The total energy dissipated in the amplifier as the output charges from VL to VH during one scanning period is therefore Etot ,ch arg e =
(
)
I biasVDD 1 + C LVDD (VH − VL ) − C L VH2 − VL2 (13) f scanning 2
When the output discharges, the total dissipated energy during one scanning period is Etot ,disch arg e
(
I V 1 = bias DD + C L VH2 − VL2 f scanning 2
)
(14)
The total average power dissipated in one buffer amplifier during one scanning period is Ptot = f scanning Etot
(15)
Fig. 2 shows the simulated results of the power supply currents for this buffer, which is loaded with a large size capacitor of 680 pF with a step-wise input of 0.8 V ~ 4.8 V. Curve (a) is the current supplied from VDD and curve (b) is the current drawn from VSS. The maximum transient current is 3.6 mA. However, the static current is only 47
Fig. 2 The simulated results of power supply currents for the proposed buffer amplifier. Curve (a) is the current supplied from VDD and curve (b) is the current drawn from VSS.
4. Experimental Results The proposed output buffer amplifier was fabricated using the TSMC 0.6-µm CMOS technology. The die photograph of the output buffer is shown in Fig 5. Fig. 6 shows the measured results of the output with the input of a large dynamic range (0.8 ~ 4.8 V) of a 100 KHz triangular wave of the buffer amplifier loaded with a 5 V supply and a large size capacitor of 680pF (not including parasitic capacitances of the pad and the test circuit). The
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
lower trace is the input waveform and the upper one is the measured output waveform. It can be seen that the output basically follows the input. The step response of the buffer with a 100 KHz square wave is shown in Fig. 7, where the lower trace is the input waveform and the upper one is the measured output waveform. The input voltage range is 0.8~4.8 V. The settling times for the outputs to settle to within 0.2% of the final voltage are 1.8 and 1.4 µs for the rising and falling edges, respectively. These values are low as compared with those of [3]. In order to show the small signal performance of the amplifier, Fig. 8 is the small signal step response of a 20 mV step waveform of the circuit. The lower trace is the input waveform and the upper one is the measured output waveform. The output waveform follows exactly the same as the input waveform with a small offset voltage of 5 mV. The total static current is 47 µA.
1.0 charge
Power Dissipation (mW)
Maximum Power Dissipation (mW)
1.0
proposed class-B buffer amplifier, which is loaded with a large size capacitor of 680 pF with the input of a step-wise (0.8 ~ 4.8 V) during one scanning period for a 97.8 KHz scanning frequency, are only 0.833 and 0.997 mW for charging and discharging respectively. Experimental prototype output buffer implemented in the TSMC 0.6-µm CMOS technology had demonstrated that the circuit draws only 47 µA static current, and exhibited settling times of 1.8 µs and 1.4 µs for rise and fall edges under a 680 pF capacitance load. The input swing is 4 V. The measured data do show that the proposed output buffer circuit is very suitable for the application in the flat panel as the display driver.
charge discharge
0.8
discharge
0.8
0.6
0.4
0.6 0.2
0
1
2
3
4
Output Voltage Swing (V)
0.4 20
40
60
80
100
Scanning Frequency (KHz)
Fig. 3 The maximum power consumption versus the scanning frequencies for a 4 V output voltage swing (0.8 ~ 4.8 V) for the charging and discharging steps of the proposed buffer.
Fig. 4 The power consumption versus the output voltage swing for a 97.8 KHz scanning frequency for the proposed buffer. The solid line is the power dissipation as the output voltage is charged from 0.8 V while the dash line is the one discharged to 0.8 V.
5. Conclusion In this paper, we have proposed and demonstrated a low power consumption, high speed, large output swing, and wide input voltage range class-B output buffer circuit which is very suitable for the flat-panel display application for driving the large column line capacitance. The driving capabilities of the circuit are achieved by adding comparators which sense the rising and/or falling edges of the input waveform to turn on a push/pull transistor to charge/discharge the output load. The push-pull transistors stay at “off” when there is no input applied, thus drawing no static power. The theoretical power dissipations of the
Fig. 5 The die photograph of the proposed output buffer.
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
Time (2µs/div) Fig. 7 The output step response of the proposed output buffer with a 100 KHz square wave input under a 680 pF capacitance load. The lower trace is the input waveform and the upper one is the measured output waveform.
Output Voltage (20mV/div)
Output Voltage (2V/div) Output Voltage (2V/div)
Time (2µs/div) Fig. 6 The measured result of the proposed output buffer under a 100 KHz triangular input waveform of an amplitude of 0.8 V to 4.8 V under a 680 pF capacitance load. The lower trace is the input waveform.
Time (2µs/div) Fig. 8 The small signal step response of the proposed output buffer. The amplitude of the step input is 20 mV. The lower trace is the input waveform.
6. References [1] Y. Takahashi et al., “Multimedia projector using 720 × 480 pixel a-Si TFT-LCD’s and a high-speed analogue driver LSI,” Displays: Technology & Application, Vol. 13, No. 1, pp. 5-30, Jan., 1992. [2] C.-C. Wang, J.-C. Wu and C.-M. Huang, “Data line driver design for a 10” 480 × 460 × 3 color FED, “ in Proc. 9th Int. Vacuum Microelectronics Conf., St. Petersburg, FL, July pp. 557-561, 1996. [3] Fan You, S.H.K. Embabi and Edgar Sanchez-Sinencio, “A 1.5 V Class AB Output Buffer” Digest of Technical papers, ISPLED, Monterey, CA, USA, pp. 285-288, 1996. [4] H. Parzhuber and W. Steinhagen, “An adaptive biasing one-stage CMOS operational amplifier for driving high capacitive loads”, IEEE Journal of Solid-State Circuit, Vol. 26, pp. 1457-1460, 1991 [5] Pang-Cheng Yu and Jiin-Chuan Wu, “A Class-B Output Buffer for Flat-Panel-Display Column Driver”, IEEE Journal of Solid-State Circuits, Vol. 34, No.1, Jan. pp. 116-119, 1999. [6] B. W. Lee and B. J. Sheu, “A high-speed CMOS amplifier with dynamic frequency compensation,” in Proc. IEEE CICC 1990, New York, May 1990, pp. 8.4.1-8.4.4. [7] H. Khorramabadi, “A CMOS line driver with 80 dB linearity for ISDN application,” in 1991 Symp. VLSI Circuits Dig. Tech. Papers, June pp. 75-76, 1991. [8] Donald A. Neamen, “Electronic Circuit Analysis and Design,” Second Edition, Published by McGraw-Hill, pp. 1043-1045, 2001.
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
