Low voltage Class-AB Output Stages For CMOS ... - Semantic Scholar
ESSCIRC 2002
Low voltage Class-AB Output Stages For CMOS Op-amps R. G. Carvajal 1, A. Torralba 1, J. Ramírez-Angulo 2, J. Tombs 1 and F. Muñoz 1 Dpto. de Ing. Electronica, Escuela Superior de Ingenieros, Universidad de Sevilla, Sevilla, Spain 2 Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM. 1
Abstract Three new class-AB output stages for CMOS op-amps with accurate quiescent current control using low-voltage techniques are proposed. These output stages make use of passive components (capacitors and resistors) and/or feedback to allow operation with a supply voltage close to a transistor threshold voltage. Three op-amps using the proposed output stages were sent for fabrication using a standard 0.8µm CMOS process and experimental results are provided showing a GBW = 15 MHz and rail-to-rail output swing using a voltage supply of 1.5V.
1. Introduction The need to reduce digital power consumption has led to a reduction of supply voltages in mixed-mode IC design. Although two oxides are presently available in some analogue technologies, digital compatibility forces analogue circuits to operate with supply voltages close to a transistor threshold voltage.
by means of one transistor and one current source. Despite the simple and power efficient implementation of the floating voltage source, its quiescent current control scheme was too complex. The Monticelli´s scheme [7] achieves an accurate quiescent current control by means of a translinear loop at the expense of a high supply voltage (larger than two VGS). In this paper three new output stages are proposed to allow operation with a supply voltage close to a transistor threshold voltage. In the following sections these output stages will be presented and it’s operation proven experimentally.
2. Class AB output stage with quiescent current control using floating capacitors A new CMOS class AB output stage is presented with simple quiescent current control and rail-to-rail output swing (figures 1b) using floating capacitors. This output stage is suitable for both continuous and discrete time applications. In both stages X is the input terminal. a) First output stage (figure 1b)
M outp Vb
The first output stage uses Multiple-Input Floating Gate Transistors (MIFGT's). In an n-MIFGT with N inputs, each input i is connected to the floating gate G by a poly II-poly I capacitor Ci. The DC equivalent circuit is derived by applying charge conservation law on the floating gate (figure 2):
Vout M outn
Vx
a) M b1
N
0 = ∑ Ci (Vi − VG ) + C S (VS − VG ) + C D (VD − VG ) + C B (VB − VG ) (1) M outp
M b2
Vout
Ib
Cx
Vz M b3
M outn
Vy
Cy
X
b) Figure 1: a) Class AB output stage with floating biasing battery, b) Low-voltage implementation with a floating-gate transistor. Several low-voltage (VDD < 1.5V) class-AB output stages for CMOS opamps have been recently reported [1]-[4]. Despite its simplicity, the circuit in [1] does not provide accurate control of the quiescent current and, even with an adaptive load, it depends on process variations. Furthermore, its class AB behavior is poor. In [2] a low-voltage class-AB output stage was proposed by folding a biasing transistor in the well-known Monticelli’s output stage [7]. In [3] a class-AB output stage was presented with the (negative) floating voltage source VAB of figure 1a implemented
i =1
where CS, CD and CG denote the capacitances from gate to source, drain and bulk, respectively, and VG, VS, VD and VB are the voltages in the floating gate, drain, source and bulk, respectively. From (1), N
Ci C C C Vi + S VS + D VD + B VB C C C C i =1 T T T T
VG = ∑
(2)
N
where C = C + C + C + C is the total gate capacitance. ∑ i S D B T i =1
For transistors Mb3 and Moutn in figure 1b, with VS = VB = 0 and Cx, Cy >> CD Cy Cy C C C (3) VG = x Vx + V y + D VD ≈ x Vx + Vy CT CT CT CT CT Therefore, transistor currents are determined by a weighted sum of the input voltages Vx and Vy . For low voltage operation, one input (Vy) is close to VDD allowing a wide range of operation in the other input.
739
CD
C1
D
G
B
V1 VN
CB
CN CS
mirror, allowing operation with less than 1V supply voltage. Note that the circuit in figure 3c maintains its operation independent on the supply voltage, as long as VAB remains negative (which approximately means VDD < 2 V in our technology). For larger supply voltages, the polarity of the floating voltage sources can be reversed by changing the role of nodes X-Y. I2 = I1 M outp
Ir
S
V2
-
Figure 2: N-input MIFGT
VAB
R
-
Vout
Figure 3a shows the second proposed output stage and figure 3b its biasing circuit for quiescent current control. The proposed stage uses resistor R and current sources Ir to implement the floating voltage source VAB of figure 1a. The input and output terminal voltages are VX and Vout .Cross connecting terminals X and Y to the gates of transistors Moutp and Moutn, respectively, allows the supply voltage to be close to a transistor threshold voltage. For larger supply voltages a straight connection of these terminals should be done. In figure 3b, transistor M1 and current source I1 determine V1=VXQ (upper index Q means quiescent value), while transistor M2 and current source I2 = I1 determine V2=VYQ. The resistor R' and the differential amplifier DA driving two matched current sources Ir' constitute a voltage-to-current converter [5], so that Ir' = - VAB / R' = ( VYQ – VXQ ) / R' . This floating voltage source VAB is replicated in figure 3a, by means of matched resistor R and current sources Ir. In a real implementation, to reduce power consumption, M1 (M2) and I1 = I2 would be a scaled version of Moutp (Moutn) and IMoutpQ = IMoutnQ , respectively.. Figure 3c shows a practical implementation of the whole output stage, where the amplifier DA of figure 3b has been implemented by means of a simple pMOS differential amplifier. Bottom current sources Ir and Ir’ have been implemented by means of a low voltage current
740
+ I 'r
(a)
(b)
I2 = I1
M outp Y R'
VAB
R Vout +
Ic
X V1 = VXQ
M outn
M1
I1
Second proposed output stage (figure 3a).
-
I1
The circuit in figure 1b allows a simple quiescent current control, rail-to-rail output swing and operates with low supply voltages. However, due to the capacitive divider in the MIFGT terminals (3), its transconductance and, hence, the maximum achievable bandwidth, are reduced.
a)
+
M outn
Ir
M2
Another two new CMOS class AB output stages for continuoustime operation are presented with simple and accurate quiescent current control and rail-to-rail output swing (figures 3a and 4).
V1
M1
X
VAB
R'
DA
+
In figure 1b, transistors Mb1 , Mb2 and Mb3 force Vy to a value such as the drain current in transistor Mb3 is equal to Ib. When this circuit is used as the second stage of an opamp (figure 5), negative feedback forces the quiescent voltage of the output node of the first stage to be VxQ=Vz, so that IMoutpQ = IMoutnQ = IoutQ = Ib. Once again, to reduce power consumption, the biasing circuitry (Mb1 , Mb2 , Mb3 and Ib ) will be normally scaled down.
3. Class AB output stages with quiescent current control using dynamic biasing.
I 'r
M2
Y
Ic 2
(c) Figure 3: Second proposed class-AB output stage: a) Basic idea, b) dynamic biasing circuitry, c) practical implementation. b)
Third proposed output stage (figure 4)
The third proposed output stage is shown in figure 4. In this figure, the bias current Io in the low voltage differential pairs M1p-M3p and M1n-M3n [8] accurately determines the quiescent output current IoutQ = IMoutnQ = IMoutpQ =2αIo. Furthermore, the minimum current in the output transistors is given by IoutMIN = IMoutnMIN = IMoutpMIN =αIo . Note that IoutQ and IoutMIN do not depend on the value of the floating voltage sources VAB, which is selected to allow an accurate copy of currents IM3p and IM3n to transistors Moutp and Moutn, respectively. Under quiescent conditions, if |VAB| was too large, transistors M3p and M3n would not be in saturation. On the other hand, if |VAB| was too small, transistors M1p-M2p and M1n-M2n would operate in linear region. Appropriate values for VXQ and VYQ are: VXQ = VDD - VSGM1pQ VDSsat - ∆VXMAX / 2, and VYQ = VGSM1nQ + VDSsat + ∆VXMAX / 2 , where ∆VXMAX is the maximum expected variation for the input node voltage VX . As a result, an appropriate value for VAB= VXQ – VYQ = VDD - VGSM1nQ - VSGM1pQ - 2VDSsat - ∆VXMAX . If the input node VX in figure 4 is the first stage output of an op-amp, negative feedback reduces ∆VXMAX to only a few mV so that, for a 0.8 µm CMOS technology with 0.8 V of transistor threshold voltages, VDD - VAB is in the order of 1.8 to 3 V depending on transistor sizes and biasing currents. According to this reasoning, this stage can be operated with less than 1 V supply voltage and VAB = - 0.8 V . Note that this stage can be also operated with a high supply voltage if VAB is positive. The same dynamic biasing scheme of figure 3b can be used to generate the floating voltage
sources VAB between nodes X-Y and W-Z by means of two matched (and, normally scaled) replicas of current sources Ir' and resistor R'.
M1p
of
transistors
has
a
reduced
M outp
M3p
X
kind
α
:
1
MIFGT as this transconductance.
M2p
I M outp
W
Io VAB
+ -
+ -
VAB
Vout
Io
M1n
Y
I M outn
Z
M2n
Figure 6: Microphotograph of the chip with the op-amps.
M outn
M3n
:
1
α
units
Figure 4: Third proposed class-AB output stage
V CM-ADJ
Idp
-
Rc
+ Vin
M in1
Cc
M in2
Vout
X
Output Stage (figure 1c or 4a or 5)
CL
Figure 5: Single op-amp in voltage follower configuration to test output stages performances.
output stage of figure1d 1.5
output stage of figure3a 1.5
Output Stage of figure4 1.5
VDD
V
CL (CC)
pF
10
10
10
Moutn
W/L
500/1
165/1
165/1
Moutp
W/L
500/1
500/1
500/1
M1 (M3p)
W/L
500/1
50/1
50/1
M2 (M3n)
W/L
50/1
16.5/1
16.5/1
Min1, Min2
W/L
500/1
500/1
500/1
Idp
µA
100
100
100
Ib (Io)
µA
7.5
-
3.75
CX
pF
6
-
-
CY
pF
2.6
-
-
R,R’
kΩ
-
25
25
I1 =I2
µA
-
7.5
-
Table I. Op-amp design parameters.
4. Experimental results The three op-amps using the scheme of figure 5 were designed with the output stages proposed in figures 1b, 3a and 4. Design parameters for the three op-amps with the same specifications are resumed in Table I. These op-amps have been fabricated using the AMS 0.8 µm CMOS technology whose transistor threshold voltages are in the order of 0.85 V (DC level shift VCM-ADJ was implemented by means of a SC circuit). Experimental results can be observed in Table II. Note that all achieve a GBW of 15MHz with a VDD=1.5V. Figure 7 shows the experimental transient response of the circuits to a square input signal of 300mVpeak-to-peak. In all cases the results obtained match with the simulated response. The values obtained for the THD also match the expected values. Note that the main difference between the three output stages is that the peak output current is much lower in the one that makes use of
5. Conclusions Three output stages for low-voltage operation have been proposed. All of them allow a simple and accurate control of the quiescent current and have rail-to-rail output swing. The first one is suitable for SC or switched-opamp applications, while the others can be used for both, sampled-data, or continuous-time applications. Simulation results show gain-bandwidth products of 15 MHz (VDD=1.5V), when acting as the output stage of an opamp with a pMOS differential pair as input stage. The three output stages have been verified experimentally and the obtained results match the expected valued.
6. Acknowledgment This work has been financed the Spanish Comisión Interministerial de Ciencia y Tecnología (CICYT) and the
741
European Union (FEDER) under grant 1FD97-0317. The help of Mrs. Marta Rodriguez Pizarro to test the chip is gratefully acknowledged.
[7]
[8] Units
DC Gain
DB
Output Stage of figure 1c 60 dB
Output Stage of figure 3a 67dB
Output Stage of figure 4 65dB
Phase Margin
Deg
70o
75º
70º
GBW
MHz
15
15
15
Quiescent output current Minimum output current Supply current
µA
80
75
75
µA
0
0
32
µA
440
332
387
PSRR
dB
40dB
40dB
38dB
CMRR
dB
54 dB
45dB
45dB
THD @ 1kHz
dB
60
65
60
VCM-ADJ *
mV
600
600
600
Slew Rate *
V/µs
10
10
10
Peak output Current *
µA
350
600
500
MONTICELLI, D.M.: "A quad CMOS single-supply op amp with rail-to-rail output swing". IEEE J. of Solid-State Circuits, 1986, SC-21, (6), pp. 1026-1034. PELUSO, V., VANCORELAND, P., MARQUES, A.M., STEYAERT, M.S.J., and SANSEN, W.: “A 900-mV low-power Σ- A/D converter with 77-dB dynamic range”, IEEE J. Solid-State Circuits, 1998, SC-33, (12), pp. 1887-1897.
a)
Table II. Simulated performances (CL=10pF, VDD=1.5, CC=10pF, RC=500Ω,). (*) Transient response, 0.3V peak square input signal
7. References [1]
[2]
[3]
[4]
[5]
[6]
742
YOU, F., EMBABI, S.H.K., and SÁNCHEZSINENCIO, E.: “Low-voltage class AB buffers with quiescent current control”, IEEE J. of Solid-State Circuits, 1998, 33, (6), pp. 915-920. DE LANGEN, and HUISING, H.J.: “Compact lowvoltage power-efficient operational amplifier cells for VLSI”, IEEE J. of Solid-State Circuits, 1998, 33, (10), pp. 1482-1496. RAMÍREZ-ANGULO, J., CARVAJAL, R.G:, TOMBS, J., and TORRALBA, A.: “A simple technique for opamp continuous-time 1 V supply operation”, Electron. Lett., 1999, 35, (4), pp. 263-264. MUÑOZ, F., TORRALBA, A., CARVAJAL, R.G., and RAMÍREZ-ANGULO, J.: “Two new VHF tunable CMOS low-voltage linear transconductors and their application to HF gm-C filter design”, in Proc. IEEE ISCAS’2000, Geneva, May 2000. PALMISANO, G., and PENNISI, S.: “Low-voltage dynamic biasing technique for CMOS class AB current-mode circuits”, Electron. Lett., 2000, 36, (2), pp. 114-115. BASCHIROTTO, A., CASTELLO, R., and MONTAGNA, G.P: “Active series switch for switched opamp circuits”, Electron. Lett., 1999, 35, (4), pp. 263264.
b)
c) Figure 7: Experimental transient response of the opam using the output stage in: a) figure 1b, b) figure 3a, c) figure 4.
Low voltage Class-AB Output Stages For CMOS Op-amps R. G. Carvajal 1, A. Torralba 1, J. Ramírez-Angulo 2, J. Tombs 1 and F. Muñoz 1 Dpto. de Ing. Electronica, Escuela Superior de Ingenieros, Universidad de Sevilla, Sevilla, Spain 2 Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM. 1
Abstract Three new class-AB output stages for CMOS op-amps with accurate quiescent current control using low-voltage techniques are proposed. These output stages make use of passive components (capacitors and resistors) and/or feedback to allow operation with a supply voltage close to a transistor threshold voltage. Three op-amps using the proposed output stages were sent for fabrication using a standard 0.8µm CMOS process and experimental results are provided showing a GBW = 15 MHz and rail-to-rail output swing using a voltage supply of 1.5V.
1. Introduction The need to reduce digital power consumption has led to a reduction of supply voltages in mixed-mode IC design. Although two oxides are presently available in some analogue technologies, digital compatibility forces analogue circuits to operate with supply voltages close to a transistor threshold voltage.
by means of one transistor and one current source. Despite the simple and power efficient implementation of the floating voltage source, its quiescent current control scheme was too complex. The Monticelli´s scheme [7] achieves an accurate quiescent current control by means of a translinear loop at the expense of a high supply voltage (larger than two VGS). In this paper three new output stages are proposed to allow operation with a supply voltage close to a transistor threshold voltage. In the following sections these output stages will be presented and it’s operation proven experimentally.
2. Class AB output stage with quiescent current control using floating capacitors A new CMOS class AB output stage is presented with simple quiescent current control and rail-to-rail output swing (figures 1b) using floating capacitors. This output stage is suitable for both continuous and discrete time applications. In both stages X is the input terminal. a) First output stage (figure 1b)
M outp Vb
The first output stage uses Multiple-Input Floating Gate Transistors (MIFGT's). In an n-MIFGT with N inputs, each input i is connected to the floating gate G by a poly II-poly I capacitor Ci. The DC equivalent circuit is derived by applying charge conservation law on the floating gate (figure 2):
Vout M outn
Vx
a) M b1
N
0 = ∑ Ci (Vi − VG ) + C S (VS − VG ) + C D (VD − VG ) + C B (VB − VG ) (1) M outp
M b2
Vout
Ib
Cx
Vz M b3
M outn
Vy
Cy
X
b) Figure 1: a) Class AB output stage with floating biasing battery, b) Low-voltage implementation with a floating-gate transistor. Several low-voltage (VDD < 1.5V) class-AB output stages for CMOS opamps have been recently reported [1]-[4]. Despite its simplicity, the circuit in [1] does not provide accurate control of the quiescent current and, even with an adaptive load, it depends on process variations. Furthermore, its class AB behavior is poor. In [2] a low-voltage class-AB output stage was proposed by folding a biasing transistor in the well-known Monticelli’s output stage [7]. In [3] a class-AB output stage was presented with the (negative) floating voltage source VAB of figure 1a implemented
i =1
where CS, CD and CG denote the capacitances from gate to source, drain and bulk, respectively, and VG, VS, VD and VB are the voltages in the floating gate, drain, source and bulk, respectively. From (1), N
Ci C C C Vi + S VS + D VD + B VB C C C C i =1 T T T T
VG = ∑
(2)
N
where C = C + C + C + C is the total gate capacitance. ∑ i S D B T i =1
For transistors Mb3 and Moutn in figure 1b, with VS = VB = 0 and Cx, Cy >> CD Cy Cy C C C (3) VG = x Vx + V y + D VD ≈ x Vx + Vy CT CT CT CT CT Therefore, transistor currents are determined by a weighted sum of the input voltages Vx and Vy . For low voltage operation, one input (Vy) is close to VDD allowing a wide range of operation in the other input.
739
CD
C1
D
G
B
V1 VN
CB
CN CS
mirror, allowing operation with less than 1V supply voltage. Note that the circuit in figure 3c maintains its operation independent on the supply voltage, as long as VAB remains negative (which approximately means VDD < 2 V in our technology). For larger supply voltages, the polarity of the floating voltage sources can be reversed by changing the role of nodes X-Y. I2 = I1 M outp
Ir
S
V2
-
Figure 2: N-input MIFGT
VAB
R
-
Vout
Figure 3a shows the second proposed output stage and figure 3b its biasing circuit for quiescent current control. The proposed stage uses resistor R and current sources Ir to implement the floating voltage source VAB of figure 1a. The input and output terminal voltages are VX and Vout .Cross connecting terminals X and Y to the gates of transistors Moutp and Moutn, respectively, allows the supply voltage to be close to a transistor threshold voltage. For larger supply voltages a straight connection of these terminals should be done. In figure 3b, transistor M1 and current source I1 determine V1=VXQ (upper index Q means quiescent value), while transistor M2 and current source I2 = I1 determine V2=VYQ. The resistor R' and the differential amplifier DA driving two matched current sources Ir' constitute a voltage-to-current converter [5], so that Ir' = - VAB / R' = ( VYQ – VXQ ) / R' . This floating voltage source VAB is replicated in figure 3a, by means of matched resistor R and current sources Ir. In a real implementation, to reduce power consumption, M1 (M2) and I1 = I2 would be a scaled version of Moutp (Moutn) and IMoutpQ = IMoutnQ , respectively.. Figure 3c shows a practical implementation of the whole output stage, where the amplifier DA of figure 3b has been implemented by means of a simple pMOS differential amplifier. Bottom current sources Ir and Ir’ have been implemented by means of a low voltage current
740
+ I 'r
(a)
(b)
I2 = I1
M outp Y R'
VAB
R Vout +
Ic
X V1 = VXQ
M outn
M1
I1
Second proposed output stage (figure 3a).
-
I1
The circuit in figure 1b allows a simple quiescent current control, rail-to-rail output swing and operates with low supply voltages. However, due to the capacitive divider in the MIFGT terminals (3), its transconductance and, hence, the maximum achievable bandwidth, are reduced.
a)
+
M outn
Ir
M2
Another two new CMOS class AB output stages for continuoustime operation are presented with simple and accurate quiescent current control and rail-to-rail output swing (figures 3a and 4).
V1
M1
X
VAB
R'
DA
+
In figure 1b, transistors Mb1 , Mb2 and Mb3 force Vy to a value such as the drain current in transistor Mb3 is equal to Ib. When this circuit is used as the second stage of an opamp (figure 5), negative feedback forces the quiescent voltage of the output node of the first stage to be VxQ=Vz, so that IMoutpQ = IMoutnQ = IoutQ = Ib. Once again, to reduce power consumption, the biasing circuitry (Mb1 , Mb2 , Mb3 and Ib ) will be normally scaled down.
3. Class AB output stages with quiescent current control using dynamic biasing.
I 'r
M2
Y
Ic 2
(c) Figure 3: Second proposed class-AB output stage: a) Basic idea, b) dynamic biasing circuitry, c) practical implementation. b)
Third proposed output stage (figure 4)
The third proposed output stage is shown in figure 4. In this figure, the bias current Io in the low voltage differential pairs M1p-M3p and M1n-M3n [8] accurately determines the quiescent output current IoutQ = IMoutnQ = IMoutpQ =2αIo. Furthermore, the minimum current in the output transistors is given by IoutMIN = IMoutnMIN = IMoutpMIN =αIo . Note that IoutQ and IoutMIN do not depend on the value of the floating voltage sources VAB, which is selected to allow an accurate copy of currents IM3p and IM3n to transistors Moutp and Moutn, respectively. Under quiescent conditions, if |VAB| was too large, transistors M3p and M3n would not be in saturation. On the other hand, if |VAB| was too small, transistors M1p-M2p and M1n-M2n would operate in linear region. Appropriate values for VXQ and VYQ are: VXQ = VDD - VSGM1pQ VDSsat - ∆VXMAX / 2, and VYQ = VGSM1nQ + VDSsat + ∆VXMAX / 2 , where ∆VXMAX is the maximum expected variation for the input node voltage VX . As a result, an appropriate value for VAB= VXQ – VYQ = VDD - VGSM1nQ - VSGM1pQ - 2VDSsat - ∆VXMAX . If the input node VX in figure 4 is the first stage output of an op-amp, negative feedback reduces ∆VXMAX to only a few mV so that, for a 0.8 µm CMOS technology with 0.8 V of transistor threshold voltages, VDD - VAB is in the order of 1.8 to 3 V depending on transistor sizes and biasing currents. According to this reasoning, this stage can be operated with less than 1 V supply voltage and VAB = - 0.8 V . Note that this stage can be also operated with a high supply voltage if VAB is positive. The same dynamic biasing scheme of figure 3b can be used to generate the floating voltage
sources VAB between nodes X-Y and W-Z by means of two matched (and, normally scaled) replicas of current sources Ir' and resistor R'.
M1p
of
transistors
has
a
reduced
M outp
M3p
X
kind
α
:
1
MIFGT as this transconductance.
M2p
I M outp
W
Io VAB
+ -
+ -
VAB
Vout
Io
M1n
Y
I M outn
Z
M2n
Figure 6: Microphotograph of the chip with the op-amps.
M outn
M3n
:
1
α
units
Figure 4: Third proposed class-AB output stage
V CM-ADJ
Idp
-
Rc
+ Vin
M in1
Cc
M in2
Vout
X
Output Stage (figure 1c or 4a or 5)
CL
Figure 5: Single op-amp in voltage follower configuration to test output stages performances.
output stage of figure1d 1.5
output stage of figure3a 1.5
Output Stage of figure4 1.5
VDD
V
CL (CC)
pF
10
10
10
Moutn
W/L
500/1
165/1
165/1
Moutp
W/L
500/1
500/1
500/1
M1 (M3p)
W/L
500/1
50/1
50/1
M2 (M3n)
W/L
50/1
16.5/1
16.5/1
Min1, Min2
W/L
500/1
500/1
500/1
Idp
µA
100
100
100
Ib (Io)
µA
7.5
-
3.75
CX
pF
6
-
-
CY
pF
2.6
-
-
R,R’
kΩ
-
25
25
I1 =I2
µA
-
7.5
-
Table I. Op-amp design parameters.
4. Experimental results The three op-amps using the scheme of figure 5 were designed with the output stages proposed in figures 1b, 3a and 4. Design parameters for the three op-amps with the same specifications are resumed in Table I. These op-amps have been fabricated using the AMS 0.8 µm CMOS technology whose transistor threshold voltages are in the order of 0.85 V (DC level shift VCM-ADJ was implemented by means of a SC circuit). Experimental results can be observed in Table II. Note that all achieve a GBW of 15MHz with a VDD=1.5V. Figure 7 shows the experimental transient response of the circuits to a square input signal of 300mVpeak-to-peak. In all cases the results obtained match with the simulated response. The values obtained for the THD also match the expected values. Note that the main difference between the three output stages is that the peak output current is much lower in the one that makes use of
5. Conclusions Three output stages for low-voltage operation have been proposed. All of them allow a simple and accurate control of the quiescent current and have rail-to-rail output swing. The first one is suitable for SC or switched-opamp applications, while the others can be used for both, sampled-data, or continuous-time applications. Simulation results show gain-bandwidth products of 15 MHz (VDD=1.5V), when acting as the output stage of an opamp with a pMOS differential pair as input stage. The three output stages have been verified experimentally and the obtained results match the expected valued.
6. Acknowledgment This work has been financed the Spanish Comisión Interministerial de Ciencia y Tecnología (CICYT) and the
741
European Union (FEDER) under grant 1FD97-0317. The help of Mrs. Marta Rodriguez Pizarro to test the chip is gratefully acknowledged.
[7]
[8] Units
DC Gain
DB
Output Stage of figure 1c 60 dB
Output Stage of figure 3a 67dB
Output Stage of figure 4 65dB
Phase Margin
Deg
70o
75º
70º
GBW
MHz
15
15
15
Quiescent output current Minimum output current Supply current
µA
80
75
75
µA
0
0
32
µA
440
332
387
PSRR
dB
40dB
40dB
38dB
CMRR
dB
54 dB
45dB
45dB
THD @ 1kHz
dB
60
65
60
VCM-ADJ *
mV
600
600
600
Slew Rate *
V/µs
10
10
10
Peak output Current *
µA
350
600
500
MONTICELLI, D.M.: "A quad CMOS single-supply op amp with rail-to-rail output swing". IEEE J. of Solid-State Circuits, 1986, SC-21, (6), pp. 1026-1034. PELUSO, V., VANCORELAND, P., MARQUES, A.M., STEYAERT, M.S.J., and SANSEN, W.: “A 900-mV low-power Σ- A/D converter with 77-dB dynamic range”, IEEE J. Solid-State Circuits, 1998, SC-33, (12), pp. 1887-1897.
a)
Table II. Simulated performances (CL=10pF, VDD=1.5, CC=10pF, RC=500Ω,). (*) Transient response, 0.3V peak square input signal
7. References [1]
[2]
[3]
[4]
[5]
[6]
742
YOU, F., EMBABI, S.H.K., and SÁNCHEZSINENCIO, E.: “Low-voltage class AB buffers with quiescent current control”, IEEE J. of Solid-State Circuits, 1998, 33, (6), pp. 915-920. DE LANGEN, and HUISING, H.J.: “Compact lowvoltage power-efficient operational amplifier cells for VLSI”, IEEE J. of Solid-State Circuits, 1998, 33, (10), pp. 1482-1496. RAMÍREZ-ANGULO, J., CARVAJAL, R.G:, TOMBS, J., and TORRALBA, A.: “A simple technique for opamp continuous-time 1 V supply operation”, Electron. Lett., 1999, 35, (4), pp. 263-264. MUÑOZ, F., TORRALBA, A., CARVAJAL, R.G., and RAMÍREZ-ANGULO, J.: “Two new VHF tunable CMOS low-voltage linear transconductors and their application to HF gm-C filter design”, in Proc. IEEE ISCAS’2000, Geneva, May 2000. PALMISANO, G., and PENNISI, S.: “Low-voltage dynamic biasing technique for CMOS class AB current-mode circuits”, Electron. Lett., 2000, 36, (2), pp. 114-115. BASCHIROTTO, A., CASTELLO, R., and MONTAGNA, G.P: “Active series switch for switched opamp circuits”, Electron. Lett., 1999, 35, (4), pp. 263264.
b)
c) Figure 7: Experimental transient response of the opam using the output stage in: a) figure 1b, b) figure 3a, c) figure 4.
