Quiz 3a (Winter 2012)
McGill University Department of Electrical and Computer Engineering Course: ECSE 323 - Digital Systems Design Winter 2012 Assignment #3 – Friday Name & Student ID:
TOPIC: CMOS CIRCUITS & VHDL Exercise 1
(35 points)
a) Consider the AND gate Y=(A AND B), where A, B are the input Boolean variables. Let us also assume that the input pattern AB follows the 2-bit Binary counting pattern, i.e., AB = 00, 01, 10, 11, 00, …, where every 1ns a transition occurs, e.g., from AB=00 to AB=01. Assume that the load capacitance at the output node Y is equal to CY=1fF. Also, we have: VDD=2V. Compute the switching power consumption at the node Y. b) What happens to power, when Y is an n-input AND gate, while the n inputs follow the nbit Binary counting pattern? Exercise 2
(30 points)
Let's consider a combinational function F which drives a circuit with capacitance C L. The propagation time tp through F increases as CL grows and can be expressed as: tp = tp0 + dtp * CL where tp0 is the propagation time when CL=0, and dtp represents the capacitive dependence of tp. The following table gives the timing characteristic of different logical gates. Function NAND-3-inputs NOR 2-inputs
Cin 6 Cref 7 Cref
tp0 42 tpref 16 tpref
dtp 3 dtpref 2 dtpref
Cin is the capacitance for each input. In order to simplify calculations, values are given as a function of reference quantities: Cref for the capacitance, tpref for the propagation time and dtpref for the capacitive dependence.
a) Assume that the circuit drives another circuit with CL= 20*Cref. By using the timing characteristic of gates in the table, derive the propagation time of the circuit. (Hint: dtpref * Cref = tpref) Exercise 3
(35 points)
Consider the combinational circuit in the following figure. Write the VHDL code describing this circuit using only concurrent statements.
Assignment 3 - Friday.
Exercise 1: a) P= activity * CY * f * Vdd2 = ¼ * 1fF * 1GHz * 22 = 1uWatt, Activity is ¼ because every 4 cycles, one charge-discharge happens at the output Y. b) P= activity * CY * f * Vdd2 = (1/2n) * 1fF * 1GHz * 22. Hence, the switching power at the output node Y exponentially decreases as the number of inputs increases.
Exercise 2: tp =42*tpref + 3*7*tpref + 16* tpref + 2*20* tpref =119* tpref
Exercise 3:
LIBRARY IEEE; Use ieee.std_logic_1164.all; entity circuit1 is port(a0, a1, a2, a3, b0, b1, b2, b3: in std_logic; AeqB, AltB, AgtB: out std_logic);
end circuit1; architecture logicfunct of circuit1 is signal i0,i1,i2,i3,x1,x2,x3,x4,AeqlB,AgrtB; begin i0
TOPIC: CMOS CIRCUITS & VHDL Exercise 1
(35 points)
a) Consider the AND gate Y=(A AND B), where A, B are the input Boolean variables. Let us also assume that the input pattern AB follows the 2-bit Binary counting pattern, i.e., AB = 00, 01, 10, 11, 00, …, where every 1ns a transition occurs, e.g., from AB=00 to AB=01. Assume that the load capacitance at the output node Y is equal to CY=1fF. Also, we have: VDD=2V. Compute the switching power consumption at the node Y. b) What happens to power, when Y is an n-input AND gate, while the n inputs follow the nbit Binary counting pattern? Exercise 2
(30 points)
Let's consider a combinational function F which drives a circuit with capacitance C L. The propagation time tp through F increases as CL grows and can be expressed as: tp = tp0 + dtp * CL where tp0 is the propagation time when CL=0, and dtp represents the capacitive dependence of tp. The following table gives the timing characteristic of different logical gates. Function NAND-3-inputs NOR 2-inputs
Cin 6 Cref 7 Cref
tp0 42 tpref 16 tpref
dtp 3 dtpref 2 dtpref
Cin is the capacitance for each input. In order to simplify calculations, values are given as a function of reference quantities: Cref for the capacitance, tpref for the propagation time and dtpref for the capacitive dependence.
a) Assume that the circuit drives another circuit with CL= 20*Cref. By using the timing characteristic of gates in the table, derive the propagation time of the circuit. (Hint: dtpref * Cref = tpref) Exercise 3
(35 points)
Consider the combinational circuit in the following figure. Write the VHDL code describing this circuit using only concurrent statements.
Assignment 3 - Friday.
Exercise 1: a) P= activity * CY * f * Vdd2 = ¼ * 1fF * 1GHz * 22 = 1uWatt, Activity is ¼ because every 4 cycles, one charge-discharge happens at the output Y. b) P= activity * CY * f * Vdd2 = (1/2n) * 1fF * 1GHz * 22. Hence, the switching power at the output node Y exponentially decreases as the number of inputs increases.
Exercise 2: tp =42*tpref + 3*7*tpref + 16* tpref + 2*20* tpref =119* tpref
Exercise 3:
LIBRARY IEEE; Use ieee.std_logic_1164.all; entity circuit1 is port(a0, a1, a2, a3, b0, b1, b2, b3: in std_logic; AeqB, AltB, AgtB: out std_logic);
end circuit1; architecture logicfunct of circuit1 is signal i0,i1,i2,i3,x1,x2,x3,x4,AeqlB,AgrtB; begin i0
