high-performace cmos current feedback ... - Semantic Scholar
High-performance CMOS Current Feedback Operational Amplifier Salvatore Pennisi Dipartimento Elettrico Elettronico e dei Sistemi (DIEES) University of Catania Catania, Italy [email protected] Abstract—The higher speed exhibited by the Current-feedback OpAmp, compared to conventional architectures, is mainly due to the superior slew-rate, whereas the constant closed-loop bandwidth relies on a low input resistance value. This last requirement revealed as the principal obstacle to the development of efficient CMOS implementations. A highperformance and robust CMOS current-feedback operational amplifier is proposed in this paper. It is obtained through a feedback configuration, which provides low input resistance and, working in class AB, allows high slew-rate capability. A design using a 0.35-µm process is given and SPICE simulations confirming the overall good performance are also provided.
I.
INTRODUCTION
Current-Feedback Operational Amplifiers (CFOAs) are employed as an alternative to conventional voltage opamps because of their inherent advantages [1-5], which can be summarized into two points. First, the CFOA closed-loop bandwidth is independent of its close-loop gain, provided that the feedback resistance is kept constant [6-7]. Second, the CFOA input and output stages work both in class AB and give high slew-rate values. Advances in bipolar processes (especially in terms of complementary performance of transistors npn and pnp) and the inherent better current-drive capability, leave BJTs as the most suited for the implementation of CFOAs. In fact, several solutions even from commercial manufacturers are now available. More recently, CMOS architectures have also been presented that were focused on a particular performance. Indeed, they provide offset compensation [8], high current-drive capability [9], high-frequency [10] and low-voltage operation [11].
allows a large variation of the closed-loop (amplifier) gain while maintaining constant the bandwidth. Moreover, the amplifier is characterized by good current drive capability and gain-bandwidth product. The proposed architecture is described in Sec. II. Simulations are given in Sec. III. II.
A simplified schematic of the adopted solution is shown in Fig. 1. It is made up of two voltage buffers, one at the input (transistors M1-M20) and the other at the output (transistors M1b-M20b). These buffers are realized from a well-known class AB differential stage [12] that is here used in unity gain. Transistors M16-M17 serve as level shifters to allow the analog ground to be set to (VDD-VSS)/2. The current at the inverting input terminal is mirrored to the highimpedance node at the intermediate stage (M21-M24) which provides the high transresistance gain. Voltage at node A is then buffered to the output by the second buffer. Dominantpole frequency compensation is obtained through capacitor CC and resistor RC introduces a negative zero. The small-signal model of the amplifier is depicted in Fig. 2. Referring to the schematic in Fig. 1, the input resistance, the output resistance and the transresistance gain are
In this paper we propose a CMOS architecture that is robust and achieves overall good performance. The solution is based on a well-known class AB differential amplifier [12], which is here utilized in unity feedback. This section is exploited as input and output stage and yields high slew rate values and low input/output resistance. This last property
0-7803-8834-8/05/$20.00 ©2005 IEEE.
PROPOSED SOLUTION
1573
rin− ≈
rout ≈
g m 4 + g m8 , g m 4 ⋅ g m8
(1)
g m 4b + g m8b , g m 4b ⋅ g m8b
Rt ≈ g m 22 ⋅ rd 22 ⋅ rd 21
(2)
g m 23 ⋅ rd 23 ⋅ rd 24 .
(3)
VDD M18
M9
M20
M19
V
DD
V
DD
V
IN(-)
M16
I BIAS
M2
M3
M4
M7
M8
M17 V
SS
M6
M5
V
M22
M15
M11
V
DD
V
M10b DD
M17b M1b
M2b
M3b
VSS Cc M5b Rc VSS
M6b
M7b
OUT
M4b
A
Vb
SS
VSS M14
DD
M16b
M23
M13
V
M21
DD
IN(+) M1
M20b
M9b
M19b
M10
M24
M12
M8b
M11b
M15b
M14b
VSS
M12b
VSS
Figure 1. Simplified schematic of the proposed current feedback operational amplifier.
The dominant pole and, assuming the CFOA in unity gain, the gain-bandwidth product are 1 ωd = Rt ⋅ CC
VinVin+
(4)
rout Vout i in
rin-
αi
V+
in
C c VA
Rt
VA
in
and
ω GBW =
Figure 2.
Rt rin− + rout
.
(5)
R2
Connecting the CFOA in inverting configuration as shown in Fig. 3, the gain-bandwidth product, which coincides with the closed-loop bandwidth, becomes
ω CL ≈
1
(
R2 + rin−
)
+ rout ⋅ CC
(
rin−
1
)
(7)
rout ⋅ C L
To ensure stability with a prescribed phase margin, PM, capacitor CC must be chosen in order to set ω GBW = ω 2 / tan( PM ) , thus yielding CC = tg ( PM )
rin ⋅ rout
(rin + rout )2
CL
R1
(8)
_ CFOA
(6)
The above equation shows the well-known constantbandwidth property provided that R2 is kept constant and only R1 is varied to achieve the desired closed-loop gain. Moreover, to maximize bandwidth the input/output resistances should be minimized. The worst-case condition form the stability point of view is represented by the unity gain configuration with a pure capacitive load (CL). In this case the second pole is located at the output and its expression is
ω2 =
Small-signal model of the CFOA.
Vin
+
Vout
Figure 3. CFOA in inverting configuration.
III.
SIMULATION RESULTS
The circuit in Fig. 1 was designed and simulated using the model parameters of the 0.35-µm AMS process obtained through EUROPRACTICE. The circuit was powered with 3.3 V, IBIAS was set to 100µA and transistor dimensions are summarized in Table I. Assuming a load capacitor CL of 2pF, we set CC=1.3pF and RC=300Ω. Power dissipation was 5.36mW and systematic input offset was 1.3mV. The input resistance was about 600Ω. The magnitude and phase of the loop gain (with the CFOA in unity gain) is shown in Fig. 4. A DC gain of 74dB and a gain-bandwidth product of 58MHz with a phase margin of 57.5° are observed. The current drive capability of the amplifier in unity gain with a load of 1kΩ is depicted in Fig. 5. A maximum current of 500µA is obtained, which is sufficient to drive the load with a 1-Vpp signal.
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The response of the CFOA in unity gain to an input step of 1Vpp is depicted in Fig. 6. The positive (negative) slew rate is 310 V/µs (340 V/µs). The settling time, at 0.1% of the final value, is 10.4 ns. Figure 7 shows the magnitude of the common-mode rejection ratio, CMRR, and power supply rejection ratio (of the positive power supply), PSRR. Their DC values are 48dB and 43dB, respectively. Both parameters are worst than those usually observed in a conventional voltage amplifier. This is due to the asymmetrical input stage that is less efficient to reject unwanted signals (like common-mode and power supply variations).
A. M. Ismail, A. M. Soliman, “Novel CMOS Current Feedback OpAmp Realisation Suitable for High Frequency Applications,” IEEE Trans. on Circuits and Systems – part I, Vol. 47, No. 6, pp. 918-921, June 2000. [10] B. J. Maundy, I. G. Finvers, P. Aronhime, “Alternative Realizations of CMOS Current Feedback Amplifiers for Low Voltage Applications,” Analog Integrated Circuits and Signal Processing, Vol. 32, pp. 157-168, December 2002. [11] R. Mita, G. Palumbo, S. Pennisi, “Low-Voltage High-Drive CMOS Current Feedback Op-Amp,” accepted for publication in IEEE Trans. on Circuits and Systems – part II. [12] E. Seevinck, R. F. Wassenaar, "A Versatile CMOS Linear Transconductor/Square-law Function Circuit," IEEE J. of Solid-State Circ., Vol. SC-22, pp. 366-377, June 1987. [9]
The input-referred noise voltage spectral density is 10.9 nV/ Hz . TABLE I.
Main performance parameters are summarized in Table II. The constant-bandwidth property was also verified by configuring the CFOA in inverting configuration as in Fig. 3. The feedback resistor R2 was kept constant to 11kΩ and only resistor R1 was varied from 11 kΩ to 1 kΩ to change the gain. Figure 8 shows the magnitude of the simulated gain. IV.
TRANSISTOR ASPECT RATIOS
Transistor M1-M4 M5-M8 M9-M10 M11-M12 M13-M15 M16-M17 M18-M20 M21 M22 M23 M24
CONCLUSION
A high-performance and robust CMOS current-feedback operational amplifier topology was proposed in this paper. A circuit implementation dissipating 5.36mW provided a loop gain of 74 dB with a gain-bandwidth product of 58 MHz. Moreover, slew-rate values better than 300 V/µs were achieved. The simulated performance was in close agreement with expected results.
W/L 80/0.3 140/0.3 90/0.6 240/0.6 100/0.6 180/0.3 90/0.6 20/0.6 120/0.6 40/0.6 160/0.6
REFERENCES [1]
[2]
[3]
[4]
[5]
[6] [7]
[8]
S. A. Mahmoud, A. M. Soliman, “New MOS-C Biquad Filter Using the Current Feedback Operational Amplifier,” IEEE Trans. on Circuits and Systems – part I, Vol. 46, No. 12, pp. 1510-1512, December 1999. A. Soliman, “Applications of the Current Feedback Operational Amplifiers,” Analog Integrated Circuits and Signal Processing, N.11, pp.265-302, 1996. A. K. Singh, R. Senani, “Active-R Design Using CFOA-Poles: New Resonators, Filters, and Oscillators,” IEEE Trans. on Circuits and System – part II, Vol. 48, No. 5, pp. 504-511, May 2001. J. Bayard, M. Ayachi, “OTA- or CFOA-Based LC Sinusoidal Oscillators – Analysis of the Magnitude Stabilization Phenomenon,” IEEE Trans. on Circuits and Systems – part I, Vol. 49, No. 8, pp. 1231-1236, August 2002. A. S. Elwakil, M. P. Kennedy, “Improved Implementation of Chua’s Chaotic Oscillator Using Current Feedback Op Amp,” IEEE Trans. on Circuits and Systems – part I, Vol. 47, No. 1, pp. 76-79, January 2000. G. Palmisano, G. Palumbo, S. Pennisi, CMOS Current Amplifiers, Kluwer Academic Publishers, Boston, 1999. G. Palumbo, S. Pennisi, “Current-Feedback amplifiers versus Voltage Operational Amplifiers,” IEEE Trans. on Circuits and Systems – part I, Vol. 48, No. 5, pp. 617-623, May 2001. A. Assi, M. Sawan, J. Zhu, “An Offset Compensated and High-Gain CMOS Current-Feedback Op-Amp,” IEEE Trans. on Circuits and Systems – part I, Vol. 45, No. 1, pp. 85-90, January 1998.
180
deg dB 90
0 -50 10 2
10 3
10 4
10 5
10 6
10 7
10 8
109
Frequency, Hz Figure 4. Magnitude and phase versus frequency of the loop gain with the CFOA in unity gain configuration.
1575
TABLE II.
800
Parameter DC Power (VDD=3.3V) Syst. Offset DC Loop Gain GBW PM SR+(-) Ts (0.1%) CMRR @DC PSRR @DC THD @100kHz Vin=0.2Vpp @5MHz Input Noise
400
Iout,µA 0 400 800 0
0.5
1.0
1.5
2.0
2.5
3.0
CFOA MAIN PERFORMANCE PARAMETERS
3.5
Vin, V Figure 5. Output current versus input voltage with the amplifier in unity gain. The resistive load is 1kΩ.
2.5
Value 5.36 mW
1.3 mV 74 dB 58 MHz 57.5 ° 310 (340) V/µs 10.4 ns 48 dB 43 dB -83 dB -52 dB 10.9 nV/ Hz
20
V 2.0 0
1.5
1.0
0
10
20
30
40
50
-20
60
Time, ns 102 Figure 6. Time response of the CFOA in unity gain to an input step voltage of 1Vpp.
10 3
10 4
10 5
106
107
10 8
Frequency, Hz Figure 8. Magnitude versus frequency of the closed-loop gain of the inverting configuration. R2 was kept constant to 11kΩ.
50 CMRR
dB 40 PSRR 30
20
10 104
105
106
107
108
109
Frequency, Hz Figure 7. Magnitude versus frequency of the CMRR and PSRR.
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I.
INTRODUCTION
Current-Feedback Operational Amplifiers (CFOAs) are employed as an alternative to conventional voltage opamps because of their inherent advantages [1-5], which can be summarized into two points. First, the CFOA closed-loop bandwidth is independent of its close-loop gain, provided that the feedback resistance is kept constant [6-7]. Second, the CFOA input and output stages work both in class AB and give high slew-rate values. Advances in bipolar processes (especially in terms of complementary performance of transistors npn and pnp) and the inherent better current-drive capability, leave BJTs as the most suited for the implementation of CFOAs. In fact, several solutions even from commercial manufacturers are now available. More recently, CMOS architectures have also been presented that were focused on a particular performance. Indeed, they provide offset compensation [8], high current-drive capability [9], high-frequency [10] and low-voltage operation [11].
allows a large variation of the closed-loop (amplifier) gain while maintaining constant the bandwidth. Moreover, the amplifier is characterized by good current drive capability and gain-bandwidth product. The proposed architecture is described in Sec. II. Simulations are given in Sec. III. II.
A simplified schematic of the adopted solution is shown in Fig. 1. It is made up of two voltage buffers, one at the input (transistors M1-M20) and the other at the output (transistors M1b-M20b). These buffers are realized from a well-known class AB differential stage [12] that is here used in unity gain. Transistors M16-M17 serve as level shifters to allow the analog ground to be set to (VDD-VSS)/2. The current at the inverting input terminal is mirrored to the highimpedance node at the intermediate stage (M21-M24) which provides the high transresistance gain. Voltage at node A is then buffered to the output by the second buffer. Dominantpole frequency compensation is obtained through capacitor CC and resistor RC introduces a negative zero. The small-signal model of the amplifier is depicted in Fig. 2. Referring to the schematic in Fig. 1, the input resistance, the output resistance and the transresistance gain are
In this paper we propose a CMOS architecture that is robust and achieves overall good performance. The solution is based on a well-known class AB differential amplifier [12], which is here utilized in unity feedback. This section is exploited as input and output stage and yields high slew rate values and low input/output resistance. This last property
0-7803-8834-8/05/$20.00 ©2005 IEEE.
PROPOSED SOLUTION
1573
rin− ≈
rout ≈
g m 4 + g m8 , g m 4 ⋅ g m8
(1)
g m 4b + g m8b , g m 4b ⋅ g m8b
Rt ≈ g m 22 ⋅ rd 22 ⋅ rd 21
(2)
g m 23 ⋅ rd 23 ⋅ rd 24 .
(3)
VDD M18
M9
M20
M19
V
DD
V
DD
V
IN(-)
M16
I BIAS
M2
M3
M4
M7
M8
M17 V
SS
M6
M5
V
M22
M15
M11
V
DD
V
M10b DD
M17b M1b
M2b
M3b
VSS Cc M5b Rc VSS
M6b
M7b
OUT
M4b
A
Vb
SS
VSS M14
DD
M16b
M23
M13
V
M21
DD
IN(+) M1
M20b
M9b
M19b
M10
M24
M12
M8b
M11b
M15b
M14b
VSS
M12b
VSS
Figure 1. Simplified schematic of the proposed current feedback operational amplifier.
The dominant pole and, assuming the CFOA in unity gain, the gain-bandwidth product are 1 ωd = Rt ⋅ CC
VinVin+
(4)
rout Vout i in
rin-
αi
V+
in
C c VA
Rt
VA
in
and
ω GBW =
Figure 2.
Rt rin− + rout
.
(5)
R2
Connecting the CFOA in inverting configuration as shown in Fig. 3, the gain-bandwidth product, which coincides with the closed-loop bandwidth, becomes
ω CL ≈
1
(
R2 + rin−
)
+ rout ⋅ CC
(
rin−
1
)
(7)
rout ⋅ C L
To ensure stability with a prescribed phase margin, PM, capacitor CC must be chosen in order to set ω GBW = ω 2 / tan( PM ) , thus yielding CC = tg ( PM )
rin ⋅ rout
(rin + rout )2
CL
R1
(8)
_ CFOA
(6)
The above equation shows the well-known constantbandwidth property provided that R2 is kept constant and only R1 is varied to achieve the desired closed-loop gain. Moreover, to maximize bandwidth the input/output resistances should be minimized. The worst-case condition form the stability point of view is represented by the unity gain configuration with a pure capacitive load (CL). In this case the second pole is located at the output and its expression is
ω2 =
Small-signal model of the CFOA.
Vin
+
Vout
Figure 3. CFOA in inverting configuration.
III.
SIMULATION RESULTS
The circuit in Fig. 1 was designed and simulated using the model parameters of the 0.35-µm AMS process obtained through EUROPRACTICE. The circuit was powered with 3.3 V, IBIAS was set to 100µA and transistor dimensions are summarized in Table I. Assuming a load capacitor CL of 2pF, we set CC=1.3pF and RC=300Ω. Power dissipation was 5.36mW and systematic input offset was 1.3mV. The input resistance was about 600Ω. The magnitude and phase of the loop gain (with the CFOA in unity gain) is shown in Fig. 4. A DC gain of 74dB and a gain-bandwidth product of 58MHz with a phase margin of 57.5° are observed. The current drive capability of the amplifier in unity gain with a load of 1kΩ is depicted in Fig. 5. A maximum current of 500µA is obtained, which is sufficient to drive the load with a 1-Vpp signal.
1574
The response of the CFOA in unity gain to an input step of 1Vpp is depicted in Fig. 6. The positive (negative) slew rate is 310 V/µs (340 V/µs). The settling time, at 0.1% of the final value, is 10.4 ns. Figure 7 shows the magnitude of the common-mode rejection ratio, CMRR, and power supply rejection ratio (of the positive power supply), PSRR. Their DC values are 48dB and 43dB, respectively. Both parameters are worst than those usually observed in a conventional voltage amplifier. This is due to the asymmetrical input stage that is less efficient to reject unwanted signals (like common-mode and power supply variations).
A. M. Ismail, A. M. Soliman, “Novel CMOS Current Feedback OpAmp Realisation Suitable for High Frequency Applications,” IEEE Trans. on Circuits and Systems – part I, Vol. 47, No. 6, pp. 918-921, June 2000. [10] B. J. Maundy, I. G. Finvers, P. Aronhime, “Alternative Realizations of CMOS Current Feedback Amplifiers for Low Voltage Applications,” Analog Integrated Circuits and Signal Processing, Vol. 32, pp. 157-168, December 2002. [11] R. Mita, G. Palumbo, S. Pennisi, “Low-Voltage High-Drive CMOS Current Feedback Op-Amp,” accepted for publication in IEEE Trans. on Circuits and Systems – part II. [12] E. Seevinck, R. F. Wassenaar, "A Versatile CMOS Linear Transconductor/Square-law Function Circuit," IEEE J. of Solid-State Circ., Vol. SC-22, pp. 366-377, June 1987. [9]
The input-referred noise voltage spectral density is 10.9 nV/ Hz . TABLE I.
Main performance parameters are summarized in Table II. The constant-bandwidth property was also verified by configuring the CFOA in inverting configuration as in Fig. 3. The feedback resistor R2 was kept constant to 11kΩ and only resistor R1 was varied from 11 kΩ to 1 kΩ to change the gain. Figure 8 shows the magnitude of the simulated gain. IV.
TRANSISTOR ASPECT RATIOS
Transistor M1-M4 M5-M8 M9-M10 M11-M12 M13-M15 M16-M17 M18-M20 M21 M22 M23 M24
CONCLUSION
A high-performance and robust CMOS current-feedback operational amplifier topology was proposed in this paper. A circuit implementation dissipating 5.36mW provided a loop gain of 74 dB with a gain-bandwidth product of 58 MHz. Moreover, slew-rate values better than 300 V/µs were achieved. The simulated performance was in close agreement with expected results.
W/L 80/0.3 140/0.3 90/0.6 240/0.6 100/0.6 180/0.3 90/0.6 20/0.6 120/0.6 40/0.6 160/0.6
REFERENCES [1]
[2]
[3]
[4]
[5]
[6] [7]
[8]
S. A. Mahmoud, A. M. Soliman, “New MOS-C Biquad Filter Using the Current Feedback Operational Amplifier,” IEEE Trans. on Circuits and Systems – part I, Vol. 46, No. 12, pp. 1510-1512, December 1999. A. Soliman, “Applications of the Current Feedback Operational Amplifiers,” Analog Integrated Circuits and Signal Processing, N.11, pp.265-302, 1996. A. K. Singh, R. Senani, “Active-R Design Using CFOA-Poles: New Resonators, Filters, and Oscillators,” IEEE Trans. on Circuits and System – part II, Vol. 48, No. 5, pp. 504-511, May 2001. J. Bayard, M. Ayachi, “OTA- or CFOA-Based LC Sinusoidal Oscillators – Analysis of the Magnitude Stabilization Phenomenon,” IEEE Trans. on Circuits and Systems – part I, Vol. 49, No. 8, pp. 1231-1236, August 2002. A. S. Elwakil, M. P. Kennedy, “Improved Implementation of Chua’s Chaotic Oscillator Using Current Feedback Op Amp,” IEEE Trans. on Circuits and Systems – part I, Vol. 47, No. 1, pp. 76-79, January 2000. G. Palmisano, G. Palumbo, S. Pennisi, CMOS Current Amplifiers, Kluwer Academic Publishers, Boston, 1999. G. Palumbo, S. Pennisi, “Current-Feedback amplifiers versus Voltage Operational Amplifiers,” IEEE Trans. on Circuits and Systems – part I, Vol. 48, No. 5, pp. 617-623, May 2001. A. Assi, M. Sawan, J. Zhu, “An Offset Compensated and High-Gain CMOS Current-Feedback Op-Amp,” IEEE Trans. on Circuits and Systems – part I, Vol. 45, No. 1, pp. 85-90, January 1998.
180
deg dB 90
0 -50 10 2
10 3
10 4
10 5
10 6
10 7
10 8
109
Frequency, Hz Figure 4. Magnitude and phase versus frequency of the loop gain with the CFOA in unity gain configuration.
1575
TABLE II.
800
Parameter DC Power (VDD=3.3V) Syst. Offset DC Loop Gain GBW PM SR+(-) Ts (0.1%) CMRR @DC PSRR @DC THD @100kHz Vin=0.2Vpp @5MHz Input Noise
400
Iout,µA 0 400 800 0
0.5
1.0
1.5
2.0
2.5
3.0
CFOA MAIN PERFORMANCE PARAMETERS
3.5
Vin, V Figure 5. Output current versus input voltage with the amplifier in unity gain. The resistive load is 1kΩ.
2.5
Value 5.36 mW
1.3 mV 74 dB 58 MHz 57.5 ° 310 (340) V/µs 10.4 ns 48 dB 43 dB -83 dB -52 dB 10.9 nV/ Hz
20
V 2.0 0
1.5
1.0
0
10
20
30
40
50
-20
60
Time, ns 102 Figure 6. Time response of the CFOA in unity gain to an input step voltage of 1Vpp.
10 3
10 4
10 5
106
107
10 8
Frequency, Hz Figure 8. Magnitude versus frequency of the closed-loop gain of the inverting configuration. R2 was kept constant to 11kΩ.
50 CMRR
dB 40 PSRR 30
20
10 104
105
106
107
108
109
Frequency, Hz Figure 7. Magnitude versus frequency of the CMRR and PSRR.
1576
