Mismatch Compensation of CMOS Current Mirrors ... - Semantic Scholar
Mismatch Compensation of CMOS Current Mirrors Using Floating-Gate Transistors Timir Datta, Pamela Abshire School of Electrical and Computer Engineering University of Maryland College Park, Maryland 20740, USA Email: [email protected], [email protected]
Abstract— The simple CMOS current mirror is a fundamental compositional element which is employed in a wide variety of analog and digital circuit designs. The use of CMOS current mirrors is appealing to circuit designers given the low cost associated with CMOS fabrication and the inherent simplicity of operation. Unfortunately, the simplicity of the CMOS current mirror makes it particularly susceptible to device mismatch due to process variations. In recent years the use of floating gate transistors for mismatch compensation has become increasingly popular. We report on our observations regarding the efficacy of this technique in both weak and strong inversion and present analytical and simulated results quantifying these observations. The central result is that although compensation using floating gates works well for correcting mismatch for subthreshold operation, similar compensation in above threshold operation results in the introduction of previously unseen mismatch effects.
I. I NTRODUCTION The proper operation of many types of circuits relies on the precision and accurate operation of the current mirror. Previous work has shown that current mirrors employing MOSFETs have a much greater degree of mismatch than those constructed with BJTs [1], with a likely cause being the great effect that surface charge anomalies have on the MOS current flow mechanism. However, the use of CMOS processes remains very popular given their widespread availability and the low cost associated with fabrication. Although modern commercial CMOS processes are very mature, and advancing rapidly, it is generally accepted that as feature sizes decrease, the effects of process variation become even more significant than in the past. The simple CMOS current mirror is a two transistor circuit. For the purposes of this discussion we will focus on the NMOS version since it has been shown that PMOS based circuits suffer from a greater degree of mismatch due to higher mobility variations and poorer gate oxide capacitance matching [2]. The results discussed here are directly relevant to the operation of both NMOS and PMOS current mirrors. The NMOS current mirror is shown in Fig(1), and in the case of ideal operation (neglecting the effects of mismatch and channel length modulation), Iout = Iin . In section II we discuss the typical sources of mismatch and the techniques which are commonly used for compensation. Section III outlines important mismatch parameters, develops
978-1-4244-3828-0/09/$25.00 ©2009 IEEE
Fig. 1.
NMOS current mirror
the SPICE models used for simulation, and presents the results of our analysis and simulation of mismatch in both strong and weak inversion. Section IV introduces the floating gate current mirror, discusses the tuning capabilities afforded by such a structure, and shows the results of our analysis and simulation of the mismatch compensated current mirror for both regimes of operation. Finally, Section V summarizes our findings. II. S OURCES OF M ISMATCH Mismatch amongst transistors of equivalent geometry arises primarily from localized process variations such as fluctuations in doping intensity and device dimensions, impurities in the silicon, surface states, and defect traps. A number of circuit layout techniques have been suggested to mitigate the occurrence of mismatch. These include the use of large geometries, multiple finger elements, and common centroid layout methods [3], [4]. All of these methods are effective to some degree, but still depend heavily on the quality of the fabrication process. There are also circuit design techniques which can be used to increase the accuracy of current mirror operation [5], [1], but these methods generally result in significantly increased complexity. Here we have chosen to focus on mismatch compensation for the principal sources of mismatch in the MOS device using the floating gate current mirror. III. M ODELING THE E FFECTS OF M ISMATCH The three parameters best suited for modeling mismatch are the threshold voltage Vth , subthreshold slope κ and the transconductance β [1]. Another factor which can be a source of mismatch is the channel length modulation parameter λ, but the effect of variations in λ only come into play at high drain voltages, and more importantly when the drain voltages of the two transistors differ. In this paper we will neglect the effect
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of variations in λ, since it will allow us to look at some of the more fundamental causes of mismatch which are present when all other operating conditions are equivalent.
0.02
SQRT(ID)
0.015
To show the effects of mismatch using simulation, we have developed two sets of 100 different BSIM3v3 SPICE models. The first of which represents uniform distributions of Vth mismatch and β mismatch, using the parameters Vth0 and µ0 respectively. Ten values of 4Vth0 are used, ranging from −100mV to +100mV . Correspondingly, ten values of 2 cm2 4µ0 are also used, ranging from −100 cm V s to +100 V s . The second set of models were developed in a similar manner to represent uniform distributions of I0 mismatch (using µ0 2 cm2 ranging from −100 cm V s to +100 V s ) and κ mismatch (using the Nf actor parameter, ranging from -20% to +20%). The ID VG characteristic of a MOS transistor was simulated for all possible combinations of these parameters within each model set.
0.005 0
D
GS
th
where A = β2 W L is the transconductance parameter and Vth is the threshold voltage. The input characteristic for the current mirror becomes Iin = A(Vin − Vth )2 (2)
1
1.5 VGS
2
2.5
3
The effects of mismatch in strong inversion
The transfer function for Iout /Iin is given by 4κV −4V in th 4I0 Iout UT = 1+ e Iin I0
(8)
The effects of mismatch for subthreshold operation in the saturation regime are shown in Fig (3), which is a log I vs V plot. Whereas the voltage offsets arising from 4Vth are easily observed in Fig (3a), the errors introduced by 4I0 are not as apparent as in the above threshold case. The horizontal shift is much smaller for the case of 4I0 and 4κ mismatch in Fig (3b), but the variation in gain becomes significant. −5
10
A −10
ID
Ignoring second order terms, the transfer function for Iout /Iin can be approximated by r Iout A 4A ≈1+ −2 4Vth (4) Iin A Iin The effects of mismatch for above threshold operation √ in the saturation regime are shown in Fig (2), which is a I vs V plot. The mismatch 4Vth results in horizontal displacements of the characteristics along the x-axis (i.e., voltage offsets), whereas the mismatch 4A results in characteristics that exhibit different slopes (i.e., gain error).
10
−15
10
−5
0
0.2
0.4
0.2
0.4
10
VGS
0.6
0.8
1
0.6
0.8
1
B
ID
−10
10
−15
B. Mismatch in Weak Inversion
10
Neglecting channel length modulation and body effect, the drain current for subthreshold operation in the saturation regime is given by κVGS −Vth UT (5) ID = I0 e where I0 is the pre-exponential scaling factor, κ is the subthreshold slope factor,Vth is the threshold voltage, and UT is the thermal voltage. The input characteristic becomes κVin −Vth UT
0.5
The output characteristic including the effects of mismatch is given by (κ+4κ)Vin −Vth −4Vth UT Iout = (I0 + 4I0 )e (7)
The output characteristic including the effects of mismatch is given by Iout = (A + 4A)(Vin − Vth − 4Vth )2 (3)
Iin = I0 e
0
Fig. 2.
A. Mismatch in Strong Inversion Neglecting channel length modulation, the drain current of an NMOS operating in the above threshold saturation regime is given by I = A(V − V )2 (1)
0.01
(6)
0
VGS
Fig. 3. The effects of mismatch in weak inversion A: 4Vth and 4I0 mismatch, B:4κ and 4I0 mismatch
IV. M ISMATCH C OMPENSATION U SING F LOATING G ATES A. Floating Gate Current Mirror Floating gate transistors can be fabricated in any standard CMOS process. The gate of the transistor is isolated by an
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√ operating point, the resultant I vs V plots all pass though the bias point at which the correction factor was computed. This is shown in Fig (5) for curves that have been corrected at Vin = 1.75.
0.02 0.015 SQRT(ID)
electrically insulating oxide layer, and thus charge may be stored on the gate in a non-volatile manner. Any stored charge produces a voltage offset VCorr which adds in series with the externally applied control voltage Vin . The charge stored on the floating gate can be modulated using either impactionized hot electron injection to decrease the potential [6], [7], or Fowler-Nordheim tunneling to increase the potential [8]. Inputs may be applied through capacitive coupling to this floating node. The capacitive inputs may be implemented using any capacitor, including MOSCAPs, poly-poly capacitors, or other dielectric capacitors available in a particular technology. The only requirement is that there be minimal leakage current onto the floating node. It is sometimes convenient to implement the input coupling capacitor using a linear polypoly capacitor which is available in many CMOS technologies. The floating gate current mirror is shown in Fig (4), where Vx = Vin − VCorr .
0.01 0.005 0
0
Fig. 5.
Fig. 4.
Floating gate NMOS current mirror
B. Tuning for Mismatch Compensation Since mismatch is present in several parameters, ideally one must introduce corrections for each of these parameters. However, the use of floating gates allows for the tuning of only one parameter (4Vth ). We have found empirically that although this works well for weak inversion, in the case of strong inversion compensation results in the introduction of unanticipated gain variations. This is further explored in the following sections. C. Compensation in Strong Inversion
1
1.5 VGS
2
2.5
3
Mismatch correction for strong inversion
Here we find that although floating gate MOSFETs allow for corrections to 4Vth mismatch, the 4A mismatch cannot be compensated in a similar manner by simply introducing an offset to the gate voltage. Furthermore, looking at Fig (5) it can be observed that although the characteristics all pass through the same bias point, there is a variation in slopes that causes them to diverge away from that bias point. Thus, compensation is best at a particular operating point and decreases in efficacy away from that point. What is not as obvious is that correcting for transconductance mismatch leads to an increase in gain variations. This effect is quantified below in Fig (6). Here it can be seen that for a given value of 4A, correction of the threshold mismatch reduces gain variation (i.e., the standard deviation of the corrected gain is lower than the uncorrected gain). However, for a given value of 4Vth , correction of the transconductance mismatch increases the gain variations.
When compensated, the output characteristic of the floating gate current mirror for above threshold becomes where VCorr is the voltage stored across the capacitor. Setting Iout − Iin = 0 and solving for VCorr gives an expression for the required correction factor as a function of A, 4A, Iin , and 4Vth . p 1 1 VCorr = −4Vth + Iin √ − √ (10) A + 4A A Using a first order Taylor series expansion this can be approximated as r Iin 4A VCorr ≈ −4Vth + 1+ (11) A 2A Once the correct value of VCorr is introduced for a particular
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1.5 std(Gain)
(9)
Uncorrected Corrected
−4
x 10
1 0.5 0 −100 −4 x 10 5
std(Gain)
Iout = (A + 4A)(Vin − Vth − 4Vth − VCorr )2
0.5
100
−0.05
0.1
4
3 −0.1
Fig. 6.
−50 0 50 Transconductance Mismatch
0 Vth Mismatch
0.05
Standard deviation of gain for strong inversion
Uncorrected Corrected
D. Compensation in Weak Inversion 1.3 std(Gain)
For subthreshold operation, the introduction of a floating gate at the output transistor gives the following output characteristic. (κ+4κ)Vin −Vth −4Vth −VCorr UT Iout = (I0 + 4I0 )e (12)
1.25
1.2 −150
Setting Iout − Iin = 0 and solving for VCorr gives an expression for the required correction factor. ! 1 (13) VCorr = 4κVin − 4Vth − UT ln 0 1 + 4I I0 Once the correct value of VCorr is introduced for a particular operating point the resultant log I vs V plot is shown in Fig (7). It can be observed from Fig (7a) that compensation nearly eliminates variations due only to 4I0 and 4Vth mismatch. However, when 4κ mismatch occurs compensation only allows for matching at the operating point. Fig (7b) shows that since the floating gate compensation results in a shifted curve the effective gain at the operating point is altered. Fig (8) quantifies this result, where it can be seen that compensation in the presence of 4κ mismatch has significant effect on gain.
std(Gain)
0.06
100
150
0.04 0.02
Fig. 8.
0.15
0.2
Standard deviation of gain for weak inversion
for transconductance mismatch in strong inversion and for κ mismatch in weak inversion. We conclude that this technique overcomes the dominant sources of mismatch in weak inversion, and that its use in strong inversion suppresses mismatch but results in the introduction of gain errors.
We thank Somashekar Bangalore Prakash and Yanyi Liu Wong, for their careful experimental work that served to motivate this effort,and anonymous reviewers for helpful comments in improving the manuscript.
−10
ID
0 50 I0 Mismatch
VI. ACKNOWLEDGMENTS A
10
−15
10
R EFERENCES 0
0.2
0.4
10
VGS
0.6
0.8
1
B −10
ID
−50
0 −0.2 −0.15 −0.1 −0.05 0 0.05 0.1 NFactor Mismatch
−5
10
−5
−100
10
−15
10
0
0.2
0.4
VGS
0.6
0.8
1
Fig. 7. Mismatch correction for weak inversion A: 4Vth and 4I0 mismatch, B:4κ and 4I0 mismatch
Thus we find that I0 and Vth mismatch are well compensated by the use of a floating gate, but that κ mismatch is poorly compensated and leads to gain variations. V. C ONCLUSION Using analysis and simulation, we have shown that the use of floating gate transistors in CMOS current mirrors allows for adequate mismatch compensation in both weak and strong inversion for signals about a particular operating point. If the current mirrors are exercised over a wide dynamic range, this method compensates well for Vth mismatch and for I0 mismatch in weak inversion, but fails to compensate
[1] S. Milam and P. Allen, “Accurate two-transistor current mirrors,” Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on, vol. 1, pp. 151–154 vol.1, Aug 1994. [2] K. Lakshmikumar, R. Hadaway, and M. Copeland, “Characterisation and modeling of mismatch in mos transistors for precision analog design,” Solid-State Circuits, IEEE Journal of, vol. 21, no. 6, pp. 1057–1066, Dec 1986. [3] D. Long, X. Hong, and S. Dong, “Optimal two-dimension common centroid layout generation for mos transistors unit-circuit,” Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, pp. 2999– 3002 Vol. 3, May 2005. [4] T. Gabara and P. Metz, “Improved dc matching of cmos circuits using rotational symmetry,” ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International, pp. P10–3/1–3, Sep 1991. [5] G. Wegmann and E. Vittoz, “Analysis and improvements of accurate dynamic current mirrors,” Solid-State Circuits, IEEE Journal of, vol. 25, no. 3, pp. 699–706, Jun 1990. [6] P. Hasler, B. Minch, and C. Diorio, “An autozeroing floating-gate amplifier,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 48, no. 1, pp. 74–82, Jan 2001. [7] T. Constandinou, J. Georgiou, and C. Toumazou, “An auto-input-offset removing floating gate pseudo-differential transconductor,” Circuits and Systems, 2003. ISCAS ’03. Proceedings of the 2003 International Symposium on, vol. 1, pp. I–169–I–172 vol.1, May 2003. [8] W. D. Brown and J. Brewer, A Comprehensive Guide to Understanding and Using NVSM Devices. John Wiley & Sons, 1998.
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Abstract— The simple CMOS current mirror is a fundamental compositional element which is employed in a wide variety of analog and digital circuit designs. The use of CMOS current mirrors is appealing to circuit designers given the low cost associated with CMOS fabrication and the inherent simplicity of operation. Unfortunately, the simplicity of the CMOS current mirror makes it particularly susceptible to device mismatch due to process variations. In recent years the use of floating gate transistors for mismatch compensation has become increasingly popular. We report on our observations regarding the efficacy of this technique in both weak and strong inversion and present analytical and simulated results quantifying these observations. The central result is that although compensation using floating gates works well for correcting mismatch for subthreshold operation, similar compensation in above threshold operation results in the introduction of previously unseen mismatch effects.
I. I NTRODUCTION The proper operation of many types of circuits relies on the precision and accurate operation of the current mirror. Previous work has shown that current mirrors employing MOSFETs have a much greater degree of mismatch than those constructed with BJTs [1], with a likely cause being the great effect that surface charge anomalies have on the MOS current flow mechanism. However, the use of CMOS processes remains very popular given their widespread availability and the low cost associated with fabrication. Although modern commercial CMOS processes are very mature, and advancing rapidly, it is generally accepted that as feature sizes decrease, the effects of process variation become even more significant than in the past. The simple CMOS current mirror is a two transistor circuit. For the purposes of this discussion we will focus on the NMOS version since it has been shown that PMOS based circuits suffer from a greater degree of mismatch due to higher mobility variations and poorer gate oxide capacitance matching [2]. The results discussed here are directly relevant to the operation of both NMOS and PMOS current mirrors. The NMOS current mirror is shown in Fig(1), and in the case of ideal operation (neglecting the effects of mismatch and channel length modulation), Iout = Iin . In section II we discuss the typical sources of mismatch and the techniques which are commonly used for compensation. Section III outlines important mismatch parameters, develops
978-1-4244-3828-0/09/$25.00 ©2009 IEEE
Fig. 1.
NMOS current mirror
the SPICE models used for simulation, and presents the results of our analysis and simulation of mismatch in both strong and weak inversion. Section IV introduces the floating gate current mirror, discusses the tuning capabilities afforded by such a structure, and shows the results of our analysis and simulation of the mismatch compensated current mirror for both regimes of operation. Finally, Section V summarizes our findings. II. S OURCES OF M ISMATCH Mismatch amongst transistors of equivalent geometry arises primarily from localized process variations such as fluctuations in doping intensity and device dimensions, impurities in the silicon, surface states, and defect traps. A number of circuit layout techniques have been suggested to mitigate the occurrence of mismatch. These include the use of large geometries, multiple finger elements, and common centroid layout methods [3], [4]. All of these methods are effective to some degree, but still depend heavily on the quality of the fabrication process. There are also circuit design techniques which can be used to increase the accuracy of current mirror operation [5], [1], but these methods generally result in significantly increased complexity. Here we have chosen to focus on mismatch compensation for the principal sources of mismatch in the MOS device using the floating gate current mirror. III. M ODELING THE E FFECTS OF M ISMATCH The three parameters best suited for modeling mismatch are the threshold voltage Vth , subthreshold slope κ and the transconductance β [1]. Another factor which can be a source of mismatch is the channel length modulation parameter λ, but the effect of variations in λ only come into play at high drain voltages, and more importantly when the drain voltages of the two transistors differ. In this paper we will neglect the effect
1823
of variations in λ, since it will allow us to look at some of the more fundamental causes of mismatch which are present when all other operating conditions are equivalent.
0.02
SQRT(ID)
0.015
To show the effects of mismatch using simulation, we have developed two sets of 100 different BSIM3v3 SPICE models. The first of which represents uniform distributions of Vth mismatch and β mismatch, using the parameters Vth0 and µ0 respectively. Ten values of 4Vth0 are used, ranging from −100mV to +100mV . Correspondingly, ten values of 2 cm2 4µ0 are also used, ranging from −100 cm V s to +100 V s . The second set of models were developed in a similar manner to represent uniform distributions of I0 mismatch (using µ0 2 cm2 ranging from −100 cm V s to +100 V s ) and κ mismatch (using the Nf actor parameter, ranging from -20% to +20%). The ID VG characteristic of a MOS transistor was simulated for all possible combinations of these parameters within each model set.
0.005 0
D
GS
th
where A = β2 W L is the transconductance parameter and Vth is the threshold voltage. The input characteristic for the current mirror becomes Iin = A(Vin − Vth )2 (2)
1
1.5 VGS
2
2.5
3
The effects of mismatch in strong inversion
The transfer function for Iout /Iin is given by 4κV −4V in th 4I0 Iout UT = 1+ e Iin I0
(8)
The effects of mismatch for subthreshold operation in the saturation regime are shown in Fig (3), which is a log I vs V plot. Whereas the voltage offsets arising from 4Vth are easily observed in Fig (3a), the errors introduced by 4I0 are not as apparent as in the above threshold case. The horizontal shift is much smaller for the case of 4I0 and 4κ mismatch in Fig (3b), but the variation in gain becomes significant. −5
10
A −10
ID
Ignoring second order terms, the transfer function for Iout /Iin can be approximated by r Iout A 4A ≈1+ −2 4Vth (4) Iin A Iin The effects of mismatch for above threshold operation √ in the saturation regime are shown in Fig (2), which is a I vs V plot. The mismatch 4Vth results in horizontal displacements of the characteristics along the x-axis (i.e., voltage offsets), whereas the mismatch 4A results in characteristics that exhibit different slopes (i.e., gain error).
10
−15
10
−5
0
0.2
0.4
0.2
0.4
10
VGS
0.6
0.8
1
0.6
0.8
1
B
ID
−10
10
−15
B. Mismatch in Weak Inversion
10
Neglecting channel length modulation and body effect, the drain current for subthreshold operation in the saturation regime is given by κVGS −Vth UT (5) ID = I0 e where I0 is the pre-exponential scaling factor, κ is the subthreshold slope factor,Vth is the threshold voltage, and UT is the thermal voltage. The input characteristic becomes κVin −Vth UT
0.5
The output characteristic including the effects of mismatch is given by (κ+4κ)Vin −Vth −4Vth UT Iout = (I0 + 4I0 )e (7)
The output characteristic including the effects of mismatch is given by Iout = (A + 4A)(Vin − Vth − 4Vth )2 (3)
Iin = I0 e
0
Fig. 2.
A. Mismatch in Strong Inversion Neglecting channel length modulation, the drain current of an NMOS operating in the above threshold saturation regime is given by I = A(V − V )2 (1)
0.01
(6)
0
VGS
Fig. 3. The effects of mismatch in weak inversion A: 4Vth and 4I0 mismatch, B:4κ and 4I0 mismatch
IV. M ISMATCH C OMPENSATION U SING F LOATING G ATES A. Floating Gate Current Mirror Floating gate transistors can be fabricated in any standard CMOS process. The gate of the transistor is isolated by an
1824
√ operating point, the resultant I vs V plots all pass though the bias point at which the correction factor was computed. This is shown in Fig (5) for curves that have been corrected at Vin = 1.75.
0.02 0.015 SQRT(ID)
electrically insulating oxide layer, and thus charge may be stored on the gate in a non-volatile manner. Any stored charge produces a voltage offset VCorr which adds in series with the externally applied control voltage Vin . The charge stored on the floating gate can be modulated using either impactionized hot electron injection to decrease the potential [6], [7], or Fowler-Nordheim tunneling to increase the potential [8]. Inputs may be applied through capacitive coupling to this floating node. The capacitive inputs may be implemented using any capacitor, including MOSCAPs, poly-poly capacitors, or other dielectric capacitors available in a particular technology. The only requirement is that there be minimal leakage current onto the floating node. It is sometimes convenient to implement the input coupling capacitor using a linear polypoly capacitor which is available in many CMOS technologies. The floating gate current mirror is shown in Fig (4), where Vx = Vin − VCorr .
0.01 0.005 0
0
Fig. 5.
Fig. 4.
Floating gate NMOS current mirror
B. Tuning for Mismatch Compensation Since mismatch is present in several parameters, ideally one must introduce corrections for each of these parameters. However, the use of floating gates allows for the tuning of only one parameter (4Vth ). We have found empirically that although this works well for weak inversion, in the case of strong inversion compensation results in the introduction of unanticipated gain variations. This is further explored in the following sections. C. Compensation in Strong Inversion
1
1.5 VGS
2
2.5
3
Mismatch correction for strong inversion
Here we find that although floating gate MOSFETs allow for corrections to 4Vth mismatch, the 4A mismatch cannot be compensated in a similar manner by simply introducing an offset to the gate voltage. Furthermore, looking at Fig (5) it can be observed that although the characteristics all pass through the same bias point, there is a variation in slopes that causes them to diverge away from that bias point. Thus, compensation is best at a particular operating point and decreases in efficacy away from that point. What is not as obvious is that correcting for transconductance mismatch leads to an increase in gain variations. This effect is quantified below in Fig (6). Here it can be seen that for a given value of 4A, correction of the threshold mismatch reduces gain variation (i.e., the standard deviation of the corrected gain is lower than the uncorrected gain). However, for a given value of 4Vth , correction of the transconductance mismatch increases the gain variations.
When compensated, the output characteristic of the floating gate current mirror for above threshold becomes where VCorr is the voltage stored across the capacitor. Setting Iout − Iin = 0 and solving for VCorr gives an expression for the required correction factor as a function of A, 4A, Iin , and 4Vth . p 1 1 VCorr = −4Vth + Iin √ − √ (10) A + 4A A Using a first order Taylor series expansion this can be approximated as r Iin 4A VCorr ≈ −4Vth + 1+ (11) A 2A Once the correct value of VCorr is introduced for a particular
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1.5 std(Gain)
(9)
Uncorrected Corrected
−4
x 10
1 0.5 0 −100 −4 x 10 5
std(Gain)
Iout = (A + 4A)(Vin − Vth − 4Vth − VCorr )2
0.5
100
−0.05
0.1
4
3 −0.1
Fig. 6.
−50 0 50 Transconductance Mismatch
0 Vth Mismatch
0.05
Standard deviation of gain for strong inversion
Uncorrected Corrected
D. Compensation in Weak Inversion 1.3 std(Gain)
For subthreshold operation, the introduction of a floating gate at the output transistor gives the following output characteristic. (κ+4κ)Vin −Vth −4Vth −VCorr UT Iout = (I0 + 4I0 )e (12)
1.25
1.2 −150
Setting Iout − Iin = 0 and solving for VCorr gives an expression for the required correction factor. ! 1 (13) VCorr = 4κVin − 4Vth − UT ln 0 1 + 4I I0 Once the correct value of VCorr is introduced for a particular operating point the resultant log I vs V plot is shown in Fig (7). It can be observed from Fig (7a) that compensation nearly eliminates variations due only to 4I0 and 4Vth mismatch. However, when 4κ mismatch occurs compensation only allows for matching at the operating point. Fig (7b) shows that since the floating gate compensation results in a shifted curve the effective gain at the operating point is altered. Fig (8) quantifies this result, where it can be seen that compensation in the presence of 4κ mismatch has significant effect on gain.
std(Gain)
0.06
100
150
0.04 0.02
Fig. 8.
0.15
0.2
Standard deviation of gain for weak inversion
for transconductance mismatch in strong inversion and for κ mismatch in weak inversion. We conclude that this technique overcomes the dominant sources of mismatch in weak inversion, and that its use in strong inversion suppresses mismatch but results in the introduction of gain errors.
We thank Somashekar Bangalore Prakash and Yanyi Liu Wong, for their careful experimental work that served to motivate this effort,and anonymous reviewers for helpful comments in improving the manuscript.
−10
ID
0 50 I0 Mismatch
VI. ACKNOWLEDGMENTS A
10
−15
10
R EFERENCES 0
0.2
0.4
10
VGS
0.6
0.8
1
B −10
ID
−50
0 −0.2 −0.15 −0.1 −0.05 0 0.05 0.1 NFactor Mismatch
−5
10
−5
−100
10
−15
10
0
0.2
0.4
VGS
0.6
0.8
1
Fig. 7. Mismatch correction for weak inversion A: 4Vth and 4I0 mismatch, B:4κ and 4I0 mismatch
Thus we find that I0 and Vth mismatch are well compensated by the use of a floating gate, but that κ mismatch is poorly compensated and leads to gain variations. V. C ONCLUSION Using analysis and simulation, we have shown that the use of floating gate transistors in CMOS current mirrors allows for adequate mismatch compensation in both weak and strong inversion for signals about a particular operating point. If the current mirrors are exercised over a wide dynamic range, this method compensates well for Vth mismatch and for I0 mismatch in weak inversion, but fails to compensate
[1] S. Milam and P. Allen, “Accurate two-transistor current mirrors,” Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on, vol. 1, pp. 151–154 vol.1, Aug 1994. [2] K. Lakshmikumar, R. Hadaway, and M. Copeland, “Characterisation and modeling of mismatch in mos transistors for precision analog design,” Solid-State Circuits, IEEE Journal of, vol. 21, no. 6, pp. 1057–1066, Dec 1986. [3] D. Long, X. Hong, and S. Dong, “Optimal two-dimension common centroid layout generation for mos transistors unit-circuit,” Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, pp. 2999– 3002 Vol. 3, May 2005. [4] T. Gabara and P. Metz, “Improved dc matching of cmos circuits using rotational symmetry,” ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International, pp. P10–3/1–3, Sep 1991. [5] G. Wegmann and E. Vittoz, “Analysis and improvements of accurate dynamic current mirrors,” Solid-State Circuits, IEEE Journal of, vol. 25, no. 3, pp. 699–706, Jun 1990. [6] P. Hasler, B. Minch, and C. Diorio, “An autozeroing floating-gate amplifier,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 48, no. 1, pp. 74–82, Jan 2001. [7] T. Constandinou, J. Georgiou, and C. Toumazou, “An auto-input-offset removing floating gate pseudo-differential transconductor,” Circuits and Systems, 2003. ISCAS ’03. Proceedings of the 2003 International Symposium on, vol. 1, pp. I–169–I–172 vol.1, May 2003. [8] W. D. Brown and J. Brewer, A Comprehensive Guide to Understanding and Using NVSM Devices. John Wiley & Sons, 1998.
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